Re: [PATCH v2 11/23] target/loongarch: Scrutinise TCG vector translation for 32 bit build

[Richard Henderson]

On 12/26/24 13:19, Jiaxun Yang wrote:
> @@ -4850,12 +4852,12 @@ static bool gen_g2x(DisasContext *ctx, arg_vr_i *a, 
> MemOp mop,
>       return gen_g2v_vl(ctx, a, 32, mop, func);
>   }
>   
> -TRANS(vinsgr2vr_b, LSX, gen_g2v, MO_8, tcg_gen_st8_i64)
> -TRANS(vinsgr2vr_h, LSX, gen_g2v, MO_16, tcg_gen_st16_i64)
> -TRANS(vinsgr2vr_w, LSX, gen_g2v, MO_32, tcg_gen_st32_i64)
> -TRANS(vinsgr2vr_d, LSX, gen_g2v, MO_64, tcg_gen_st_i64)
> -TRANS(xvinsgr2vr_w, LASX, gen_g2x, MO_32, tcg_gen_st32_i64)
> -TRANS(xvinsgr2vr_d, LASX, gen_g2x, MO_64, tcg_gen_st_i64)
> +TRANS(vinsgr2vr_b, LSX, gen_g2v, MO_8, tcg_gen_st8_tl)
> +TRANS(vinsgr2vr_h, LSX, gen_g2v, MO_16, tcg_gen_st16_tl)
> +TRANS(vinsgr2vr_w, LSX, gen_g2v, MO_32, tcg_gen_st32_tl)
> +TRANS(vinsgr2vr_d, LSX, gen_g2v, MO_64, tcg_gen_st_tl)
> +TRANS(xvinsgr2vr_w, LASX, gen_g2x, MO_32, tcg_gen_st32_tl)
> +TRANS(xvinsgr2vr_d, LASX, gen_g2x, MO_64, tcg_gen_st_tl)

All of these *_d instructions are invalid for LA32.
This is obvious because they specifically refer to general registers.

All of the rest of these changes need to be audited.

> @@ -4905,8 +4907,8 @@ static bool gvec_dup_vl(DisasContext *ctx, arg_vr *a,
>           return true;
>       }
>   
> -    tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd),
> -                         oprsz, ctx->vl/8, src);
> +    tcg_gen_gvec_dup_tl(mop, vec_full_offset(a->vd),
> +                         oprsz, ctx->vl/TARGET_LONG_SIZE, src);
>       return true;
>   }

This is not obvious.  There might be uses for which we really ought to have extended the 
src argument to TCGv_i64.


r~