[Commit-gnuradio] r10886 - gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad

[jcorgan]

Author: jcorgan
Date: 2009-04-21 15:42:44 -0600 (Tue, 21 Apr 2009)
New Revision: 10886

Modified:
   
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_rx.v
   
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.sav
   
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.v
Log:
Implement integrate-and-dump decimator, tests ok in simulation

Modified: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_rx.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_rx.v
  2009-04-21 01:00:20 UTC (rev 10885)
+++ 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_rx.v
  2009-04-21 21:42:44 UTC (rev 10886)
@@ -1,4 +1,3 @@
-
 `define DSP_CORE_RX_BASE 160
 module dsp_core_rx
   (input clk, input rst,
@@ -23,16 +22,13 @@
 
    wire [35:0] prod_i, prod_q;
    wire [23:0] i_cordic, q_cordic;
-   wire [23:0] i_cic, q_cic;
-   wire [17:0] i_cic_scaled, q_cic_scaled;
-   wire [17:0] i_hb1, q_hb1;
-   wire [17:0] i_hb2, q_hb2;
+   wire [31:0] i_iad, q_iad;
    wire [15:0] i_out, q_out;
-
-   wire        strobe_cic, strobe_hb1, strobe_hb2;
-   wire        enable_hb1, enable_hb2;
-   wire [7:0]  cic_decim_rate;
    
+   wire        enable_hb1, enable_hb2; // Correspond to std firmware settings
+   wire [7:0]  cic_decim;              // for combined CIC/HB decimator
+   wire [9:0]  decim_rate;             // Reconstructed original decimation 
setting
+   
    setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(phase_inc),.changed());
@@ -43,7 +39,7 @@
    
    setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
+      .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed());
 
    rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a
      
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
@@ -117,47 +113,30 @@
    
    cordic_z24 #(.bitwidth(24))
      cordic(.clock(clk), .reset(rst), .enable(run),
-           .xi(prod_i[23:0]),. yi(prod_q[23:0]), .zi(phase[31:8]),
+           .xi(prod_i[24:1]),. yi(prod_q[24:1]), .zi(phase[31:8]),
            .xo(i_cordic),.yo(q_cordic),.zo() );
 
-   cic_strober 
cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate),
-                          .strobe_fast(1),.strobe_slow(strobe_cic) );
+   // Reconstruct original decimation rate from standard firmware settings
+   assign decim_rate = enable_hb1 ? (enable_hb2 ? {cic_decim,2'b0} : 
{1'b0,cic_decim,1'b0 }) :
+                                   cic_decim;
 
-   cic_decim #(.bw(24))
-     decim_i (.clock(clk),.reset(rst),.enable(run),
-             .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
-             .signal_in(i_cordic),.signal_out(i_cic));
-   
-   cic_decim #(.bw(24))
-     decim_q (.clock(clk),.reset(rst),.enable(run),
-             .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
-             .signal_in(q_cordic),.signal_out(q_cic));
+   cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator
+   cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate),
+              .strobe_fast(1),.strobe_slow(strobe_iad) );
 
-   round_reg #(.bits_in(24),.bits_out(18)) round_icic 
(.clk(clk),.in(i_cic),.out(i_cic_scaled));
-   round_reg #(.bits_in(24),.bits_out(18)) round_qcic 
(.clk(clk),.in(q_cic),.out(q_cic_scaled));
-   reg                strobe_cic_d1;
-   always @(posedge clk) strobe_cic_d1 <= strobe_cic;
-   
-   small_hb_dec #(.WIDTH(18)) small_hb_i
-     (.clk(clk),.rst(rst),.bypass(~enable_hb1),
-      
.stb_in(strobe_cic_d1),.data_in(i_cic_scaled),.stb_out(strobe_hb1),.data_out(i_hb1));
-   
-   small_hb_dec #(.WIDTH(18)) small_hb_q
-     (.clk(clk),.rst(rst),.bypass(~enable_hb1),
-      
.stb_in(strobe_cic_d1),.data_in(q_cic_scaled),.stb_out(),.data_out(q_hb1));
+   integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i
+     (.clk_i(clk),.rst_i(rst),.ena_i(run),
+      .dump_i(strobe_iad),.data_i(i_cordic),
+      .stb_o(strobe),.integ_o(i_iad) );
 
-   wire [8:0]  cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : 
{1'b0,cic_decim_rate};
-   hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_i
-     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.cpi(cpi_hb),
-      
.stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2));
-
-   hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_q
-     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.cpi(cpi_hb),
-      .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
-
-   round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out));
-   round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out));
-
+   integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q
+     (.clk_i(clk),.rst_i(rst),.ena_i(run),
+      .dump_i(strobe_iad),.data_i(q_cordic),
+      .stb_o(strobe),.integ_o(q_iad) );
+   
+   round #(.bits_in(32),.bits_out(16)) round_iout (.in(i_iad),.out(i_out));
+   round #(.bits_in(32),.bits_out(16)) round_qout (.in(q_iad),.out(q_out));
+  
    // Streaming GPIO
    //
    // io_rx[15] => I channel LSB if gpio_ena[0] high
@@ -173,7 +152,6 @@
      end
    
    assign      sample = sample_reg;
-   assign      strobe = strobe_hb2;
-   assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, 
strobe_cic_d1, strobe_hb1, strobe_hb2};
+   assign      debug = {clk, rst, run, strobe};
    
 endmodule // dsp_core_rx

Modified: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.sav
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.sav
        2009-04-21 01:00:20 UTC (rev 10885)
+++ 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.sav
        2009-04-21 21:42:44 UTC (rev 10886)
@@ -1,6 +1,7 @@
 [size] 1680 975
 [pos] -1 -1
-*-23.920586 21670000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
-1 -1 -1 -1 -1 -1 -1
+*-24.007835 13660000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
-1 -1 -1 -1 -1 -1 -1
+[treeopen] dsp_core_tb.
 @200
 -SYSCON
 @28
@@ -12,49 +13,43 @@
 -Settings Bus
 @22
 dsp_core_tb.set_addr[7:0]
address@hidden
 dsp_core_tb.set_data[31:0]
 @28
 dsp_core_tb.set_stb
 @200
 -
 -RX DSP CORE
address@hidden
-dsp_core_tb.adc.adc_a[13:0]
address@hidden
 -
address@hidden
+dsp_core_tb.rx_path.decim_rate[9:0]
 @200
 -
 @8420
-dsp_core_tb.rx_path.adc_a_ofs[13:0]
+dsp_core_tb.adc_a[13:0]
 @20000
 -
 @200
 -
 @8420
-dsp_core_tb.rx_path.i_cordic[23:0]
+dsp_core_tb.rx_path.adc_a_ofs[13:0]
 @20000
 -
 @200
 -
address@hidden
-dsp_core_tb.rx_path.i_cic[23:0]
address@hidden
+dsp_core_tb.rx_path.i_cordic[23:0]
 @20000
 -
 @200
 -
address@hidden
-dsp_core_tb.rx_path.i_hb1[17:0]
address@hidden
+dsp_core_tb.rx_path.i_iad[31:0]
 @20000
 -
 @200
 -
 @8420
-dsp_core_tb.rx_path.i_hb2[17:0]
address@hidden
--
address@hidden
--
address@hidden
 dsp_core_tb.rx_path.i_out[15:0]
 @20000
 -
@@ -62,3 +57,5 @@
 -
 @28
 dsp_core_tb.stb
address@hidden
+-

Modified: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.v
  2009-04-21 01:00:20 UTC (rev 10885)
+++ 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.v
  2009-04-21 21:42:44 UTC (rev 10886)
@@ -47,13 +47,13 @@
 // Unit(s) under test                                                          
  //
 
///////////////////////////////////////////////////////////////////////////////////
    
-   reg [13:0] amplitude = 13'h1FFF;
-   reg [15:0] impulse_len = 1;
-   reg [15:0] zero_len = 999;
+   reg [13:0] amplitude = 13'h1fff;
+   reg [15:0] impulse_len = 0;
+   reg [15:0] zero_len = 0;
    reg               adc_ena = 0;
 
    initial #500 @(posedge clk) adc_ena = 1;
-   
+
    impulse adc
      (.clk(clk),.rst(rst),.ena(adc_ena),
       .dc_offset_a(0),.dc_offset_b(0),
@@ -70,7 +70,7 @@
       .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),
       .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
       .io_rx(16'b0),
-      .run(run),.sample(sample),.strobe(stb),
+      .run(adc_ena),.sample(sample),.strobe(stb),
       .debug() );
    
 
///////////////////////////////////////////////////////////////////////////////////
@@ -174,8 +174,8 @@
         set_zero_len(999);
         set_rx_muxctrl(1);
         set_ddc_freq(0);
-        set_rx_scale_iq(1024, 1024);
-        set_decim(1, 1, 10); // decim = 40
+        set_rx_scale_iq(1243, 1243);
+        set_decim(1, 1, 10);
 
         #100000 $finish;
       end