[Commit-gnuradio] r10885 - gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad

[jcorgan]

Author: jcorgan
Date: 2009-04-20 19:00:20 -0600 (Mon, 20 Apr 2009)
New Revision: 10885

Added:
   
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/impulse.v
   
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/integrate.v
Modified:
   gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/Makefile
   
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.sav
   
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.v
Log:
Add impulse generator and receive path parameter setting.

Modified: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/Makefile
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/Makefile   
    2009-04-20 23:51:19 UTC (rev 10884)
+++ 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/Makefile   
    2009-04-21 01:00:20 UTC (rev 10885)
@@ -250,3 +250,4 @@
        rm -f dsp_core_tb
        rm -f *.lx2
        rm -f *.dat
+       rm -f *.vcd

Modified: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.sav
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.sav
        2009-04-20 23:51:19 UTC (rev 10884)
+++ 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.sav
        2009-04-21 01:00:20 UTC (rev 10885)
@@ -1,7 +1,6 @@
 [size] 1680 975
 [pos] -1 -1
-*-20.692646 1008000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
-1 -1 -1 -1 -1 -1 -1
-[treeopen] dsp_core_tb.
+*-23.920586 21670000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
-1 -1 -1 -1 -1 -1 -1
 @200
 -SYSCON
 @28
@@ -18,66 +17,48 @@
 dsp_core_tb.set_stb
 @200
 -
--ADC Interface
address@hidden
-dsp_core_tb.adc_a[13:0]
-dsp_core_tb.adc_b[13:0]
address@hidden
+-RX DSP CORE
address@hidden
+dsp_core_tb.adc.adc_a[13:0]
address@hidden
 -
--DSP Output
address@hidden
-dsp_core_tb.sample[31:0]
address@hidden
-dsp_core_tb.stb
 @200
 -
--
--Rx Path Internals
address@hidden
address@hidden
 dsp_core_tb.rx_path.adc_a_ofs[13:0]
-dsp_core_tb.rx_path.adc_b_ofs[13:0]
-dsp_core_tb.rx_path.adc_i[13:0]
-dsp_core_tb.rx_path.adc_q[13:0]
-dsp_core_tb.rx_path.muxctrl[3:0]
-dsp_core_tb.rx_path.io_rx[15:0]
-dsp_core_tb.rx_path.scale_i[15:0]
-dsp_core_tb.rx_path.scale_q[15:0]
-dsp_core_tb.rx_path.prod_i[35:0]
-dsp_core_tb.rx_path.prod_q[35:0]
-dsp_core_tb.rx_path.cic_decim_rate[7:0]
address@hidden
-dsp_core_tb.rx_path.enable_hb1
-dsp_core_tb.rx_path.enable_hb2
address@hidden
-dsp_core_tb.rx_path.cpi_hb[8:0]
address@hidden
-dsp_core_tb.rx_path.strobe_cic
-dsp_core_tb.rx_path.strobe_cic_d1
address@hidden
-dsp_core_tb.rx_path.phase[31:0]
-dsp_core_tb.rx_path.phase_inc[31:0]
address@hidden
+-
address@hidden
+-
address@hidden
 dsp_core_tb.rx_path.i_cordic[23:0]
-dsp_core_tb.rx_path.q_cordic[23:0]
address@hidden
-dsp_core_tb.rx_path.gpio_ena[1:0]
address@hidden
address@hidden
+-
address@hidden
+-
address@hidden
 dsp_core_tb.rx_path.i_cic[23:0]
-dsp_core_tb.rx_path.q_cic[23:0]
-dsp_core_tb.rx_path.i_cic_scaled[17:0]
-dsp_core_tb.rx_path.q_cic_scaled[17:0]
address@hidden
-dsp_core_tb.rx_path.strobe_hb1
address@hidden
address@hidden
+-
address@hidden
+-
address@hidden
 dsp_core_tb.rx_path.i_hb1[17:0]
-dsp_core_tb.rx_path.q_hb1[17:0]
address@hidden
-dsp_core_tb.rx_path.strobe_hb2
address@hidden
address@hidden
+-
address@hidden
+-
address@hidden
 dsp_core_tb.rx_path.i_hb2[17:0]
-dsp_core_tb.rx_path.q_hb2[17:0]
address@hidden
+-
address@hidden
+-
address@hidden
 dsp_core_tb.rx_path.i_out[15:0]
-dsp_core_tb.rx_path.q_out[15:0]
-dsp_core_tb.rx_path.debug[31:0]
-dsp_core_tb.rx_path.sample_reg[31:0]
address@hidden
+-
address@hidden
+-
 @28
-dsp_core_tb.rx_path.strobe
+dsp_core_tb.stb

Modified: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.v
  2009-04-20 23:51:19 UTC (rev 10884)
+++ 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.v
  2009-04-21 01:00:20 UTC (rev 10885)
@@ -7,20 +7,22 @@
 
///////////////////////////////////////////////////////////////////////////////////
    
    // System control bus
-   reg                clk;                initial clk = 1'b0;
-   reg                rst;                 initial rst = 1'b1;
+   reg                clk = 0;
+   reg                rst = 1;
    
    // Configuration bus
-   reg                set_stb;             initial set_stb = 1'b0;
-   reg          [7:0] set_addr;            initial set_addr = 8'b0;
-   reg         [31:0] set_data;            initial set_data = 32'b0;
+   reg                set_stb = 0;  
+   reg          [7:0] set_addr = 0; 
+   reg         [31:0] set_data = 0; 
 
    // ADC input bus
-   reg  signed [13:0] adc_a;               initial adc_a = 14'd0;
-   reg  signed [13:0] adc_b;               initial adc_b = 14'd0;
-
+   wire signed [13:0] adc_a;
+   wire signed [13:0] adc_b;
+   wire               adc_ovf_a;
+   wire               adc_ovf_b;
+   
    // RX sample bus
-   reg                run;                 initial run = 1'b1;
+   reg                run = 1;
    wire        [31:0] sample;
    wire               stb;
    
@@ -35,7 +37,7 @@
    end
 
    // Update display every 10 us
-   always #10000 $monitor("Time in us ",$time/1000);
+   always #1000 $monitor("Time in us ",$time/1000);
 
    // Generate master clock 50% @ 100 MHz
    always
@@ -45,14 +47,28 @@
 // Unit(s) under test                                                          
  //
 
///////////////////////////////////////////////////////////////////////////////////
    
-   // Make unisims happy
-   // glbl glbl();
+   reg [13:0] amplitude = 13'h1FFF;
+   reg [15:0] impulse_len = 1;
+   reg [15:0] zero_len = 999;
+   reg               adc_ena = 0;
 
+   initial #500 @(posedge clk) adc_ena = 1;
+   
+   impulse adc
+     (.clk(clk),.rst(rst),.ena(adc_ena),
+      .dc_offset_a(0),.dc_offset_b(0),
+      .amplitude(amplitude),
+      .impulse_len(impulse_len),.zero_len(zero_len),
+      .adc_a(adc_a),.adc_b(adc_b),
+      .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) );
+
+   initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate 
X's
+   initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset
    dsp_core_rx rx_path
      (.clk(clk),.rst(rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .adc_a(adc_a),.adc_ovf_a(0'b0),
-      .adc_b(adc_b),.adc_ovf_b(0'b0),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),
+      .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
       .io_rx(16'b0),
       .run(run),.sample(sample),.strobe(stb),
       .debug() );
@@ -91,6 +107,16 @@
      end
    endtask // power_on
    
+   task set_impulse_len;
+      input [15:0] len;
+      @(posedge clk) impulse_len = len-1;
+   endtask
+ 
+   task set_zero_len;
+      input [15:0] len;
+      @(posedge clk) zero_len = len-1;
+   endtask
+
    // Strobe configuration bus with addr, data
    task write_cfg_register;
       input [7:0]  regno;
@@ -106,12 +132,53 @@
       end
    endtask // write_cfg_register
 
+   // Set RX DDC frequency
+   task set_ddc_freq;
+      input [31:0] freq;
+
+      write_cfg_register(160, freq);
+   endtask // set_ddc_freq
+
+   // Set RX IQ scaling registers
+   task set_rx_scale_iq;
+      input [15:0] scale_i;
+      input [15:0] scale_q;
+
+      write_cfg_register(161, {scale_i,scale_q});
+   endtask // set_rx_scale_iq
+   
+   // Set RX MUX control
+   task set_rx_muxctrl;
+      input [3:0] muxctrl;
+
+      write_cfg_register(168, muxctrl);
+   endtask // set_rx_muxctrl
+   
+   // Set RX CIC decim and halfband enables
+   task set_decim;
+      input hb1_ena;
+      input hb2_ena;
+      input [7:0] decim;
+
+      write_cfg_register(162, {hb1_ena,hb2_ena,decim});
+   endtask // set_decim
+      
+   
 
///////////////////////////////////////////////////////////////////////////////////
 // Individual tests                                                            
  //
 
///////////////////////////////////////////////////////////////////////////////////
 
    task test_rx;
-      #10000 $finish;
+      begin
+        set_impulse_len(1);
+        set_zero_len(999);
+        set_rx_muxctrl(1);
+        set_ddc_freq(0);
+        set_rx_scale_iq(1024, 1024);
+        set_decim(1, 1, 10); // decim = 40
+
+        #100000 $finish;
+      end
    endtask // test_rx
    
       

Added: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/impulse.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/impulse.v  
                            (rev 0)
+++ 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/impulse.v  
    2009-04-21 01:00:20 UTC (rev 10885)
@@ -0,0 +1,63 @@
+module impulse
+  (input clk,
+   input rst,
+   input ena,
+   
+   input [13:0] dc_offset_a,
+   input [13:0] dc_offset_b,
+   input [13:0] amplitude,
+   input [15:0] impulse_len,
+   input [15:0] zero_len,
+
+   output [13:0] adc_a,
+   output [13:0] adc_b,
+   output        adc_ovf_a,
+   output        adc_ovf_b
+   );
+
+   reg [13:0] adc_a_int = 0;
+   reg [15:0] count;
+
+   localparam ST_ZERO = 0;
+   localparam ST_HIGH = 1;
+   reg               state;
+   
+   always @(posedge clk)
+     if (rst | ~ena)
+       begin
+         adc_a_int <= 0;
+         count <= 0;
+         state <= ST_ZERO;
+       end
+     else
+       case(state)
+        ST_ZERO:
+          if (count == zero_len)
+            begin
+               adc_a_int <= amplitude;
+               state <= ST_HIGH;
+               count <= 0;
+            end
+          else
+            count <= count + 1;
+
+        ST_HIGH:
+          if (count == impulse_len)
+            begin
+               adc_a_int <= 0;
+               state <= ST_ZERO;
+               count <= 0;
+            end
+          else
+            count <= count + 1;
+
+       endcase // case (state)
+
+   assign adc_a = adc_a_int + dc_offset_a;
+
+   // Ignore for now
+   assign adc_b = dc_offset_b;
+   assign adc_ovf_a = 0;
+   assign adc_ovf_b = 0;
+
+endmodule // adc_model

Added: 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/integrate.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/integrate.v
                            (rev 0)
+++ 
gnuradio/branches/developers/jcorgan/iad2/usrp2/fpga/top/u2_rev3_iad/integrate.v
    2009-04-21 01:00:20 UTC (rev 10885)
@@ -0,0 +1,38 @@
+module integrate
+  #(parameter INPUTW = 16,
+    parameter ACCUMW = 32,
+    parameter OUTPUTW = 16)
+
+   (input clk_i,
+    input rst_i,
+    input ena_i,
+
+    input dump_i,
+    input [INPUTW-1:0] data_i,
+
+    output reg stb_o,
+    output reg [OUTPUTW-1:0] integ_o
+   );
+   
+   wire [ACCUMW-1:0] data_ext = {{ACCUMW-INPUTW{data_i[INPUTW-1]}},data_i};
+   reg  [ACCUMW-1:0] accum;
+
+   always @(posedge clk_i)
+     if (rst_i | ~ena_i)
+       begin
+         accum <= 0;
+         integ_o <= 0;
+       end
+     else
+       if (dump_i)
+        begin
+           integ_o <= accum[ACCUMW-1:ACCUMW-OUTPUTW];
+           accum <= data_ext;
+        end
+       else
+        accum <= accum + data_ext;
+
+   always @(posedge clk_i)
+     stb_o <= dump_i;
+   
+endmodule // integrate