[RFC PATCH 7/7] target/riscv: Add big endian CPU target

[Roan Richmond]

From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>

Adds a RV64 equivalent CPU which starts in big endian mode, i.e. MBE,
SBE, and UBE set.

Authored-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
Co-authored-by: Ben Dooks <ben.dooks@codethink.co.uk>
Co-authored-by: Roan Richmond <roan.richmond@codethink.co.uk>
Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
---
 target/riscv/cpu-qom.h | 1 +
 target/riscv/cpu.c     | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 62115375cd..487c544ef1 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -38,6 +38,7 @@
 #define TYPE_RISCV_CPU_RV32E            RISCV_CPU_TYPE_NAME("rv32e")
 #define TYPE_RISCV_CPU_RV64I            RISCV_CPU_TYPE_NAME("rv64i")
 #define TYPE_RISCV_CPU_RV64E            RISCV_CPU_TYPE_NAME("rv64e")
+#define TYPE_RISCV_CPU_BIG_ENDIAN       RISCV_CPU_TYPE_NAME("rv64-be")
 #define TYPE_RISCV_CPU_RVA22U64         RISCV_CPU_TYPE_NAME("rva22u64")
 #define TYPE_RISCV_CPU_RVA22S64         RISCV_CPU_TYPE_NAME("rva22s64")
 #define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f219f0c3b5..8c65b0f88e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -615,6 +615,13 @@ static void rv64e_bare_cpu_init(Object *obj)
     riscv_cpu_set_misa_ext(env, RVE);
 }
 
+static void rv64_big_endian_bare_cpu_init(Object *obj)
+{
+    CPURISCVState *env = &RISCV_CPU(obj)->env;
+    env->mstatus |= (MSTATUS_MBE | MSTATUS_SBE | MSTATUS_UBE);
+    riscv_cpu_set_misa_ext(env, RVE);
+}
+
 #endif /* !TARGET_RISCV64 */
 
 #if defined(TARGET_RISCV32) || \
@@ -2988,6 +2995,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
 #endif /* CONFIG_TCG */
     DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I,        MXL_RV64,  
rv64i_bare_cpu_init),
     DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E,        MXL_RV64,  
rv64e_bare_cpu_init),
+    DEFINE_BARE_CPU(TYPE_RISCV_CPU_BIG_ENDIAN,   MXL_RV64,  
rv64_big_endian_bare_cpu_init),
     DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64,  MXL_RV64,  
rva22u64_profile_cpu_init),
     DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64,  MXL_RV64,  
rva22s64_profile_cpu_init),
 #endif /* TARGET_RISCV64 */
-- 
2.43.0