[PATCH] ppc/pnv: Add PowerPC Special Purpose Registers (SPRs):

[dan tan]

    The handling of the following SPRs are added -
        ITV1  (0x375, 885) - noop (not in Power10 ISA)
        SIER2 (0x2f0, 752) - Sampled Instruction Event Register 2
        SIER2 (0x2f1, 753) - Sampled Instruction Event Register 3
        MMCR3 (0x2f2, 754) - Performance Monitor Mode Control Register 3

    Signed-off-by: dan tan <dantan@linux.vnet.ibm.com>
---
 target/ppc/cpu.h      |  4 ++++
 target/ppc/cpu_init.c | 17 +++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f8101ff..de0af02 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1933,6 +1933,9 @@ void ppc_compat_add_property(Object *obj, const char 
*name,
 #define SPR_BOOKE_TLB2CFG     (0x2B2)
 #define SPR_BOOKE_TLB3CFG     (0x2B3)
 #define SPR_BOOKE_EPR         (0x2BE)
+#define SPR_POWER_SIER2       (0x2F0)
+#define SPR_POWER_SIER3       (0x2F1)
+#define SPR_POWER_MMCR3       (0x2F2)
 #define SPR_PERF0             (0x300)
 #define SPR_RCPU_MI_RBA0      (0x300)
 #define SPR_MPC_MI_CTR        (0x300)
@@ -2053,6 +2056,7 @@ void ppc_compat_add_property(Object *obj, const char 
*name,
 #define SPR_440_INV3          (0x373)
 #define SPR_440_ITV0          (0x374)
 #define SPR_440_ITV1          (0x375)
+#define SPR_ITV1              (0x375)
 #define SPR_440_ITV2          (0x376)
 #define SPR_440_ITV3          (0x377)
 #define SPR_440_CCR1          (0x378)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 40fe14a..71c46b2 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5294,6 +5294,18 @@ static void register_power8_pmu_sup_sprs(CPUPPCState 
*env)
                      SPR_NOACCESS, SPR_NOACCESS,
                      &spr_read_generic, &spr_write_generic,
                      KVM_REG_PPC_CSIGR, 0x00000000);
+    spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_MMCR3, 0x00000000);
+    spr_register_kvm(env, SPR_POWER_SIER2, "SIER2",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_SIER2, 0x00000000);
+    spr_register_kvm(env, SPR_POWER_SIER3, "SIER3",
+                     SPR_NOACCESS, SPR_NOACCESS,
+                     &spr_read_generic, &spr_write_generic,
+                     KVM_REG_PPC_SIER3, 0x00000000);
 }
 
 static void register_power8_pmu_user_sprs(CPUPPCState *env)
@@ -5670,6 +5682,11 @@ static void register_power_common_book4_sprs(CPUPPCState 
*env)
                  &spr_access_nop, &spr_write_generic,
                  &spr_access_nop, &spr_write_generic,
                  0x00000000);
+    spr_register_hv(env, SPR_ITV1, "ITV1",
+                 SPR_NOACCESS, SPR_NOACCESS,
+                 &spr_access_nop, &spr_write_generic,
+                 &spr_access_nop, &spr_write_generic,
+                 0x00000000);
 #endif
 }
 
-- 
1.8.3.1