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[PATCH v2 01/11] target/ppc: Fix insn32.decode style issues
From: |
Víctor Colombo |
Subject: |
[PATCH v2 01/11] target/ppc: Fix insn32.decode style issues |
Date: |
Mon, 23 May 2022 14:57:57 -0300 |
Some lines in insn32.decode have inconsistent alignment when compared
to others.
Fix this by changing the alignment of some lines, making it more
consistent throughout the file.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/insn32.decode | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 39372fe673..b47213764d 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -18,11 +18,11 @@
#
&D rt ra si:int64_t
-@D ...... rt:5 ra:5 si:s16 &D
+@D ...... rt:5 ra:5 si:s16 &D
&D_bf bf l:bool ra imm
-@D_bfs ...... bf:3 - l:1 ra:5 imm:s16 &D_bf
-@D_bfu ...... bf:3 - l:1 ra:5 imm:16 &D_bf
+@D_bfs ...... bf:3 . l:1 ra:5 imm:s16 &D_bf
+@D_bfu ...... bf:3 . l:1 ra:5 imm:16 &D_bf
%dq_si 4:s12 !function=times_16
%dq_rtp 22:4 !function=times_2
@@ -35,7 +35,7 @@
@DQ_TSXP ...... ..... ra:5 ............ .... &D si=%dq_si
rt=%rt_tsxp
%ds_si 2:s14 !function=times_4
-@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
+@DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
%ds_rtp 22:4 !function=times_2
@DS_rtp ...... ....0 ra:5 .............. .. &D rt=%ds_rtp
si=%ds_si
@@ -46,10 +46,10 @@
&DX rt d
%dx_d 6:s10 16:5 0:1
-@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
+@DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d
&VA vrt vra vrb rc
-@VA ...... vrt:5 vra:5 vrb:5 rc:5 ...... &VA
+@VA ...... vrt:5 vra:5 vrb:5 rc:5 ...... &VA
&VC vrt vra vrb rc:bool
@VC ...... vrt:5 vra:5 vrb:5 rc:1 .......... &VC
@@ -58,7 +58,7 @@
@VN ...... vrt:5 vra:5 vrb:5 .. sh:3 ...... &VN
&VX vrt vra vrb
-@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
+@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
&VX_bf bf vra vrb
@VX_bf ...... bf:3 .. vra:5 vrb:5 ........... &VX_bf
@@ -73,13 +73,13 @@
@VX_tb_rc ...... vrt:5 ..... vrb:5 rc:1 .......... &VX_tb_rc
&VX_uim4 vrt uim vrb
-@VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4
+@VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4
&VX_tb vrt vrb
-@VX_tb ...... vrt:5 ..... vrb:5 ........... &VX_tb
+@VX_tb ...... vrt:5 ..... vrb:5 ........... &VX_tb
&X rt ra rb
-@X ...... rt:5 ra:5 rb:5 .......... . &X
+@X ...... rt:5 ra:5 rb:5 .......... . &X
&X_rc rt ra rb rc:bool
@X_rc ...... rt:5 ra:5 rb:5 .......... rc:1 &X_rc
@@ -104,7 +104,7 @@
@X_t_bp_rc ...... rt:5 ..... ....0 .......... rc:1 &X_tb_rc
rb=%x_frbp
&X_bi rt bi
-@X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
+@X_bi ...... rt:5 bi:5 ..... .......... . &X_bi
&X_bf bf ra rb
@X_bf ...... bf:3 .. ra:5 rb:5 .......... . &X_bf
@@ -119,7 +119,7 @@
@X_bf_uim_bp ...... bf:3 . uim:6 ....0 .......... . &X_bf_uim
rb=%x_frbp
&X_bfl bf l:bool ra rb
-@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
+@X_bfl ...... bf:3 . l:1 ra:5 rb:5 .......... . &X_bfl
%x_xt 0:1 21:5
&X_imm5 xt imm:uint8_t vrb
--
2.25.1
- [PATCH v2 00/11] BCDA and mffscdrn implementations, Víctor Colombo, 2022/05/23
- [PATCH v2 01/11] target/ppc: Fix insn32.decode style issues,
Víctor Colombo <=
- [PATCH v2 02/11] target/ppc: Move mffscrn[i] to decodetree, Víctor Colombo, 2022/05/23
- [PATCH v2 03/11] target/ppc: Move mffsce to decodetree, Víctor Colombo, 2022/05/23
- [PATCH v2 04/11] target/ppc: Move mffsl to decodetree, Víctor Colombo, 2022/05/23
- [PATCH v2 05/11] target/ppc: Move mffs[.] to decodetree, Víctor Colombo, 2022/05/23
- [PATCH v2 06/11] target/ppc: Implement mffscdrn[i] instructions, Víctor Colombo, 2022/05/23
- [PATCH v2 07/11] tests/tcg/ppc64: Add mffsce test, Víctor Colombo, 2022/05/23
- [PATCH v2 08/11] target/ppc: Add flag for ISA v2.06 BCDA instructions, Víctor Colombo, 2022/05/23
- [PATCH v2 09/11] target/ppc: implement addg6s, Víctor Colombo, 2022/05/23
- [PATCH v2 10/11] target/ppc: implement cbcdtd, Víctor Colombo, 2022/05/23
- [PATCH v2 11/11] target/ppc: implement cdtbcd, Víctor Colombo, 2022/05/23