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[PULL 64/72] target/hexagon: Use float32_muladd_scalbn for helper_sffma_
From: |
Richard Henderson |
Subject: |
[PULL 64/72] target/hexagon: Use float32_muladd_scalbn for helper_sffma_sc |
Date: |
Tue, 24 Dec 2024 12:05:13 -0800 |
This instruction has a special case that 0 * x + c returns c
without the normal sign folding that comes with 0 + -0.
Use the new float_muladd_suppress_add_product_zero to
describe this.
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hexagon/op_helper.c | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 95bfa5d029..53c65e852e 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -1080,15 +1080,10 @@ static float32 check_nan(float32 dst, float32 x,
float_status *fp_status)
float32 HELPER(sffma_sc)(CPUHexagonState *env, float32 RxV,
float32 RsV, float32 RtV, float32 PuV)
{
- size4s_t tmp;
arch_fpop_start(env);
- RxV = check_nan(RxV, RxV, &env->fp_status);
- RxV = check_nan(RxV, RsV, &env->fp_status);
- RxV = check_nan(RxV, RtV, &env->fp_status);
- tmp = internal_fmafx(RsV, RtV, RxV, fSXTN(8, 64, PuV), &env->fp_status);
- if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) {
- RxV = tmp;
- }
+ RxV = float32_muladd_scalbn(RsV, RtV, RxV, fSXTN(8, 64, PuV),
+ float_muladd_suppress_add_product_zero,
+ &env->fp_status);
arch_fpop_end(env);
return RxV;
}
--
2.43.0
- [PULL 48/72] tcg/optimize: Use fold_masks_zs in fold_xor, (continued)
- [PULL 48/72] tcg/optimize: Use fold_masks_zs in fold_xor, Richard Henderson, 2024/12/24
- [PULL 50/72] tcg/optimize: Use finish_folding as default in tcg_optimize, Richard Henderson, 2024/12/24
- [PULL 42/72] tcg/optimize: Use fold_masks_zs in fold_sextract, Richard Henderson, 2024/12/24
- [PULL 46/72] tcg/optimize: Use fold_masks_zs in fold_tcg_ld, Richard Henderson, 2024/12/24
- [PULL 47/72] tcg/optimize: Use finish_folding in fold_tcg_ld_memcopy, Richard Henderson, 2024/12/24
- [PULL 49/72] tcg/optimize: Use finish_folding in fold_bitsel_vec, Richard Henderson, 2024/12/24
- [PULL 53/72] tcg/optimize: Move fold_bitsel_vec into alphabetic sort, Richard Henderson, 2024/12/24
- [PULL 58/72] softfloat: Remove float_muladd_halve_result, Richard Henderson, 2024/12/24
- [PULL 60/72] softfloat: Add float_muladd_suppress_add_product_zero, Richard Henderson, 2024/12/24
- [PULL 61/72] target/hexagon: Use float32_mul in helper_sfmpy, Richard Henderson, 2024/12/24
- [PULL 64/72] target/hexagon: Use float32_muladd_scalbn for helper_sffma_sc,
Richard Henderson <=
- [PULL 68/72] target/hexagon: Remove Float, Richard Henderson, 2024/12/24
- [PULL 44/72] tcg/optimize: Simplify sign bit test in fold_shift, Richard Henderson, 2024/12/24
- [PULL 56/72] target/arm: Use float*_muladd_scalbn, Richard Henderson, 2024/12/24
- [PULL 52/72] tcg/optimize: Re-enable sign-mask optimizations, Richard Henderson, 2024/12/24
- [PULL 69/72] target/hexagon: Remove Double, Richard Henderson, 2024/12/24
- [PULL 70/72] target/hexagon: Use mulu64 for int128_mul_6464, Richard Henderson, 2024/12/24
- [PULL 51/72] tcg/optimize: Remove z_mask, s_mask from OptContext, Richard Henderson, 2024/12/24
- [PULL 67/72] target/hexagon: Expand GEN_XF_ROUND, Richard Henderson, 2024/12/24
- [PULL 72/72] accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core, Richard Henderson, 2024/12/24
- [PULL 62/72] target/hexagon: Use float32_muladd for helper_sffma, Richard Henderson, 2024/12/24