[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v2 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU
|
From: |
Alistair Francis |
|
Subject: |
[PULL v2 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU |
|
Date: |
Fri, 20 Dec 2024 11:54:39 +1000 |
From: MollyChen <xiaoou@iscas.ac.cn>
Add a CPU entry for the RV64 XiangShan NANHU CPU which
supports single-core and dual-core configurations. More
details can be found at
https://docs.xiangshan.cc/zh-cn/latest/integration/overview
Signed-off-by: MollyChen <xiaoou@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20241205073622.46052-1-xiaoou@iscas.ac.cn>
[ Changes by AF
- Fixup code formatting
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu-qom.h | 1 +
target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 6547642287..d56b067bf2 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -50,6 +50,7 @@
#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906")
#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
#define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon")
+#define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nanhu")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d7b830d489..58bb5196a8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -647,6 +647,34 @@ static void rv64_tt_ascalon_cpu_init(Object *obj)
#endif
}
+static void rv64_xiangshan_nanhu_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+
+ riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU);
+ env->priv_ver = PRIV_VERSION_1_12_0;
+
+ /* Enable ISA extensions */
+ cpu->cfg.ext_zbc = true;
+ cpu->cfg.ext_zbkb = true;
+ cpu->cfg.ext_zbkc = true;
+ cpu->cfg.ext_zbkx = true;
+ cpu->cfg.ext_zknd = true;
+ cpu->cfg.ext_zkne = true;
+ cpu->cfg.ext_zknh = true;
+ cpu->cfg.ext_zksed = true;
+ cpu->cfg.ext_zksh = true;
+ cpu->cfg.ext_svinval = true;
+
+ cpu->cfg.mmu = true;
+ cpu->cfg.pmp = true;
+
+#ifndef CONFIG_USER_ONLY
+ set_satp_mode_max_supported(cpu, VM_1_10_SV39);
+#endif
+}
+
#ifdef CONFIG_TCG
static void rv128_base_cpu_init(Object *obj)
{
@@ -3056,6 +3084,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64,
rv64_thead_c906_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64,
rv64_tt_ascalon_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64,
rv64_veyron_v1_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU,
+ MXL_RV64,
rv64_xiangshan_nanhu_cpu_init),
#ifdef CONFIG_TCG
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128,
rv128_base_cpu_init),
#endif /* CONFIG_TCG */
--
2.47.1
- [PULL v2 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system., (continued)
- [PULL v2 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system., Alistair Francis, 2024/12/19
- [PULL v2 27/39] hw/riscv: Add a new struct RISCVBootInfo, Alistair Francis, 2024/12/19
- [PULL v2 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses, Alistair Francis, 2024/12/19
- [PULL v2 31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/19
- [PULL v2 32/39] target/riscv: Check memory access to meet svukte rule, Alistair Francis, 2024/12/19
- [PULL v2 34/39] target/riscv: Check svukte is not enabled in RV32, Alistair Francis, 2024/12/19
- [PULL v2 33/39] target/riscv: Expose svukte ISA extension, Alistair Francis, 2024/12/19
- [PULL v2 35/39] target/riscv: Include missing headers in 'vector_internals.h', Alistair Francis, 2024/12/19
- [PULL v2 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver, Alistair Francis, 2024/12/19
- [PULL v2 36/39] target/riscv: Include missing headers in 'internals.h', Alistair Francis, 2024/12/19
- [PULL v2 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU,
Alistair Francis <=
- [PULL v2 38/39] target/riscv: add ssstateen, Alistair Francis, 2024/12/19
- Re: [PULL v2 00/39] riscv-to-apply queue, Stefan Hajnoczi, 2024/12/21