[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 37/39] target/riscv/tcg: hide warn for named feats when disabling
|
From: |
Alistair Francis |
|
Subject: |
[PULL 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver |
|
Date: |
Thu, 19 Dec 2024 08:30:07 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Commit 68c9e54bea handled a situation where a warning was being shown
when using the 'sifive_e' cpu when disabling the named extension zic64b.
It makes little sense to show user warnings for named extensions that
users can't control, and the solution taken was to disable zic64b
manually in riscv_cpu_update_named_features().
This solution won't scale well when adding more named features, and can
eventually end up repeating riscv_cpu_disable_priv_spec_isa_exts().
Change riscv_cpu_disable_priv_spec_isa_exts() to not show warnings when
disabling a named feature. This will accomplish the same thing we're
doing today while avoiding having two points where we're disabling
exts via priv_ver mismatch.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241113171755.978109-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 3b99c8c9e3..48a55ba1d8 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -304,6 +304,15 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU
*cpu)
}
isa_ext_update_enabled(cpu, edata->ext_enable_offset, false);
+
+ /*
+ * Do not show user warnings for named features that users
+ * can't enable/disable in the command line. See commit
+ * 68c9e54bea for more info.
+ */
+ if (cpu_cfg_offset_is_named_feat(edata->ext_enable_offset)) {
+ continue;
+ }
#ifndef CONFIG_USER_ONLY
warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
" because privilege spec version does not match",
@@ -331,11 +340,9 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu)
cpu->cfg.has_priv_1_13 = true;
}
- /* zic64b is 1.12 or later */
cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 &&
cpu->cfg.cbop_blocksize == 64 &&
- cpu->cfg.cboz_blocksize == 64 &&
- cpu->cfg.has_priv_1_12;
+ cpu->cfg.cboz_blocksize == 64;
}
static void riscv_cpu_validate_g(RISCVCPU *cpu)
--
2.47.1
- [PULL 32/39] target/riscv: Check memory access to meet svukte rule, (continued)
- [PULL 32/39] target/riscv: Check memory access to meet svukte rule, Alistair Francis, 2024/12/18
- [PULL 19/39] hw/riscv: Add Microblaze V generic board, Alistair Francis, 2024/12/18
- [PULL 22/39] tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V, Alistair Francis, 2024/12/18
- [PULL 26/39] hw/riscv: Support to load DTB after 3GB memory on 64-bit system., Alistair Francis, 2024/12/18
- [PULL 39/39] target/riscv: add support for RV64 Xiangshan Nanhu CPU, Alistair Francis, 2024/12/18
- [PULL 27/39] hw/riscv: Add a new struct RISCVBootInfo, Alistair Francis, 2024/12/18
- [PULL 20/39] qtest: allow SPCR acpi table changes, Alistair Francis, 2024/12/18
- [PULL 28/39] hw/riscv: Add the checking if DTB overlaps to kernel or initrd, Alistair Francis, 2024/12/18
- [PULL 31/39] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/18
- [PULL 33/39] target/riscv: Expose svukte ISA extension, Alistair Francis, 2024/12/18
- [PULL 37/39] target/riscv/tcg: hide warn for named feats when disabling via priv_ver,
Alistair Francis <=
- [PULL 17/39] target/riscv/kvm: remove irqchip_split() restriction, Alistair Francis, 2024/12/18
- [PULL 25/39] hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses, Alistair Francis, 2024/12/18
- [PULL 29/39] target/riscv: Add svukte extension capability variable, Alistair Francis, 2024/12/18
- [PULL 35/39] target/riscv: Include missing headers in 'vector_internals.h', Alistair Francis, 2024/12/18
- [PULL 34/39] target/riscv: Check svukte is not enabled in RV32, Alistair Francis, 2024/12/18
- [PULL 23/39] MAINTAINERS: Cover RISC-V HTIF interface, Alistair Francis, 2024/12/18
- [PULL 30/39] target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled, Alistair Francis, 2024/12/18
- [PULL 38/39] target/riscv: add ssstateen, Alistair Francis, 2024/12/18
- [PULL 18/39] docs: update riscv/virt.rst with kernel-irqchip=split support, Alistair Francis, 2024/12/18
- [PULL 36/39] target/riscv: Include missing headers in 'internals.h', Alistair Francis, 2024/12/18