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Re: [PATCH 3/3] target/riscv: fix the trap generation for conditional st
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH 3/3] target/riscv: fix the trap generation for conditional store |
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Date: |
Wed, 11 Dec 2024 15:43:02 -0600 |
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User-agent: |
Mozilla Thunderbird |
On 12/11/24 15:19, Frederic Konrad wrote:
+ /*
+ * A misaligned store trap should be triggered even if the store should
+ * fail due to the reservation.
+ */
+ tcg_gen_andi_tl(tmp, src1, ~((uint64_t)0) << memop_alignment_bits(mop));
The constant is incorrect for testing the low bits.
+ tcg_gen_brcond_tl(TCG_COND_EQ, tmp, src1, l3);
Best to make the fallthrough path be the common case, as we will optimize across the
extended basic block.
Use test-style comparison:
tcg_gen_brcondi_tl(TCG_COND_TSTNE, src1, memop_size(mop) - 1, l_misalign);
r~