Re: [PATCH v7 03/11] target/riscv: Add cycle & instret privilege mode filtering properties

[Atish Kumar Patra]

On Tue, Jul 2, 2024 at 7:03 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Thu, Jun 27, 2024 at 9:59 AM Atish Patra <atishp@rivosinc.com> wrote:
> >
> > From: Kaiwen Xue <kaiwenx@rivosinc.com>
> >
> > This adds the properties for ISA extension smcntrpmf. Patches
> > implementing it will follow.
> >
> > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
> > ---
> >  target/riscv/cpu.c     | 2 ++
> >  target/riscv/cpu_cfg.h | 1 +
> >  2 files changed, 3 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 4760cb2cc17f..ef50130a91e7 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -178,6 +178,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> >      ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
> >      ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
> >      ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
> > +    ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
> >      ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
> >      ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
> >      ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
> > @@ -1467,6 +1468,7 @@ const char *riscv_get_misa_ext_description(uint32_t 
> > bit)
> >  const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
> >      /* Defaults for standard extensions */
> >      MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
> > +    MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false),
>
> Exposing the config should be at the end of the series. Implement then expose
>

Sure. I will move this to the end of the series.

> Alistair
>
> >      MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
> >      MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true),
> >      MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
> > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> > index fb7eebde523b..b1376beb1dab 100644
> > --- a/target/riscv/cpu_cfg.h
> > +++ b/target/riscv/cpu_cfg.h
> > @@ -74,6 +74,7 @@ struct RISCVCPUConfig {
> >      bool ext_ztso;
> >      bool ext_smstateen;
> >      bool ext_sstc;
> > +    bool ext_smcntrpmf;
> >      bool ext_svadu;
> >      bool ext_svinval;
> >      bool ext_svnapot;
> >
> > --
> > 2.34.1
> >
> >