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[PATCH v2 01/11] target/riscv: do not mask unsupported QEMU extensions i
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From: |
Daniel Henrique Barboza |
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Subject: |
[PATCH v2 01/11] target/riscv: do not mask unsupported QEMU extensions in write_misa() |
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Date: |
Tue, 14 Feb 2023 16:23:46 -0300 |
The masking done using env->misa_ext_mask already filters any extension
that QEMU doesn't support. If the hart supports the extension then QEMU
supports it as well.
If the masking done by env->misa_ext_mask is somehow letting unsupported
QEMU extensions pass by, misa_ext_mask itself needs to be fixed instead.
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/csr.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1b0a0c1693..e149b453da 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1356,9 +1356,6 @@ static RISCVException write_misa(CPURISCVState *env, int
csrno,
/* Mask extensions that are not supported by this hart */
val &= env->misa_ext_mask;
- /* Mask extensions that are not supported by QEMU */
- val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
-
/* 'D' depends on 'F', so clear 'D' if 'F' is not present */
if ((val & RVD) && !(val & RVF)) {
val &= ~RVD;
--
2.39.1
- [PATCH v2 00/11] enable write_misa() and RISCV_FEATURE_* cleanups, Daniel Henrique Barboza, 2023/02/14
- [PATCH v2 01/11] target/riscv: do not mask unsupported QEMU extensions in write_misa(),
Daniel Henrique Barboza <=
- [PATCH v2 02/11] target/riscv: introduce riscv_cpu_cfg(), Daniel Henrique Barboza, 2023/02/14
- [PATCH v2 03/11] target/riscv: allow users to actually write the MISA CSR, Daniel Henrique Barboza, 2023/02/14
- [PATCH v2 04/11] target/riscv: remove RISCV_FEATURE_MISA, Daniel Henrique Barboza, 2023/02/14
- [PATCH v2 05/11] target/riscv: remove RISCV_FEATURE_DEBUG, Daniel Henrique Barboza, 2023/02/14
- [PATCH v2 06/11] target/riscv/cpu.c: error out if EPMP is enabled without PMP, Daniel Henrique Barboza, 2023/02/14