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[PATCH V1 3/3] amd-iommu: Fix amdvi_mmio_trace() to differentiate MMIO R
From: |
Wei Huang |
Subject: |
[PATCH V1 3/3] amd-iommu: Fix amdvi_mmio_trace() to differentiate MMIO R/W |
Date: |
Mon, 28 Sep 2020 15:05:06 -0500 |
amd-iommu MMIO trace function does not differentiate MMIO writes from
reads. Let us extend it to support both types.
Co-developed-by: Wei Huang <wei.huang2@amd.com>
Signed-off-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
---
hw/i386/amd_iommu.c | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 7604e2080595..827818b9f781 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -662,17 +662,28 @@ static void amdvi_cmdbuf_run(AMDVIState *s)
}
}
-static void amdvi_mmio_trace(hwaddr addr, unsigned size)
+static void amdvi_mmio_trace(hwaddr addr, unsigned size, bool iswrite,
+ uint64_t val)
{
uint8_t index = (addr & ~0x2000) / 8;
if ((addr & 0x2000)) {
/* high table */
index = index >= AMDVI_MMIO_REGS_HIGH ? AMDVI_MMIO_REGS_HIGH : index;
- trace_amdvi_mmio_read(amdvi_mmio_high[index], addr, size, addr &
~0x07);
+ if (!iswrite)
+ trace_amdvi_mmio_read(amdvi_mmio_high[index], addr, size,
+ addr & ~0x07);
+ else
+ trace_amdvi_mmio_write(amdvi_mmio_high[index], addr, size, val,
+ addr & ~0x07);
} else {
index = index >= AMDVI_MMIO_REGS_LOW ? AMDVI_MMIO_REGS_LOW : index;
- trace_amdvi_mmio_read(amdvi_mmio_low[index], addr, size, addr & ~0x07);
+ if (!iswrite)
+ trace_amdvi_mmio_read(amdvi_mmio_low[index], addr, size,
+ addr & ~0x07);
+ else
+ trace_amdvi_mmio_write(amdvi_mmio_low[index], addr, size, val,
+ addr & ~0x07);
}
}
@@ -693,7 +704,7 @@ static uint64_t amdvi_mmio_read(void *opaque, hwaddr addr,
unsigned size)
} else if (size == 8) {
val = amdvi_readq(s, addr);
}
- amdvi_mmio_trace(addr, size);
+ amdvi_mmio_trace(addr, size, 0, val);
return val;
}
@@ -840,7 +851,7 @@ static void amdvi_mmio_write(void *opaque, hwaddr addr,
uint64_t val,
return;
}
- amdvi_mmio_trace(addr, size);
+ amdvi_mmio_trace(addr, size, 1, val);
switch (addr & ~0x07) {
case AMDVI_MMIO_CONTROL:
amdvi_mmio_reg_write(s, size, val, addr);
--
2.25.2