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[Qemu-devel] [PATCH v3 07/21] RISC-V GDB Stub
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v3 07/21] RISC-V GDB Stub |
Date: |
Wed, 10 Jan 2018 18:21:50 -0800 |
GDB Register read and write routines.
Signed-off-by: Michael Clark <address@hidden>
---
target/riscv/gdbstub.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 target/riscv/gdbstub.c
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
new file mode 100644
index 0000000..12d1d9f
--- /dev/null
+++ b/target/riscv/gdbstub.c
@@ -0,0 +1,59 @@
+/*
+ * RISC-V GDB Server Stub
+ *
+ * Author: Sagar Karandikar, address@hidden
+ *
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "exec/gdbstub.h"
+#include "cpu.h"
+
+int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
+{
+ /* TODO proper x0 handling */
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+
+ if (n < 32) {
+ return gdb_get_regl(mem_buf, env->gpr[n]);
+ } else if (n == 32) {
+ return gdb_get_regl(mem_buf, env->pc);
+ } else if (n < 65) {
+ return gdb_get_reg64(mem_buf, env->fpr[n - 33]);
+ }
+ return 0;
+}
+
+int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
+{
+ /* TODO proper x0 handling */
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+
+ if (n < 32) {
+ env->gpr[n] = ldtul_p(mem_buf);
+ return sizeof(target_ulong);
+ } else if (n == 32) {
+ env->pc = ldtul_p(mem_buf);
+ return sizeof(target_ulong);
+ } else if (n < 65) {
+ env->fpr[n - 33] = ldq_p(mem_buf); /* always 64-bit */
+ return sizeof(uint64_t);
+ }
+ return 0;
+}
--
2.7.0
- [Qemu-devel] [PATCH v3 00/21] RISC-V QEMU Port Submission v3, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 01/21] RISC-V Maintainers, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 02/21] RISC-V ELF Machine Definition, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 06/21] RISC-V FPU Support, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 03/21] RISC-V CPU Core Definition, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 05/21] RISC-V CPU Helpers, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 07/21] RISC-V GDB Stub,
Michael Clark <=
- [Qemu-devel] [PATCH v3 09/21] RISC-V Physical Memory Protection, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 12/21] RISC-V HART Array, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 13/21] SiFive RISC-V CLINT Block, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 11/21] RISC-V HTIF Console, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 18/21] SiFive RISC-V PRCI Block, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 10/21] RISC-V Linux User Emulation, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 17/21] SiFive RISC-V UART Device, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 16/21] RISC-V VirtIO Machine, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure, Michael Clark, 2018/01/10