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[Qemu-devel] [PULL 15/30] arm: cpu: handle BE32 user-mode as BE
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 15/30] arm: cpu: handle BE32 user-mode as BE |
Date: |
Fri, 4 Mar 2016 11:41:38 +0000 |
From: Peter Crosthwaite <address@hidden>
endian with address manipulations on subword accesses (to give the
illusion of BE). But user-mode cannot tell the difference and is
already implemented as straight BE. So handle the difference in the
endianess query, where USER mode is BE and system is not.
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 75e5ea0..ab0ea92 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1915,7 +1915,22 @@ static inline bool
arm_cpu_data_is_big_endian(CPUARMState *env)
/* In 32bit endianness is determined by looking at CPSR's E bit */
if (!is_a64(env)) {
- return (env->uncached_cpsr & CPSR_E) ? 1 : 0;
+ return
+#ifdef CONFIG_USER_ONLY
+ /* In system mode, BE32 is modelled in line with the
+ * architecture (as word-invariant big-endianness), where loads
+ * and stores are done little endian but from addresses which
+ * are adjusted by XORing with the appropriate constant. So the
+ * endianness to use for the raw data access is not affected by
+ * SCTLR.B.
+ * In user mode, however, we model BE32 as byte-invariant
+ * big-endianness (because user-only code cannot tell the
+ * difference), and so we need to use a data access endianness
+ * that depends on SCTLR.B.
+ */
+ arm_sctlr_b(env) ||
+#endif
+ ((env->uncached_cpsr & CPSR_E) ? 1 : 0);
}
cur_el = arm_current_el(env);
--
1.9.1
- [Qemu-devel] [PULL 01/30] target-arm: Correct handling of writes to CPSR mode bits from gdb in usermode, (continued)
- [Qemu-devel] [PULL 01/30] target-arm: Correct handling of writes to CPSR mode bits from gdb in usermode, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 12/30] linux-user: arm: pass env to get_user_code_*, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 10/30] bcm2835_mbox/property: replace ldl_phys/stl_phys with endian-specific accesses, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 16/30] linux-user: arm: set CPSR.E/SCTLR.E0E correctly for BE mode, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 07/30] hw/arm/virt: Load bios image to MemoryRegion, not physaddr, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 14/30] target-arm: cpu: Move cpu_is_big_endian to header, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 22/30] target-arm: introduce tbflag for endianness, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 06/30] loader: Add load_image_mr() to load ROM image to a MemoryRegion, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 19/30] target-arm: pass DisasContext to gen_aa32_ld*/st*, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 08/30] hw/arm/virt: Make first flash device Secure-only if booting secure, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 15/30] arm: cpu: handle BE32 user-mode as BE,
Peter Maydell <=
- [Qemu-devel] [PULL 17/30] linux-user: arm: handle CPSR.E correctly in strex emulation, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 28/30] arm: boot: Support big-endian elfs, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 05/30] hw/arm/virt: Provide a secure-only RAM if booting in Secure mode, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 18/30] target-arm: implement SCTLR.EE, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 23/30] target-arm: implement setend, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 26/30] loader: load_elf(): Add doc comment, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 09/30] hw/arm/virt: Assume EL3 boot rom will handle PSCI if one is provided, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 11/30] linux-user: arm: fix coding style for some linux-user signal functions, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 13/30] target-arm: implement SCTLR.B, drop bswap_code, Peter Maydell, 2016/03/04
- [Qemu-devel] [PULL 21/30] target-arm: a64: Add endianness support, Peter Maydell, 2016/03/04