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[Qemu-block] [PATCH 7/9] tcg: add tcg_out_start
From: |
Paolo Bonzini |
Subject: |
[Qemu-block] [PATCH 7/9] tcg: add tcg_out_start |
Date: |
Sat, 4 May 2019 06:05:25 -0600 |
This function is called at the beginning of any translation block. We will
use it to emit ENDBR32 or ENDBR64 annotations for x86 CET.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
---
tcg/aarch64/tcg-target.inc.c | 4 ++++
tcg/arm/tcg-target.inc.c | 4 ++++
tcg/i386/tcg-target.inc.c | 4 ++++
tcg/mips/tcg-target.inc.c | 4 ++++
tcg/ppc/tcg-target.inc.c | 4 ++++
tcg/riscv/tcg-target.inc.c | 4 ++++
tcg/s390/tcg-target.inc.c | 4 ++++
tcg/sparc/tcg-target.inc.c | 4 ++++
tcg/tcg.c | 2 ++
tcg/tci/tcg-target.inc.c | 4 ++++
10 files changed, 38 insertions(+)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index eefa929948..c66f3cb857 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -2539,6 +2539,10 @@ QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
/* We're expecting to use a single ADDI insn. */
QEMU_BUILD_BUG_ON(FRAME_SIZE - PUSH_SIZE > 0xfff);
+static inline void tcg_out_start(TCGContext *s)
+{
+}
+
static void tcg_target_qemu_prologue(TCGContext *s)
{
TCGReg r;
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index abf0c444b4..8f919c7641 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -2284,6 +2284,10 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
}
}
+static inline void tcg_out_start(TCGContext *s)
+{
+}
+
/* Compute frame size via macros, to share between tcg_target_qemu_prologue
and tcg_register_jit. */
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index d5ed9f1ffd..b210977800 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -3510,6 +3510,10 @@ static const int tcg_target_callee_save_regs[] = {
+ TCG_TARGET_STACK_ALIGN - 1) \
& ~(TCG_TARGET_STACK_ALIGN - 1))
+static inline void tcg_out_start(TCGContext *s)
+{
+}
+
/* Generate global QEMU prologue and epilogue code */
static void tcg_target_qemu_prologue(TCGContext *s)
{
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 412cacdcb9..2bb976a9a5 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -2471,6 +2471,10 @@ static tcg_insn_unit *align_code_ptr(TCGContext *s)
return s->code_ptr;
}
+static inline void tcg_out_start(TCGContext *s)
+{
+}
+
/* Stack frame parameters. */
#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 36b4791707..f4efca8f7b 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -1904,6 +1904,10 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
}
}
+static inline void tcg_out_start(TCGContext *s)
+{
+}
+
/* Parameters for function call generation, used in tcg.c. */
#define TCG_TARGET_STACK_ALIGN 16
#define TCG_TARGET_EXTEND_ARGS 1
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 2932505094..5780537b73 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -1798,6 +1798,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
}
}
+static inline void tcg_out_start(TCGContext *s)
+{
+}
+
static const int tcg_target_callee_save_regs[] = {
TCG_REG_S0, /* used for the global env (TCG_AREG0) */
TCG_REG_S1,
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 3d6150b10e..924bd01afd 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -2499,6 +2499,10 @@ static void query_s390_facilities(void)
}
}
+static inline void tcg_out_start(TCGContext *s)
+{
+}
+
static void tcg_target_init(TCGContext *s)
{
query_s390_facilities();
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index 7a61839dc1..f795e78153 100644
--- a/tcg/sparc/tcg-target.inc.c
+++ b/tcg/sparc/tcg-target.inc.c
@@ -1004,6 +1004,10 @@ static void build_trampolines(TCGContext *s)
}
#endif
+static inline void tcg_out_start(TCGContext *s)
+{
+}
+
/* Generate global QEMU prologue and epilogue code */
static void tcg_target_qemu_prologue(TCGContext *s)
{
diff --git a/tcg/tcg.c b/tcg/tcg.c
index f7bef51de8..c8832c3ccf 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -101,6 +101,7 @@ static void tcg_register_jit_int(void *buf, size_t size,
/* Forward declarations for functions declared and used in tcg-target.inc.c. */
static const char *target_parse_constraint(TCGArgConstraint *ct,
const char *ct_str, TCGType type);
+static void tcg_out_start(TCGContext *s);
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
intptr_t arg2);
static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
@@ -3925,6 +3926,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
#endif
num_insns = -1;
+ tcg_out_start(s);
QTAILQ_FOREACH(op, &s->ops, link) {
TCGOpcode opc = op->opc;
diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c
index 0015a98485..cb90012999 100644
--- a/tcg/tci/tcg-target.inc.c
+++ b/tcg/tci/tcg-target.inc.c
@@ -889,6 +889,10 @@ static void tcg_target_init(TCGContext *s)
CPU_TEMP_BUF_NLONGS * sizeof(long));
}
+static inline void tcg_out_start(void)
+{
+}
+
/* Generate global QEMU prologue and epilogue code. */
static inline void tcg_target_qemu_prologue(TCGContext *s)
{
--
2.21.0
- [Qemu-block] [PATCH 1/9] qemugdb: allow adding support for other coroutine backends, (continued)
- [Qemu-block] [PATCH 1/9] qemugdb: allow adding support for other coroutine backends, Paolo Bonzini, 2019/05/04
- [Qemu-block] [PATCH 2/9] qemugdb: allow adding support for other architectures, Paolo Bonzini, 2019/05/04
- [Qemu-block] [PATCH 4/9] coroutine: add host specific coroutine backend for 64-bit ARM, Paolo Bonzini, 2019/05/04
- [Qemu-block] [PATCH 3/9] coroutine: add host specific coroutine backend for 64-bit x86, Paolo Bonzini, 2019/05/04
- [Qemu-block] [PATCH 5/9] coroutine: add host specific coroutine backend for 64-bit s390, Paolo Bonzini, 2019/05/04
- [Qemu-block] [PATCH 6/9] configure: add control-flow protection support, Paolo Bonzini, 2019/05/04
- [Qemu-block] [PATCH 7/9] tcg: add tcg_out_start,
Paolo Bonzini <=
- [Qemu-block] [PATCH 8/9] tcg/i386: add support for IBT, Paolo Bonzini, 2019/05/04
- [Qemu-block] [PATCH 9/9] linux-user: add IBT support to x86 safe-syscall.S, Paolo Bonzini, 2019/05/04
- [Qemu-block] [PATCH 10/9] coroutine-asm: add x86 CET shadow stack support, Paolo Bonzini, 2019/05/04
- Re: [Qemu-block] [Qemu-devel] [PATCH 0/9] Assembly coroutine backend and x86 CET support, Alex Bennée, 2019/05/05
Re: [Qemu-block] [Qemu-devel] [PATCH 0/9] Assembly coroutine backend and x86 CET support, Stefan Hajnoczi, 2019/05/09