Recursive make problem (bug?)

[Jason Elbaum]

I'm managing a system of makefiles, each of which builds a
subdirectory-based module of a larger system. The top-level makefile
invokes make recursively to build each of the parts. Pretty
conventional, so far.

Furthermore, each individual makefile also includes a standard, common,
template makefile which defines various standard targets. Thus the
structure is like this (in make-style psedocode):

Makefile (subdir a)
        include Makefile.standard

Makefile (subdir b)
        include Makefile.standard

Makefile (top-level)
        include Makefile.standard

        a:
                $(MAKE) -C a

        b:
                $(MAKE) -C b


The problem is that when Make calls itself recursively, it apparently
doesn't really open a new shell. It somehow reads in the new makefile
while retaining the currently-defined targets. As a result, I get a slew
of warning messages of the following sort:

Makefile.standard:10: warning: overriding commands for target `xyz'
Makefile.standard:10: warning: ignoring old commands for target `xyz'

This happens every time make is called recursively, and for every target
in the standard makefile.

Is there any way to change this behavior, either by forcing make to
reinvoke itself with a clean target environment, or at least by
disabling those annoying warnings?


Thanks,

Jason Elbaum
address@hidden