Re: make - problem with include during sub-make (recursive make)

[Paul D. Smith]

%% "Satheesh Kolathur" <address@hidden> writes:

Please always provide the version of GNU make you're using, and the
operating system you're running it on, when reporting problems or asking
for help.  Thanks!

  sk> I have the following problem with 'make'

  sk> ------------------------------------------------------------------------
  sk> include <filename1>
  sk> ..
  sk> clean
  sk>   cd ../subdir1/subdir2 && $(MAKE) clean
  sk> ------------------------------------------------------------------------

  sk> ------------------------------------------------------------------------
  sk> include <filename>
  sk> ..
  sk> if (condition)
  sk> VAR1 = $(VAR) xyz // $VAR is defines in the include file
  sk> endif

  sk> module:
  sk>   $(CC).....FLAGS.....$(VAR1).....
  sk> ------------------------------------------------------------------------

Did you really mean one of these to be "filename1" and one to be just
"filename", or are they both the same file?

  sk> when I execute $(MAKE) from the toplevel makefile, VAR1 is not
  sk> getting resolved.  There are few variables defined in the include
  sk> file 'filename1' Both the makefiles are including the same include
  sk> file 'filename1', but the sub-make file is not able to see these
  sk> variables when called from the top level make file.  However, when
  sk> the sublevel make is run independently, it works fine.

  sk> So I gave a export command on the toplevel make file so that all
  sk> the variables are exported thru the environment to the sub-make
  sk> files(because anyway the same file is included).  Now all of the
  sk> variables defined in the include file get known to the sub level
  sk> make file, but VAR1 is not resolved. Its empty. VAR1 is not
  sk> defined in the include file. It is constructed using a variable
  sk> VAR which is defined in the include file.

  sk> I dunno where things are wrong.

>From your pseudo-makefile and your description I cannot tell you what's
wrong.  You do not need to export things from the top-level makefile if
the same file is included in the sub makefile.

And there's no reason that VAR1 would not be resolved given your
description.

So, there must be a bug in your makefiles somewhere.


My first suggestion is you examine _carefully_ the condition in your
"if* (condition)" statement, because the most obvious answer is that
it's always evaluating to false, and so VAR1 is not set.  For example,
carefully check whitespace; if you have extra spaces at inappropriate
places that can cause values to be considered not equal.

If that doesn't help you'll need to create a short _real_ example
showing the problem so we can see what you're really doing.

-- 
-------------------------------------------------------------------------------
 Paul D. Smith <address@hidden>          Find some GNU make tips at:
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 "Please remain calm...I may be mad, but I am a professional." --Mad Scientist