Re: Deriving dependency from target

[Paul D. Smith]

%% Eitan Rabin <address@hidden> writes:
 
  er> $(TARGET): $($(@:%=%_SOURCES))
  er>     gcc ...
 
  er> This doesn't work.

Correct.
 
  er> Is there a similar way to create such makefile without having to
  er> create temporary makefiles.
 
No.  Not right now.

Note, though, that GNU make can make creating these temporary makefiles
much more painless (although you do need to run make twice, it's done
automatically for you so you don't have to do it by hand) via to its
auto-re-exec feature.

  er> 2) I was curious to know what is the reason that variable in
  er> dependencies are replaced immediatly. This requires to make all
  er> variable definition before the rules which is not clean in many
  er> cases. Anyone know the reason for that?

Because that's how make has behaved for 30+ years and how the POSIX
standard specifies it, and hundreds of thousands of makefiles already
exist, of which a large fraction would not work if changes like this
were made.

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