Re: gnu make

[Paul D. Smith]

%% address@hidden writes:

  jk> > cat makefile 
  jk> include tmp.mk 

  jk> %.o: %.c 
  jk>   echo "Compiling" 
  jk>   gcc -c  $< -o $@ 

  jk> SRCS = t.c 

  jk> > cat tmp.mk 
  jk> OBJ = $(SRCS:.c=.o) 

  jk> lib : $(OBJ) 
  jk>   echo $(SRCS) 

So, after the include your makefile looks like this:

  OBJ = $(SRCS:.c=.o) 

  lib : $(OBJ) 
        echo $(SRCS) 

  %.o: %.c 
        echo "Compiling" 
        gcc -c  $< -o $@ 

  SRCS = t.c 

The problem is that SRCS is not defined yet when OBJ is used as a
prerequisite of the lib target, so $(OBJ) resolves to the empty string.

-- 
-------------------------------------------------------------------------------
 Paul D. Smith <address@hidden>          Find some GNU make tips at:
 http://www.gnu.org                      http://www.paulandlesley.org/gmake/
 "Please remain calm...I may be mad, but I am a professional." --Mad Scientist