sequence in a rule

[Angelika Kratochwil]

hello!

I've got this vhdl code: 
signal hit,test,works : OUT std_logic;
signal gameover : out std_logic;
signal reset_n : in std_logic;
signal do_step : in std_logic

it works when i have in one row just one signal, but if i have a sequence, 
it didn't.
my bison code looks like that:
input:?????????????????????????? /* empty string */
?????? | input line
?????? ;
line: NEWLINE
?????? | fullSignal NEWLINE???????????????????? { /*printf("\t%.10g\n",$1); 
*/}
?????? ;
fullSignal: fullSignal SEMICOLON SIGNAL asig sigio STRING???? 
{printf("fullSignal");}
?????? ?????? ?????? |SIGNAL asig sigio STRING?????? ?????? 
{printf("fullSignal");}
?????? ?????? ;
asig: asig COMMA STRING ?????? { printf("signal: %s",$3);}
?????? | STRING?????? ?????? { printf("signal: %s",$1);}
?????? ;
sigio : COLON SOUT {printf("Typ: out");}
?????? | COLON SIN {printf("Typ: in");}
?????? ;

has anyone an idea how i can merge a sequence? the problem is the "asig" 
rule in the rule "fullSignal". Please help me, I have no idea how I can 
solve that. 

cheers angelika        
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