[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Commit-gnuradio] git://gnuradio.org/jblum branch, master, updated. e259
|
From: |
git repository hosting |
|
Subject: |
[Commit-gnuradio] git://gnuradio.org/jblum branch, master, updated. e259d4d2eeb0b152e1e042333a8b36e07f5ad094 |
|
Date: |
Wed, 3 Mar 2010 18:45:09 +0000 (GMT) |
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "git://gnuradio.org/jblum".
The branch, master has been updated
via e259d4d2eeb0b152e1e042333a8b36e07f5ad094 (commit)
via b811e8749dcd7c96f1af2d98caba403e50c1602b (commit)
via 97275c32783a8831c7eac3786257fe2e142d95c0 (commit)
via 4c296bd1f0e7769db69ca15bcc528802b06f752c (commit)
via a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3 (commit)
via 752df2b84454756685dc2a05c232b59e3ebdaa2e (commit)
via 803cb1d7974ed7d419550cc66480c107c2f0d454 (commit)
via db29a2cfc18554ae0a3c55a4e13dc4cbfa86317f (commit)
from 48850cce5609941289c00fea9cd3493624bf7376 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit e259d4d2eeb0b152e1e042333a8b36e07f5ad094
Author: Josh Blum <address@hidden>
Date: Wed Mar 3 10:00:27 2010 -0800
If the directory is read-only, use the systems tmp directory for generated
py files.
commit b811e8749dcd7c96f1af2d98caba403e50c1602b
Merge: 97275c32783a8831c7eac3786257fe2e142d95c0
4c296bd1f0e7769db69ca15bcc528802b06f752c
Author: Johnathan Corgan <address@hidden>
Date: Tue Mar 2 09:15:09 2010 -0800
Merge branch 'usrp2_set_ant' of git://gnuradio.org/jblum
commit 97275c32783a8831c7eac3786257fe2e142d95c0
Author: Johnathan Corgan <address@hidden>
Date: Tue Mar 2 08:08:18 2010 -0800
Add README for new FPGA hosting location
commit a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3
Author: Johnathan Corgan <address@hidden>
Date: Sun Feb 28 12:47:43 2010 -0800
Remove usrp1 and usrp2 FPGA files. These are now hosted at:
git://ettus.sourcerepo.com/ettus/fpga.git
...under the 'usrp1' and 'usrp2' top-level directories.
-----------------------------------------------------------------------
Summary of changes:
gr-usrp2/src/usrp2.i | 2 +
gr-usrp2/src/usrp2_sink_base.cc | 8 +-
gr-usrp2/src/usrp2_sink_base.h | 7 +-
gr-usrp2/src/usrp2_source_base.cc | 6 +
gr-usrp2/src/usrp2_source_base.h | 7 +-
grc/python/Generator.py | 7 +-
grc/python/Platform.py | 4 +-
usrp/fpga/Makefile.am | 2 -
usrp/fpga/Makefile.extra | 181 -
usrp/fpga/README | 3 +
usrp/fpga/TODO | 23 -
usrp/fpga/gen_makefile_extra.py | 67 -
usrp/fpga/inband_lib/chan_fifo_reader.v | 219 -
usrp/fpga/inband_lib/channel_demux.v | 78 -
usrp/fpga/inband_lib/channel_ram.v | 107 -
usrp/fpga/inband_lib/cmd_reader.v | 305 -
usrp/fpga/inband_lib/packet_builder.v | 152 -
usrp/fpga/inband_lib/register_io.v | 82 -
usrp/fpga/inband_lib/rx_buffer_inband.v | 209 -
usrp/fpga/inband_lib/tx_buffer_inband.v | 143 -
usrp/fpga/inband_lib/tx_packer.v | 119 -
usrp/fpga/inband_lib/usb_packet_fifo.v | 112 -
usrp/fpga/megacells/.gitignore | 1 -
usrp/fpga/megacells/accum32.bsf | 86 -
usrp/fpga/megacells/accum32.cmp | 31 -
usrp/fpga/megacells/accum32.inc | 32 -
usrp/fpga/megacells/accum32.v | 765 -
usrp/fpga/megacells/accum32_bb.v | 35 -
usrp/fpga/megacells/accum32_inst.v | 7 -
usrp/fpga/megacells/add32.bsf | 62 -
usrp/fpga/megacells/add32.cmp | 29 -
usrp/fpga/megacells/add32.inc | 30 -
usrp/fpga/megacells/add32.v | 221 -
usrp/fpga/megacells/add32_bb.v | 31 -
usrp/fpga/megacells/add32_inst.v | 5 -
usrp/fpga/megacells/addsub16.bsf | 96 -
usrp/fpga/megacells/addsub16.cmp | 33 -
usrp/fpga/megacells/addsub16.inc | 34 -
usrp/fpga/megacells/addsub16.v | 438 -
usrp/fpga/megacells/addsub16_bb.v | 39 -
usrp/fpga/megacells/addsub16_inst.v | 9 -
usrp/fpga/megacells/bustri.bsf | 62 -
usrp/fpga/megacells/bustri.cmp | 29 -
usrp/fpga/megacells/bustri.inc | 30 -
usrp/fpga/megacells/bustri.v | 71 -
usrp/fpga/megacells/bustri_bb.v | 31 -
usrp/fpga/megacells/bustri_inst.v | 5 -
usrp/fpga/megacells/clk_doubler.v | 198 -
usrp/fpga/megacells/clk_doubler_bb.v | 143 -
usrp/fpga/megacells/dspclkpll.v | 237 -
usrp/fpga/megacells/dspclkpll_bb.v | 31 -
usrp/fpga/megacells/fifo_1kx16.bsf | 107 -
usrp/fpga/megacells/fifo_1kx16.cmp | 30 -
usrp/fpga/megacells/fifo_1kx16.inc | 31 -
usrp/fpga/megacells/fifo_1kx16.v | 175 -
usrp/fpga/megacells/fifo_1kx16_bb.v | 127 -
usrp/fpga/megacells/fifo_1kx16_inst.v | 12 -
usrp/fpga/megacells/fifo_2k.v | 3343 -
usrp/fpga/megacells/fifo_2k_bb.v | 131 -
usrp/fpga/megacells/fifo_4k.v | 3495 -
usrp/fpga/megacells/fifo_4k_18.v | 186 -
usrp/fpga/megacells/fifo_4k_bb.v | 131 -
usrp/fpga/megacells/fifo_4kx16_dc.bsf | 117 -
usrp/fpga/megacells/fifo_4kx16_dc.cmp | 31 -
usrp/fpga/megacells/fifo_4kx16_dc.inc | 32 -
usrp/fpga/megacells/fifo_4kx16_dc.v | 178 -
usrp/fpga/megacells/fifo_4kx16_dc_bb.v | 130 -
usrp/fpga/megacells/fifo_4kx16_dc_inst.v | 13 -
usrp/fpga/megacells/mylpm_addsub.bsf | 80 -
usrp/fpga/megacells/mylpm_addsub.cmp | 31 -
usrp/fpga/megacells/mylpm_addsub.inc | 32 -
usrp/fpga/megacells/mylpm_addsub.v | 102 -
usrp/fpga/megacells/mylpm_addsub_bb.v | 35 -
usrp/fpga/megacells/mylpm_addsub_inst.v | 7 -
usrp/fpga/megacells/pll.v | 207 -
usrp/fpga/megacells/pll_bb.v | 29 -
usrp/fpga/megacells/pll_inst.v | 4 -
usrp/fpga/megacells/sub32.bsf | 87 -
usrp/fpga/megacells/sub32.cmp | 32 -
usrp/fpga/megacells/sub32.inc | 33 -
usrp/fpga/megacells/sub32.v | 675 -
usrp/fpga/megacells/sub32_bb.v | 37 -
usrp/fpga/megacells/sub32_inst.v | 8 -
usrp/fpga/models/bustri.v | 17 -
usrp/fpga/models/fifo.v | 82 -
usrp/fpga/models/fifo_1c_1k.v | 81 -
usrp/fpga/models/fifo_1c_2k.v | 81 -
usrp/fpga/models/fifo_1c_4k.v | 76 -
usrp/fpga/models/fifo_1k.v | 24 -
usrp/fpga/models/fifo_2k.v | 24 -
usrp/fpga/models/fifo_4k.v | 24 -
usrp/fpga/models/fifo_4k_18.v | 26 -
usrp/fpga/models/pll.v | 33 -
usrp/fpga/models/ssram.v | 38 -
usrp/fpga/sdr_lib/.gitignore | 2 -
usrp/fpga/sdr_lib/adc_interface.v | 71 -
usrp/fpga/sdr_lib/atr_delay.v | 83 -
usrp/fpga/sdr_lib/bidir_reg.v | 29 -
usrp/fpga/sdr_lib/cic_dec_shifter.v | 100 -
usrp/fpga/sdr_lib/cic_decim.v | 93 -
usrp/fpga/sdr_lib/cic_int_shifter.v | 94 -
usrp/fpga/sdr_lib/cic_interp.v | 90 -
usrp/fpga/sdr_lib/clk_divider.v | 43 -
usrp/fpga/sdr_lib/cordic.v | 109 -
usrp/fpga/sdr_lib/cordic_stage.v | 60 -
usrp/fpga/sdr_lib/ddc.v | 97 -
usrp/fpga/sdr_lib/dpram.v | 47 -
usrp/fpga/sdr_lib/duc.v | 95 -
usrp/fpga/sdr_lib/ext_fifo.v | 126 -
usrp/fpga/sdr_lib/gen_cordic_consts.py | 10 -
usrp/fpga/sdr_lib/gen_sync.v | 43 -
usrp/fpga/sdr_lib/hb/acc.v | 22 -
usrp/fpga/sdr_lib/hb/coeff_rom.v | 19 -
usrp/fpga/sdr_lib/hb/halfband_decim.v | 163 -
usrp/fpga/sdr_lib/hb/halfband_interp.v | 121 -
usrp/fpga/sdr_lib/hb/hbd_tb/HBD | 80 -
usrp/fpga/sdr_lib/hb/hbd_tb/really_golden | 142 -
usrp/fpga/sdr_lib/hb/hbd_tb/regression | 95 -
usrp/fpga/sdr_lib/hb/hbd_tb/run_hbd | 4 -
usrp/fpga/sdr_lib/hb/hbd_tb/test_hbd.v | 75 -
usrp/fpga/sdr_lib/hb/mac.v | 58 -
usrp/fpga/sdr_lib/hb/mult.v | 16 -
usrp/fpga/sdr_lib/hb/ram16_2port.v | 22 -
usrp/fpga/sdr_lib/hb/ram16_2sum.v | 27 -
usrp/fpga/sdr_lib/hb/ram32_2sum.v | 22 -
usrp/fpga/sdr_lib/io_pins.v | 52 -
usrp/fpga/sdr_lib/master_control.v | 163 -
usrp/fpga/sdr_lib/master_control_multi.v | 73 -
usrp/fpga/sdr_lib/phase_acc.v | 52 -
usrp/fpga/sdr_lib/ram.v | 16 -
usrp/fpga/sdr_lib/ram16.v | 17 -
usrp/fpga/sdr_lib/ram32.v | 17 -
usrp/fpga/sdr_lib/ram64.v | 16 -
usrp/fpga/sdr_lib/rssi.v | 30 -
usrp/fpga/sdr_lib/rx_buffer.v | 237 -
usrp/fpga/sdr_lib/rx_chain.v | 106 -
usrp/fpga/sdr_lib/rx_chain_dual.v | 103 -
usrp/fpga/sdr_lib/rx_dcoffset.v | 22 -
usrp/fpga/sdr_lib/serial_io.v | 118 -
usrp/fpga/sdr_lib/setting_reg.v | 23 -
usrp/fpga/sdr_lib/setting_reg_masked.v | 26 -
usrp/fpga/sdr_lib/sign_extend.v | 35 -
usrp/fpga/sdr_lib/strobe_gen.v | 46 -
usrp/fpga/sdr_lib/tx_buffer.v | 170 -
usrp/fpga/sdr_lib/tx_chain.v | 65 -
usrp/fpga/sdr_lib/tx_chain_hb.v | 76 -
usrp/fpga/tb/.gitignore | 3 -
usrp/fpga/tb/cbus_tb.v | 71 -
usrp/fpga/tb/cordic_tb.v | 61 -
usrp/fpga/tb/decim_tb.v | 108 -
usrp/fpga/tb/fullchip_tb.v | 174 -
usrp/fpga/tb/interp_tb.v | 108 -
usrp/fpga/tb/justinterp_tb.v | 73 -
usrp/fpga/tb/makesine.pl | 14 -
usrp/fpga/tb/run_cordic | 4 -
usrp/fpga/tb/run_fullchip | 4 -
usrp/fpga/tb/usrp_tasks.v | 145 -
.../toplevel/include/common_config_1rxhb_1tx.vh | 61 -
.../fpga/toplevel/include/common_config_2rx_0tx.vh | 61 -
.../toplevel/include/common_config_2rxhb_0tx.vh | 61 -
.../toplevel/include/common_config_2rxhb_2tx.vh | 61 -
.../fpga/toplevel/include/common_config_4rx_0tx.vh | 61 -
usrp/fpga/toplevel/include/common_config_bottom.vh | 104 -
usrp/fpga/toplevel/mrfm/.gitignore | 17 -
usrp/fpga/toplevel/mrfm/biquad_2stage.v | 131 -
usrp/fpga/toplevel/mrfm/biquad_6stage.v | 137 -
usrp/fpga/toplevel/mrfm/mrfm.csf | 444 -
usrp/fpga/toplevel/mrfm/mrfm.esf | 14 -
usrp/fpga/toplevel/mrfm/mrfm.psf | 312 -
usrp/fpga/toplevel/mrfm/mrfm.py | 129 -
usrp/fpga/toplevel/mrfm/mrfm.qpf | 29 -
usrp/fpga/toplevel/mrfm/mrfm.qsf | 411 -
usrp/fpga/toplevel/mrfm/mrfm.v | 199 -
usrp/fpga/toplevel/mrfm/mrfm.vh | 21 -
usrp/fpga/toplevel/mrfm/mrfm_compensator.v | 80 -
usrp/fpga/toplevel/mrfm/mrfm_fft.py | 319 -
usrp/fpga/toplevel/mrfm/mrfm_proc.v | 96 -
usrp/fpga/toplevel/mrfm/shifter.v | 106 -
usrp/fpga/toplevel/sizetest/.gitignore | 15 -
usrp/fpga/toplevel/sizetest/sizetest.csf | 160 -
usrp/fpga/toplevel/sizetest/sizetest.psf | 228 -
usrp/fpga/toplevel/sizetest/sizetest.quartus | 19 -
usrp/fpga/toplevel/sizetest/sizetest.ssf | 14 -
usrp/fpga/toplevel/sizetest/sizetest.v | 39 -
usrp/fpga/toplevel/usrp_inband_usb/.gitignore | 16 -
usrp/fpga/toplevel/usrp_inband_usb/config.vh | 53 -
.../toplevel/usrp_inband_usb/usrp_inband_usb.csf | 444 -
.../toplevel/usrp_inband_usb/usrp_inband_usb.esf | 14 -
.../toplevel/usrp_inband_usb/usrp_inband_usb.psf | 312 -
.../toplevel/usrp_inband_usb/usrp_inband_usb.qpf | 29 -
.../toplevel/usrp_inband_usb/usrp_inband_usb.qsf | 423 -
.../toplevel/usrp_inband_usb/usrp_inband_usb.v | 428 -
usrp/fpga/toplevel/usrp_multi/.gitignore | 16 -
usrp/fpga/toplevel/usrp_multi/config.vh | 62 -
usrp/fpga/toplevel/usrp_multi/usrp_multi.csf | 444 -
usrp/fpga/toplevel/usrp_multi/usrp_multi.esf | 14 -
usrp/fpga/toplevel/usrp_multi/usrp_multi.psf | 312 -
usrp/fpga/toplevel/usrp_multi/usrp_multi.qpf | 29 -
usrp/fpga/toplevel/usrp_multi/usrp_multi.qsf | 408 -
usrp/fpga/toplevel/usrp_multi/usrp_multi.v | 379 -
usrp/fpga/toplevel/usrp_std/.gitignore | 17 -
usrp/fpga/toplevel/usrp_std/config.vh | 53 -
usrp/fpga/toplevel/usrp_std/usrp_std.csf | 444 -
usrp/fpga/toplevel/usrp_std/usrp_std.esf | 14 -
usrp/fpga/toplevel/usrp_std/usrp_std.psf | 312 -
usrp/fpga/toplevel/usrp_std/usrp_std.qpf | 29 -
usrp/fpga/toplevel/usrp_std/usrp_std.qsf | 409 -
usrp/fpga/toplevel/usrp_std/usrp_std.v | 333 -
usrp2/firmware/apps/.gitignore | 1 +
usrp2/firmware/apps/Makefile.am | 4 +
usrp2/firmware/apps/app_common_v2.c | 8 +
usrp2/firmware/include/usrp2_eth_packet.h | 6 +-
usrp2/firmware/lib/Makefile.am | 41 +-
usrp2/firmware/lib/db.h | 5 +-
usrp2/firmware/lib/db_base.h | 1 +
usrp2/firmware/lib/db_basic.c | 4 +
usrp2/firmware/lib/db_dbsrx.c | 1 +
usrp2/firmware/lib/db_init.c | 12 +-
usrp2/firmware/lib/db_init_wbx.c | 7 +
.../firmware/lib/{db_init_wbx.c => db_init_xcvr.c} | 15 +-
usrp2/firmware/lib/db_rfx.c | 10 +
usrp2/firmware/lib/db_tvrx.c | 3 +
usrp2/firmware/lib/db_wbxng.c | 2 +
usrp2/firmware/lib/db_xcvr2450.c | 25 +
usrp2/fpga/.gitignore | 2 -
usrp2/fpga/README | 3 +
usrp2/fpga/boot_cpld/.gitignore | 38 -
usrp2/fpga/boot_cpld/_impact.cmd | 34 -
usrp2/fpga/boot_cpld/boot_cpld.ipf | Bin 2967 -> 0 bytes
usrp2/fpga/boot_cpld/boot_cpld.ise | Bin 227573 -> 0 bytes
usrp2/fpga/boot_cpld/boot_cpld.lfp | 5 -
usrp2/fpga/boot_cpld/boot_cpld.ucf | 34 -
usrp2/fpga/boot_cpld/boot_cpld.v | 95 -
usrp2/fpga/control_lib/.gitignore | 5 -
usrp2/fpga/control_lib/CRC16_D16.v | 89 -
usrp2/fpga/control_lib/SYSCTRL.sav | 24 -
usrp2/fpga/control_lib/WB_SIM.sav | 47 -
usrp2/fpga/control_lib/atr_controller.v | 57 -
usrp2/fpga/control_lib/bin2gray.v | 10 -
usrp2/fpga/control_lib/bootrom.mem | 26 -
usrp2/fpga/control_lib/clock_bootstrap_rom.v | 34 -
usrp2/fpga/control_lib/clock_control.v | 115 -
usrp2/fpga/control_lib/clock_control_tb.sav | 28 -
usrp2/fpga/control_lib/clock_control_tb.v | 35 -
usrp2/fpga/control_lib/cmdfile | 18 -
usrp2/fpga/control_lib/dcache.v | 165 -
usrp2/fpga/control_lib/decoder_3_8.v | 21 -
usrp2/fpga/control_lib/dpram32.v | 82 -
usrp2/fpga/control_lib/fifo_tb.v | 151 -
usrp2/fpga/control_lib/gray2bin.v | 13 -
usrp2/fpga/control_lib/gray_send.v | 29 -
usrp2/fpga/control_lib/icache.v | 135 -
usrp2/fpga/control_lib/longfifo.v | 150 -
usrp2/fpga/control_lib/medfifo.v | 49 -
usrp2/fpga/control_lib/mux4.v | 16 -
usrp2/fpga/control_lib/mux8.v | 21 -
usrp2/fpga/control_lib/mux_32_4.v | 13 -
usrp2/fpga/control_lib/newfifo/.gitignore | 1 -
usrp2/fpga/control_lib/newfifo/buffer_int.v | 168 -
usrp2/fpga/control_lib/newfifo/buffer_int_tb.v | 418 -
usrp2/fpga/control_lib/newfifo/buffer_pool.v | 283 -
usrp2/fpga/control_lib/newfifo/buffer_pool_tb.v | 58 -
usrp2/fpga/control_lib/newfifo/fifo19_to_fifo36.v | 71 -
usrp2/fpga/control_lib/newfifo/fifo19_to_ll8.v | 53 -
usrp2/fpga/control_lib/newfifo/fifo36_to_fifo18.v | 40 -
usrp2/fpga/control_lib/newfifo/fifo36_to_fifo19.v | 41 -
usrp2/fpga/control_lib/newfifo/fifo36_to_ll8.v | 60 -
usrp2/fpga/control_lib/newfifo/fifo_2clock.v | 117 -
.../fpga/control_lib/newfifo/fifo_2clock_cascade.v | 35 -
usrp2/fpga/control_lib/newfifo/fifo_cascade.v | 52 -
usrp2/fpga/control_lib/newfifo/fifo_long.v | 148 -
usrp2/fpga/control_lib/newfifo/fifo_new_tb.vcd | 5506 -
usrp2/fpga/control_lib/newfifo/fifo_short.v | 95 -
usrp2/fpga/control_lib/newfifo/fifo_spec.txt | 36 -
usrp2/fpga/control_lib/newfifo/fifo_tb.v | 158 -
usrp2/fpga/control_lib/newfifo/ll8_shortfifo.v | 13 -
usrp2/fpga/control_lib/newfifo/ll8_to_fifo19.v | 77 -
usrp2/fpga/control_lib/newfifo/ll8_to_fifo36.v | 97 -
usrp2/fpga/control_lib/nsgpio.v | 107 -
usrp2/fpga/control_lib/oneshot_2clk.v | 35 -
usrp2/fpga/control_lib/pic.v | 183 -
usrp2/fpga/control_lib/priority_enc.v | 44 -
usrp2/fpga/control_lib/ram_2port.v | 42 -
usrp2/fpga/control_lib/ram_harv_cache.v | 75 -
usrp2/fpga/control_lib/ram_loader.v | 225 -
usrp2/fpga/control_lib/ram_wb_harvard.v | 86 -
usrp2/fpga/control_lib/reset_sync.v | 16 -
usrp2/fpga/control_lib/sd_spi.v | 70 -
usrp2/fpga/control_lib/sd_spi_tb.v | 40 -
usrp2/fpga/control_lib/sd_spi_wb.v | 76 -
usrp2/fpga/control_lib/setting_reg.v | 23 -
usrp2/fpga/control_lib/settings_bus.v | 49 -
usrp2/fpga/control_lib/shortfifo.v | 87 -
usrp2/fpga/control_lib/simple_uart.v | 61 -
usrp2/fpga/control_lib/simple_uart_rx.v | 64 -
usrp2/fpga/control_lib/simple_uart_tx.v | 60 -
usrp2/fpga/control_lib/spi.v | 84 -
usrp2/fpga/control_lib/srl.v | 21 -
usrp2/fpga/control_lib/ss_rcvr.v | 81 -
usrp2/fpga/control_lib/system_control.v | 47 -
usrp2/fpga/control_lib/system_control_tb.v | 57 -
usrp2/fpga/control_lib/traffic_cop.v | 25 -
usrp2/fpga/control_lib/wb_1master.v | 464 -
usrp2/fpga/control_lib/wb_bridge_16_32.v | 36 -
usrp2/fpga/control_lib/wb_bus_writer.v | 57 -
usrp2/fpga/control_lib/wb_output_pins32.v | 49 -
usrp2/fpga/control_lib/wb_ram_block.v | 36 -
usrp2/fpga/control_lib/wb_ram_dist.v | 33 -
usrp2/fpga/control_lib/wb_readback_mux.v | 60 -
usrp2/fpga/control_lib/wb_regfile_2clock.v | 107 -
usrp2/fpga/control_lib/wb_semaphore.v | 42 -
usrp2/fpga/control_lib/wb_sim.v | 79 -
usrp2/fpga/coregen/.gitignore | 3 -
usrp2/fpga/coregen/coregen.cgp | 20 -
.../fpga/coregen/fifo_generator_release_notes.txt | 160 -
usrp2/fpga/coregen/fifo_generator_ug175.pdf | Bin 1069823 -> 0 bytes
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.ngc | 3 -
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.v | 169 -
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.veo | 53 -
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.xco | 82 -
...o_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso | 3 -
...x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt | 103 -
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_flist.txt | 8 -
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_readme.txt | 39 -
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl | 68 -
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.asy | 49 -
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.ngc | 3 -
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.sym | 74 -
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.v | 173 -
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.veo | 53 -
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vhd | 156 -
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vho | 76 -
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.xco | 82 -
...o_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso | 3 -
...x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt | 106 -
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_flist.txt | 12 -
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_readme.txt | 55 -
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl | 84 -
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.asy | 49 -
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.ngc | 3 -
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.sym | 74 -
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.v | 169 -
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.veo | 53 -
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.vhd | 156 -
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.vho | 76 -
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.xco | 82 -
..._xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso | 3 -
...x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt | 109 -
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_flist.txt | 8 -
.../fpga/coregen/fifo_xlnx_512x36_2clk_readme.txt | 39 -
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl | 68 -
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.ngc | 3 -
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.v | 169 -
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.veo | 53 -
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.xco | 82 -
...o_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso | 3 -
...x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt | 104 -
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_flist.txt | 8 -
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_readme.txt | 39 -
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl | 68 -
usrp2/fpga/extram/.gitignore | 1 -
usrp2/fpga/extram/extram_interface.v | 53 -
usrp2/fpga/extram/extram_wb.v | 146 -
usrp2/fpga/extram/wb_zbt16_b.v | 63 -
usrp2/fpga/models/BUFG.v | 33 -
usrp2/fpga/models/CY7C1356C/cy1356.inp | 140 -
usrp2/fpga/models/CY7C1356C/cy1356.v | 485 -
usrp2/fpga/models/CY7C1356C/readme.txt | 33 -
usrp2/fpga/models/CY7C1356C/testbench.v | 189 -
usrp2/fpga/models/FIFO_GENERATOR_V4_3.v | 3494 -
usrp2/fpga/models/M24LC024B.v | 459 -
usrp2/fpga/models/M24LC02B.v | 455 -
usrp2/fpga/models/MULT18X18S.v | 20 -
usrp2/fpga/models/RAMB16_S36_S36.v | 2194 -
usrp2/fpga/models/SRL16E.v | 53 -
usrp2/fpga/models/SRLC16E.v | 61 -
usrp2/fpga/models/adc_model.v | 48 -
usrp2/fpga/models/cpld_model.v | 96 -
usrp2/fpga/models/math_real.v | 495 -
usrp2/fpga/models/miim_model.v | 14 -
usrp2/fpga/models/phy_sim.v | 113 -
usrp2/fpga/models/serdes_model.v | 34 -
usrp2/fpga/models/uart_rx.v | 48 -
usrp2/fpga/models/xlnx_glbl.v | 29 -
usrp2/fpga/opencores/8b10b/.gitignore | 2 -
usrp2/fpga/opencores/8b10b/8b10b_a.mem | 268 -
usrp2/fpga/opencores/8b10b/README | 4 -
usrp2/fpga/opencores/8b10b/decode_8b10b.v | 165 -
usrp2/fpga/opencores/8b10b/encode_8b10b.v | 120 -
usrp2/fpga/opencores/8b10b/validate_8b10b.v | 168 -
usrp2/fpga/opencores/README | 11 -
usrp2/fpga/opencores/aemb/CVS/.gitignore | 1 -
usrp2/fpga/opencores/aemb/CVS/Entries | 4 -
usrp2/fpga/opencores/aemb/CVS/Repository | 1 -
usrp2/fpga/opencores/aemb/CVS/Root | 1 -
usrp2/fpga/opencores/aemb/doc/CVS/Entries | 2 -
usrp2/fpga/opencores/aemb/doc/CVS/Repository | 1 -
usrp2/fpga/opencores/aemb/doc/CVS/Root | 1 -
usrp2/fpga/opencores/aemb/doc/aeMB_datasheet.pdf | Bin 119495 -> 0 bytes
usrp2/fpga/opencores/aemb/rtl/CVS/Entries | 1 -
usrp2/fpga/opencores/aemb/rtl/CVS/Repository | 1 -
usrp2/fpga/opencores/aemb/rtl/CVS/Root | 1 -
usrp2/fpga/opencores/aemb/rtl/verilog/.gitignore | 1 -
usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Entries | 38 -
.../fpga/opencores/aemb/rtl/verilog/CVS/Repository | 1 -
usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Root | 1 -
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_bpcu.v | 184 -
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_core.v | 137 -
.../fpga/opencores/aemb/rtl/verilog/aeMB_core_BE.v | 62 -
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ctrl.v | 336 -
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v | 289 -
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v | 192 -
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_regf.v | 241 -
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_sim.v | 312 -
usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v | 412 -
usrp2/fpga/opencores/aemb/sim/.gitignore | 4 -
usrp2/fpga/opencores/aemb/sim/CODE_DEBUG.sav | 16 -
usrp2/fpga/opencores/aemb/sim/CVS/Entries | 3 -
usrp2/fpga/opencores/aemb/sim/CVS/Repository | 1 -
usrp2/fpga/opencores/aemb/sim/CVS/Root | 1 -
usrp2/fpga/opencores/aemb/sim/cversim | 22 -
usrp2/fpga/opencores/aemb/sim/iversim | 21 -
usrp2/fpga/opencores/aemb/sim/verilog/CVS/Entries | 3 -
.../fpga/opencores/aemb/sim/verilog/CVS/Repository | 1 -
usrp2/fpga/opencores/aemb/sim/verilog/CVS/Root | 1 -
usrp2/fpga/opencores/aemb/sim/verilog/aemb2.v | 242 -
usrp2/fpga/opencores/aemb/sim/verilog/edk32.v | 288 -
usrp2/fpga/opencores/aemb/sw/CVS/Entries | 2 -
usrp2/fpga/opencores/aemb/sw/CVS/Repository | 1 -
usrp2/fpga/opencores/aemb/sw/CVS/Root | 1 -
usrp2/fpga/opencores/aemb/sw/c/CVS/Entries | 3 -
usrp2/fpga/opencores/aemb/sw/c/CVS/Repository | 1 -
usrp2/fpga/opencores/aemb/sw/c/CVS/Root | 1 -
usrp2/fpga/opencores/aemb/sw/c/aeMB_testbench.c | 385 -
usrp2/fpga/opencores/aemb/sw/c/endian-test.c | 86 -
usrp2/fpga/opencores/aemb/sw/c/libaemb.h | 218 -
usrp2/fpga/opencores/aemb/sw/gccrom | 62 -
usrp2/fpga/opencores/i2c/CVS/Entries | 8 -
usrp2/fpga/opencores/i2c/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/CVS/Root | 1 -
usrp2/fpga/opencores/i2c/bench/CVS/Entries | 1 -
usrp2/fpga/opencores/i2c/bench/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/bench/CVS/Root | 1 -
usrp2/fpga/opencores/i2c/bench/verilog/CVS/Entries | 5 -
.../opencores/i2c/bench/verilog/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/bench/verilog/CVS/Root | 1 -
.../opencores/i2c/bench/verilog/i2c_slave_model.v | 360 -
.../opencores/i2c/bench/verilog/spi_slave_model.v | 128 -
.../opencores/i2c/bench/verilog/tst_bench_top.v | 467 -
.../opencores/i2c/bench/verilog/wb_master_model.v | 205 -
usrp2/fpga/opencores/i2c/doc/CVS/Entries | 2 -
usrp2/fpga/opencores/i2c/doc/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/doc/CVS/Root | 1 -
usrp2/fpga/opencores/i2c/doc/i2c_specs.pdf | Bin 211471 -> 0 bytes
usrp2/fpga/opencores/i2c/doc/src/CVS/Entries | 2 -
usrp2/fpga/opencores/i2c/doc/src/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/doc/src/CVS/Root | 1 -
usrp2/fpga/opencores/i2c/doc/src/I2C_specs.doc | Bin 464896 -> 0 bytes
usrp2/fpga/opencores/i2c/documentation/CVS/Entries | 1 -
.../opencores/i2c/documentation/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/documentation/CVS/Root | 1 -
usrp2/fpga/opencores/i2c/rtl/CVS/Entries | 2 -
usrp2/fpga/opencores/i2c/rtl/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/rtl/CVS/Root | 1 -
usrp2/fpga/opencores/i2c/rtl/verilog/CVS/Entries | 6 -
.../fpga/opencores/i2c/rtl/verilog/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/rtl/verilog/CVS/Root | 1 -
.../i2c/rtl/verilog/i2c_master_bit_ctrl.v | 538 -
.../i2c/rtl/verilog/i2c_master_byte_ctrl.v | 344 -
.../opencores/i2c/rtl/verilog/i2c_master_defines.v | 64 -
.../opencores/i2c/rtl/verilog/i2c_master_top.v | 301 -
usrp2/fpga/opencores/i2c/rtl/verilog/timescale.v | 2 -
usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Entries | 7 -
usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Root | 1 -
usrp2/fpga/opencores/i2c/rtl/vhdl/I2C.VHD | 620 -
.../opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd | 495 -
.../i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd | 370 -
.../fpga/opencores/i2c/rtl/vhdl/i2c_master_top.vhd | 359 -
usrp2/fpga/opencores/i2c/rtl/vhdl/readme | 25 -
usrp2/fpga/opencores/i2c/rtl/vhdl/tst_ds1621.vhd | 283 -
usrp2/fpga/opencores/i2c/sim/CVS/Entries | 1 -
usrp2/fpga/opencores/i2c/sim/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/sim/CVS/Root | 1 -
.../fpga/opencores/i2c/sim/i2c_verilog/CVS/Entries | 1 -
.../opencores/i2c/sim/i2c_verilog/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Root | 1 -
.../opencores/i2c/sim/i2c_verilog/run/CVS/Entries | 6 -
.../i2c/sim/i2c_verilog/run/CVS/Repository | 1 -
.../opencores/i2c/sim/i2c_verilog/run/CVS/Root | 1 -
.../i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries | 1 -
.../sim/i2c_verilog/run/INCA_libs/CVS/Repository | 1 -
.../i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root | 1 -
.../opencores/i2c/sim/i2c_verilog/run/bench.vcd |1496812
--------------------
.../i2c/sim/i2c_verilog/run/ncverilog.key | 1 -
.../i2c/sim/i2c_verilog/run/ncverilog.log | 118 -
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/run | 25 -
.../i2c/sim/i2c_verilog/run/waves/CVS/Entries | 1 -
.../i2c/sim/i2c_verilog/run/waves/CVS/Repository | 1 -
.../i2c/sim/i2c_verilog/run/waves/CVS/Root | 1 -
usrp2/fpga/opencores/i2c/software/CVS/Entries | 2 -
usrp2/fpga/opencores/i2c/software/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/software/CVS/Root | 1 -
.../opencores/i2c/software/drivers/CVS/Entries | 1 -
.../opencores/i2c/software/drivers/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/software/drivers/CVS/Root | 1 -
.../opencores/i2c/software/include/CVS/Entries | 2 -
.../opencores/i2c/software/include/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/software/include/CVS/Root | 1 -
.../opencores/i2c/software/include/oc_i2c_master.h | 102 -
usrp2/fpga/opencores/i2c/verilog/CVS/Entries | 1 -
usrp2/fpga/opencores/i2c/verilog/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/verilog/CVS/Root | 1 -
usrp2/fpga/opencores/i2c/vhdl/CVS/Entries | 1 -
usrp2/fpga/opencores/i2c/vhdl/CVS/Repository | 1 -
usrp2/fpga/opencores/i2c/vhdl/CVS/Root | 1 -
usrp2/fpga/opencores/simple_gpio/CVS/Entries | 1 -
usrp2/fpga/opencores/simple_gpio/CVS/Repository | 1 -
usrp2/fpga/opencores/simple_gpio/CVS/Root | 1 -
usrp2/fpga/opencores/simple_gpio/rtl/CVS/Entries | 2 -
.../fpga/opencores/simple_gpio/rtl/CVS/Repository | 1 -
usrp2/fpga/opencores/simple_gpio/rtl/CVS/Root | 1 -
usrp2/fpga/opencores/simple_gpio/rtl/simple_gpio.v | 193 -
usrp2/fpga/opencores/simple_pic/CVS/Entries | 1 -
usrp2/fpga/opencores/simple_pic/CVS/Repository | 1 -
usrp2/fpga/opencores/simple_pic/CVS/Root | 1 -
usrp2/fpga/opencores/simple_pic/rtl/CVS/Entries | 2 -
usrp2/fpga/opencores/simple_pic/rtl/CVS/Repository | 1 -
usrp2/fpga/opencores/simple_pic/rtl/CVS/Root | 1 -
usrp2/fpga/opencores/simple_pic/rtl/simple_pic.v | 228 -
usrp2/fpga/opencores/spi/CVS/Entries | 4 -
usrp2/fpga/opencores/spi/CVS/Repository | 1 -
usrp2/fpga/opencores/spi/CVS/Root | 1 -
usrp2/fpga/opencores/spi/bench/CVS/Entries | 1 -
usrp2/fpga/opencores/spi/bench/CVS/Repository | 1 -
usrp2/fpga/opencores/spi/bench/CVS/Root | 1 -
usrp2/fpga/opencores/spi/bench/verilog/CVS/Entries | 4 -
.../opencores/spi/bench/verilog/CVS/Repository | 1 -
usrp2/fpga/opencores/spi/bench/verilog/CVS/Root | 1 -
.../opencores/spi/bench/verilog/spi_slave_model.v | 73 -
.../fpga/opencores/spi/bench/verilog/tb_spi_top.v | 339 -
.../opencores/spi/bench/verilog/wb_master_model.v | 176 -
usrp2/fpga/opencores/spi/doc/CVS/Entries | 2 -
usrp2/fpga/opencores/spi/doc/CVS/Repository | 1 -
usrp2/fpga/opencores/spi/doc/CVS/Root | 1 -
usrp2/fpga/opencores/spi/doc/spi.pdf | Bin 78741 -> 0 bytes
usrp2/fpga/opencores/spi/doc/src/CVS/Entries | 2 -
usrp2/fpga/opencores/spi/doc/src/CVS/Repository | 1 -
usrp2/fpga/opencores/spi/doc/src/CVS/Root | 1 -
usrp2/fpga/opencores/spi/doc/src/spi.doc | Bin 231936 -> 0 bytes
usrp2/fpga/opencores/spi/rtl/CVS/Entries | 1 -
usrp2/fpga/opencores/spi/rtl/CVS/Repository | 1 -
usrp2/fpga/opencores/spi/rtl/CVS/Root | 1 -
usrp2/fpga/opencores/spi/rtl/verilog/CVS/Entries | 6 -
.../fpga/opencores/spi/rtl/verilog/CVS/Repository | 1 -
usrp2/fpga/opencores/spi/rtl/verilog/CVS/Root | 1 -
usrp2/fpga/opencores/spi/rtl/verilog/spi_clgen.v | 108 -
usrp2/fpga/opencores/spi/rtl/verilog/spi_defines.v | 159 -
usrp2/fpga/opencores/spi/rtl/verilog/spi_shift.v | 238 -
usrp2/fpga/opencores/spi/rtl/verilog/spi_top.v | 287 -
usrp2/fpga/opencores/spi/rtl/verilog/timescale.v | 2 -
usrp2/fpga/opencores/spi/sim/CVS/Entries | 2 -
usrp2/fpga/opencores/spi/sim/CVS/Repository | 1 -
usrp2/fpga/opencores/spi/sim/CVS/Root | 1 -
usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Entries | 1 -
.../fpga/opencores/spi/sim/rtl_sim/CVS/Repository | 1 -
usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Root | 1 -
.../fpga/opencores/spi/sim/rtl_sim/run/CVS/Entries | 4 -
.../opencores/spi/sim/rtl_sim/run/CVS/Repository | 1 -
usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Root | 1 -
usrp2/fpga/opencores/spi/sim/rtl_sim/run/rtl.fl | 3 -
usrp2/fpga/opencores/spi/sim/rtl_sim/run/run_sim | 108 -
usrp2/fpga/opencores/spi/sim/rtl_sim/run/sim.fl | 3 -
usrp2/fpga/opencores/spi/sim/run/CVS/Entries | 1 -
usrp2/fpga/opencores/spi/sim/run/CVS/Repository | 1 -
usrp2/fpga/opencores/spi/sim/run/CVS/Root | 1 -
usrp2/fpga/opencores/spi_boot/COMPILE_LIST | 33 -
usrp2/fpga/opencores/spi_boot/COPYING | 340 -
usrp2/fpga/opencores/spi_boot/CVS/Entries | 9 -
usrp2/fpga/opencores/spi_boot/CVS/Repository | 1 -
usrp2/fpga/opencores/spi_boot/CVS/Root | 1 -
usrp2/fpga/opencores/spi_boot/KNOWN_BUGS | 4 -
usrp2/fpga/opencores/spi_boot/README | 170 -
usrp2/fpga/opencores/spi_boot/bench/CVS/Entries | 1 -
usrp2/fpga/opencores/spi_boot/bench/CVS/Repository | 1 -
usrp2/fpga/opencores/spi_boot/bench/CVS/Root | 1 -
.../fpga/opencores/spi_boot/bench/vhdl/CVS/Entries | 13 -
.../opencores/spi_boot/bench/vhdl/CVS/Repository | 1 -
usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Root | 1 -
.../fpga/opencores/spi_boot/bench/vhdl/card-c.vhd | 14 -
usrp2/fpga/opencores/spi_boot/bench/vhdl/card.vhd | 446 -
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb-c.vhd | 31 -
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb.vhd | 201 -
.../spi_boot/bench/vhdl/tb_elem-full-c.vhd | 23 -
.../spi_boot/bench/vhdl/tb_elem-minimal-c.vhd | 23 -
.../spi_boot/bench/vhdl/tb_elem-mmc-c.vhd | 23 -
.../opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd | 23 -
.../fpga/opencores/spi_boot/bench/vhdl/tb_elem.vhd | 376 -
.../opencores/spi_boot/bench/vhdl/tb_pack-p.vhd | 93 -
.../fpga/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd | 27 -
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_rl.vhd | 259 -
usrp2/fpga/opencores/spi_boot/doc/CVS/Entries | 3 -
usrp2/fpga/opencores/spi_boot/doc/CVS/Repository | 1 -
usrp2/fpga/opencores/spi_boot/doc/CVS/Root | 1 -
usrp2/fpga/opencores/spi_boot/doc/spi_boot.pdf | Bin 113923 -> 0 bytes
.../opencores/spi_boot/doc/spi_boot_schematic.pdf | Bin 87189 -> 0 bytes
usrp2/fpga/opencores/spi_boot/doc/src/CVS/Entries | 10 -
.../fpga/opencores/spi_boot/doc/src/CVS/Repository | 1 -
usrp2/fpga/opencores/spi_boot/doc/src/CVS/Root | 1 -
.../opencores/spi_boot/doc/src/architecture.eps | 512 -
.../opencores/spi_boot/doc/src/architecture.fig | 222 -
.../opencores/spi_boot/doc/src/initialization.eps | 303 -
.../opencores/spi_boot/doc/src/initialization.fig | 119 -
.../spi_boot/doc/src/memory_organization.eps | 421 -
.../spi_boot/doc/src/memory_organization.fig | 176 -
usrp2/fpga/opencores/spi_boot/doc/src/spi_boot.sxw | Bin 39665 -> 0 bytes
usrp2/fpga/opencores/spi_boot/doc/src/transfer.eps | 323 -
usrp2/fpga/opencores/spi_boot/doc/src/transfer.fig | 119 -
usrp2/fpga/opencores/spi_boot/rtl/CVS/Entries | 1 -
usrp2/fpga/opencores/spi_boot/rtl/CVS/Repository | 1 -
usrp2/fpga/opencores/spi_boot/rtl/CVS/Root | 1 -
usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Entries | 15 -
.../opencores/spi_boot/rtl/vhdl/CVS/Repository | 1 -
usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Root | 1 -
usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-e.vhd | 91 -
.../opencores/spi_boot/rtl/vhdl/chip-full-a.vhd | 164 -
.../opencores/spi_boot/rtl/vhdl/chip-full-c.vhd | 19 -
.../opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd | 164 -
.../opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd | 19 -
.../opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd | 164 -
.../opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd | 19 -
.../fpga/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd | 164 -
.../fpga/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd | 19 -
.../opencores/spi_boot/rtl/vhdl/sample/CVS/Entries | 3 -
.../spi_boot/rtl/vhdl/sample/CVS/Repository | 1 -
.../opencores/spi_boot/rtl/vhdl/sample/CVS/Root | 1 -
.../spi_boot/rtl/vhdl/sample/ram_loader-c.vhd | 10 -
.../spi_boot/rtl/vhdl/sample/ram_loader.vhd | 355 -
.../opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd | 27 -
.../fpga/opencores/spi_boot/rtl/vhdl/spi_boot.vhd | 979 -
.../spi_boot/rtl/vhdl/spi_boot_pack-p.vhd | 54 -
.../opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd | 14 -
.../opencores/spi_boot/rtl/vhdl/spi_counter.vhd | 118 -
usrp2/fpga/opencores/spi_boot/sim/CVS/Entries | 1 -
usrp2/fpga/opencores/spi_boot/sim/CVS/Repository | 1 -
usrp2/fpga/opencores/spi_boot/sim/CVS/Root | 1 -
.../opencores/spi_boot/sim/rtl_sim/CVS/Entries | 2 -
.../opencores/spi_boot/sim/rtl_sim/CVS/Repository | 1 -
usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Root | 1 -
usrp2/fpga/opencores/spi_boot/sim/rtl_sim/Makefile | 159 -
usrp2/fpga/opencores/spi_boot/sw/CVS/Entries | 1 -
usrp2/fpga/opencores/spi_boot/sw/CVS/Repository | 1 -
usrp2/fpga/opencores/spi_boot/sw/CVS/Root | 1 -
usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Entries | 2 -
.../fpga/opencores/spi_boot/sw/misc/CVS/Repository | 1 -
usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Root | 1 -
.../fpga/opencores/spi_boot/sw/misc/bit_reverse.c | 74 -
usrp2/fpga/opencores/wb_zbt/CVS/Entries | 2 -
usrp2/fpga/opencores/wb_zbt/CVS/Repository | 1 -
usrp2/fpga/opencores/wb_zbt/CVS/Root | 1 -
usrp2/fpga/opencores/wb_zbt/wb_zbt.v | 149 -
usrp2/fpga/sdr_lib/.gitignore | 3 -
usrp2/fpga/sdr_lib/HB.sav | 56 -
usrp2/fpga/sdr_lib/SMALL_HB.sav | 40 -
usrp2/fpga/sdr_lib/acc.v | 28 -
usrp2/fpga/sdr_lib/add2.v | 11 -
usrp2/fpga/sdr_lib/add2_and_round.v | 11 -
usrp2/fpga/sdr_lib/add2_and_round_reg.v | 16 -
usrp2/fpga/sdr_lib/add2_reg.v | 17 -
usrp2/fpga/sdr_lib/cic_dec_shifter.v | 106 -
usrp2/fpga/sdr_lib/cic_decim.v | 88 -
usrp2/fpga/sdr_lib/cic_int_shifter.v | 100 -
usrp2/fpga/sdr_lib/cic_interp.v | 87 -
usrp2/fpga/sdr_lib/cic_strober.v | 45 -
usrp2/fpga/sdr_lib/clip.v | 36 -
usrp2/fpga/sdr_lib/clip_and_round.v | 43 -
usrp2/fpga/sdr_lib/clip_and_round_reg.v | 40 -
usrp2/fpga/sdr_lib/clip_reg.v | 38 -
usrp2/fpga/sdr_lib/cordic.v | 109 -
usrp2/fpga/sdr_lib/cordic_stage.v | 60 -
usrp2/fpga/sdr_lib/cordic_z24.v | 126 -
usrp2/fpga/sdr_lib/ddc.v | 97 -
usrp2/fpga/sdr_lib/dsp_core_rx.v | 179 -
usrp2/fpga/sdr_lib/dsp_core_tx.v | 152 -
usrp2/fpga/sdr_lib/duc.v | 95 -
usrp2/fpga/sdr_lib/dummy_rx.v | 62 -
usrp2/fpga/sdr_lib/gen_cordic_consts.py | 10 -
usrp2/fpga/sdr_lib/halfband_ideal.v | 84 -
usrp2/fpga/sdr_lib/halfband_tb.v | 120 -
usrp2/fpga/sdr_lib/hb/acc.v | 22 -
usrp2/fpga/sdr_lib/hb/coeff_ram.v | 26 -
usrp2/fpga/sdr_lib/hb/coeff_rom.v | 19 -
usrp2/fpga/sdr_lib/hb/halfband_decim.v | 163 -
usrp2/fpga/sdr_lib/hb/halfband_interp.v | 121 -
usrp2/fpga/sdr_lib/hb/hbd_tb/HBD | 80 -
usrp2/fpga/sdr_lib/hb/hbd_tb/really_golden | 142 -
usrp2/fpga/sdr_lib/hb/hbd_tb/regression | 95 -
usrp2/fpga/sdr_lib/hb/hbd_tb/run_hbd | 4 -
usrp2/fpga/sdr_lib/hb/hbd_tb/test_hbd.v | 75 -
usrp2/fpga/sdr_lib/hb/mac.v | 58 -
usrp2/fpga/sdr_lib/hb/mult.v | 16 -
usrp2/fpga/sdr_lib/hb/ram16_2port.v | 22 -
usrp2/fpga/sdr_lib/hb/ram16_2sum.v | 27 -
usrp2/fpga/sdr_lib/hb/ram32_2sum.v | 22 -
usrp2/fpga/sdr_lib/hb_dec.v | 171 -
usrp2/fpga/sdr_lib/hb_dec_tb.v | 140 -
usrp2/fpga/sdr_lib/hb_interp.v | 157 -
usrp2/fpga/sdr_lib/hb_interp_tb.v | 132 -
usrp2/fpga/sdr_lib/hb_tb.v | 155 -
usrp2/fpga/sdr_lib/input.dat | 341 -
usrp2/fpga/sdr_lib/integrate.v | 38 -
usrp2/fpga/sdr_lib/med_hb_int.v | 95 -
usrp2/fpga/sdr_lib/output.dat | 130 -
usrp2/fpga/sdr_lib/round.v | 33 -
usrp2/fpga/sdr_lib/round_reg.v | 39 -
usrp2/fpga/sdr_lib/rssi.v | 30 -
usrp2/fpga/sdr_lib/rx_control.v | 180 -
usrp2/fpga/sdr_lib/rx_dcoffset.v | 43 -
usrp2/fpga/sdr_lib/rx_dcoffset_tb.v | 25 -
usrp2/fpga/sdr_lib/sign_extend.v | 35 -
usrp2/fpga/sdr_lib/small_hb_dec.v | 111 -
usrp2/fpga/sdr_lib/small_hb_dec_tb.v | 140 -
usrp2/fpga/sdr_lib/small_hb_int.v | 85 -
usrp2/fpga/sdr_lib/small_hb_int_tb.v | 132 -
usrp2/fpga/sdr_lib/tx_control.v | 168 -
usrp2/fpga/serdes/serdes.v | 63 -
usrp2/fpga/serdes/serdes_fc_rx.v | 62 -
usrp2/fpga/serdes/serdes_fc_tx.v | 24 -
usrp2/fpga/serdes/serdes_rx.v | 292 -
usrp2/fpga/serdes/serdes_tb.v | 328 -
usrp2/fpga/serdes/serdes_tx.v | 186 -
usrp2/fpga/simple_gemac/.gitignore | 4 -
usrp2/fpga/simple_gemac/address_filter.v | 35 -
usrp2/fpga/simple_gemac/crc.v | 66 -
usrp2/fpga/simple_gemac/delay_line.v | 21 -
usrp2/fpga/simple_gemac/eth_tasks.v | 156 -
usrp2/fpga/simple_gemac/eth_tasks_f36.v | 92 -
usrp2/fpga/simple_gemac/flow_ctrl_rx.v | 61 -
usrp2/fpga/simple_gemac/flow_ctrl_tx.v | 39 -
usrp2/fpga/simple_gemac/ll8_to_txmac.v | 43 -
usrp2/fpga/simple_gemac/miim/eth_clockgen.v | 141 -
usrp2/fpga/simple_gemac/miim/eth_miim.v | 470 -
usrp2/fpga/simple_gemac/miim/eth_outputcontrol.v | 158 -
usrp2/fpga/simple_gemac/miim/eth_shiftreg.v | 159 -
usrp2/fpga/simple_gemac/rxmac_to_ll8.v | 54 -
usrp2/fpga/simple_gemac/simple_gemac.v | 61 -
usrp2/fpga/simple_gemac/simple_gemac_rx.v | 174 -
usrp2/fpga/simple_gemac/simple_gemac_tb.v | 200 -
usrp2/fpga/simple_gemac/simple_gemac_tx.v | 254 -
usrp2/fpga/simple_gemac/simple_gemac_wb.v | 161 -
usrp2/fpga/simple_gemac/simple_gemac_wrapper.build | 1 -
usrp2/fpga/simple_gemac/simple_gemac_wrapper.v | 165 -
.../simple_gemac/simple_gemac_wrapper_f36_tb.v | 243 -
usrp2/fpga/simple_gemac/simple_gemac_wrapper_tb.v | 209 -
usrp2/fpga/simple_gemac/test_packet.mem | 66 -
usrp2/fpga/testbench/.gitignore | 5 -
usrp2/fpga/testbench/BOOTSTRAP.sav | 82 -
usrp2/fpga/testbench/Makefile | 10 -
usrp2/fpga/testbench/PAUSE.sav | 62 -
usrp2/fpga/testbench/README | 5 -
usrp2/fpga/testbench/SERDES.sav | 35 -
usrp2/fpga/testbench/U2_SIM.sav | 95 -
usrp2/fpga/testbench/cmdfile | 27 -
usrp2/fpga/timing/.gitignore | 2 -
usrp2/fpga/timing/time_64bit.v | 63 -
usrp2/fpga/timing/time_receiver.v | 94 -
usrp2/fpga/timing/time_sender.v | 110 -
usrp2/fpga/timing/time_sync.v | 146 -
usrp2/fpga/timing/time_transfer_tb.v | 50 -
usrp2/fpga/timing/timer.v | 40 -
usrp2/fpga/top/.gitignore | 1 -
usrp2/fpga/top/eth_test/.gitignore | 43 -
usrp2/fpga/top/eth_test/eth_sim_top.v | 437 -
usrp2/fpga/top/eth_test/eth_tb.v | 257 -
usrp2/fpga/top/single_u2_sim/single_u2_sim.v | 324 -
usrp2/fpga/top/tcl/ise_helper.tcl | 89 -
usrp2/fpga/top/u2_core/.gitignore | 44 -
usrp2/fpga/top/u2_core/u2_core.v | 761 -
usrp2/fpga/top/u2_rev1/.gitignore | 52 -
usrp2/fpga/top/u2_rev1/Makefile | 129 -
usrp2/fpga/top/u2_rev1/u2_fpga.ise | Bin 477678 -> 0 bytes
usrp2/fpga/top/u2_rev1/u2_fpga.ucf | 341 -
usrp2/fpga/top/u2_rev1/u2_fpga_top.prj | 102 -
usrp2/fpga/top/u2_rev1/u2_fpga_top.v | 393 -
usrp2/fpga/top/u2_rev2/.gitignore | 57 -
usrp2/fpga/top/u2_rev2/Makefile | 248 -
usrp2/fpga/top/u2_rev2/u2_rev2.ucf | 337 -
usrp2/fpga/top/u2_rev2/u2_rev2.v | 417 -
usrp2/fpga/top/u2_rev3/.gitignore | 57 -
usrp2/fpga/top/u2_rev3/Makefile | 246 -
usrp2/fpga/top/u2_rev3/u2_rev3.ucf | 333 -
usrp2/fpga/top/u2_rev3/u2_rev3.v | 432 -
usrp2/fpga/top/u2_rev3_2rx_iad/Makefile | 254 -
usrp2/fpga/top/u2_rev3_2rx_iad/README | 32 -
usrp2/fpga/top/u2_rev3_2rx_iad/cmdfile | 4 -
usrp2/fpga/top/u2_rev3_2rx_iad/dsp_core_rx.v | 212 -
usrp2/fpga/top/u2_rev3_2rx_iad/dsp_core_tb.sav | 106 -
usrp2/fpga/top/u2_rev3_2rx_iad/dsp_core_tb.v | 233 -
usrp2/fpga/top/u2_rev3_2rx_iad/impulse.v | 68 -
usrp2/fpga/top/u2_rev3_2rx_iad/u2_core.v | 789 -
usrp2/fpga/top/u2_rev3_2rx_iad/wave.sh | 3 -
usrp2/fpga/top/u2_rev3_iad/.gitignore | 4 -
usrp2/fpga/top/u2_rev3_iad/Makefile | 254 -
usrp2/fpga/top/u2_rev3_iad/cmdfile | 4 -
usrp2/fpga/top/u2_rev3_iad/dsp_core_rx.v | 158 -
usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.sav | 61 -
usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.v | 196 -
usrp2/fpga/top/u2_rev3_iad/impulse.v | 63 -
usrp2/fpga/top/u2_rev3_iad/wave.sh | 3 -
usrp2/fpga/top/u2plus/u2plus.ucf | 354 -
usrp2/fpga/top/u2plus/u2plus.v | 377 -
usrp2/host/include/usrp2/usrp2.h | 10 +
usrp2/host/lib/usrp2.cc | 10 +
usrp2/host/lib/usrp2_impl.cc | 42 +
usrp2/host/lib/usrp2_impl.h | 2 +
815 files changed, 237 insertions(+), 1584284 deletions(-)
delete mode 100644 usrp/fpga/Makefile.extra
create mode 100644 usrp/fpga/README
delete mode 100644 usrp/fpga/TODO
delete mode 100755 usrp/fpga/gen_makefile_extra.py
delete mode 100755 usrp/fpga/inband_lib/chan_fifo_reader.v
delete mode 100644 usrp/fpga/inband_lib/channel_demux.v
delete mode 100755 usrp/fpga/inband_lib/channel_ram.v
delete mode 100755 usrp/fpga/inband_lib/cmd_reader.v
delete mode 100755 usrp/fpga/inband_lib/packet_builder.v
delete mode 100755 usrp/fpga/inband_lib/register_io.v
delete mode 100755 usrp/fpga/inband_lib/rx_buffer_inband.v
delete mode 100755 usrp/fpga/inband_lib/tx_buffer_inband.v
delete mode 100644 usrp/fpga/inband_lib/tx_packer.v
delete mode 100755 usrp/fpga/inband_lib/usb_packet_fifo.v
delete mode 100644 usrp/fpga/megacells/.gitignore
delete mode 100755 usrp/fpga/megacells/accum32.bsf
delete mode 100755 usrp/fpga/megacells/accum32.cmp
delete mode 100755 usrp/fpga/megacells/accum32.inc
delete mode 100755 usrp/fpga/megacells/accum32.v
delete mode 100755 usrp/fpga/megacells/accum32_bb.v
delete mode 100755 usrp/fpga/megacells/accum32_inst.v
delete mode 100755 usrp/fpga/megacells/add32.bsf
delete mode 100755 usrp/fpga/megacells/add32.cmp
delete mode 100755 usrp/fpga/megacells/add32.inc
delete mode 100755 usrp/fpga/megacells/add32.v
delete mode 100755 usrp/fpga/megacells/add32_bb.v
delete mode 100755 usrp/fpga/megacells/add32_inst.v
delete mode 100755 usrp/fpga/megacells/addsub16.bsf
delete mode 100755 usrp/fpga/megacells/addsub16.cmp
delete mode 100755 usrp/fpga/megacells/addsub16.inc
delete mode 100755 usrp/fpga/megacells/addsub16.v
delete mode 100755 usrp/fpga/megacells/addsub16_bb.v
delete mode 100755 usrp/fpga/megacells/addsub16_inst.v
delete mode 100755 usrp/fpga/megacells/bustri.bsf
delete mode 100755 usrp/fpga/megacells/bustri.cmp
delete mode 100755 usrp/fpga/megacells/bustri.inc
delete mode 100755 usrp/fpga/megacells/bustri.v
delete mode 100755 usrp/fpga/megacells/bustri_bb.v
delete mode 100755 usrp/fpga/megacells/bustri_inst.v
delete mode 100644 usrp/fpga/megacells/clk_doubler.v
delete mode 100644 usrp/fpga/megacells/clk_doubler_bb.v
delete mode 100644 usrp/fpga/megacells/dspclkpll.v
delete mode 100644 usrp/fpga/megacells/dspclkpll_bb.v
delete mode 100755 usrp/fpga/megacells/fifo_1kx16.bsf
delete mode 100755 usrp/fpga/megacells/fifo_1kx16.cmp
delete mode 100755 usrp/fpga/megacells/fifo_1kx16.inc
delete mode 100755 usrp/fpga/megacells/fifo_1kx16.v
delete mode 100755 usrp/fpga/megacells/fifo_1kx16_bb.v
delete mode 100755 usrp/fpga/megacells/fifo_1kx16_inst.v
delete mode 100644 usrp/fpga/megacells/fifo_2k.v
delete mode 100644 usrp/fpga/megacells/fifo_2k_bb.v
delete mode 100644 usrp/fpga/megacells/fifo_4k.v
delete mode 100755 usrp/fpga/megacells/fifo_4k_18.v
delete mode 100644 usrp/fpga/megacells/fifo_4k_bb.v
delete mode 100755 usrp/fpga/megacells/fifo_4kx16_dc.bsf
delete mode 100755 usrp/fpga/megacells/fifo_4kx16_dc.cmp
delete mode 100755 usrp/fpga/megacells/fifo_4kx16_dc.inc
delete mode 100755 usrp/fpga/megacells/fifo_4kx16_dc.v
delete mode 100755 usrp/fpga/megacells/fifo_4kx16_dc_bb.v
delete mode 100755 usrp/fpga/megacells/fifo_4kx16_dc_inst.v
delete mode 100755 usrp/fpga/megacells/mylpm_addsub.bsf
delete mode 100755 usrp/fpga/megacells/mylpm_addsub.cmp
delete mode 100755 usrp/fpga/megacells/mylpm_addsub.inc
delete mode 100755 usrp/fpga/megacells/mylpm_addsub.v
delete mode 100755 usrp/fpga/megacells/mylpm_addsub_bb.v
delete mode 100755 usrp/fpga/megacells/mylpm_addsub_inst.v
delete mode 100644 usrp/fpga/megacells/pll.v
delete mode 100644 usrp/fpga/megacells/pll_bb.v
delete mode 100644 usrp/fpga/megacells/pll_inst.v
delete mode 100755 usrp/fpga/megacells/sub32.bsf
delete mode 100755 usrp/fpga/megacells/sub32.cmp
delete mode 100755 usrp/fpga/megacells/sub32.inc
delete mode 100755 usrp/fpga/megacells/sub32.v
delete mode 100755 usrp/fpga/megacells/sub32_bb.v
delete mode 100755 usrp/fpga/megacells/sub32_inst.v
delete mode 100644 usrp/fpga/models/bustri.v
delete mode 100644 usrp/fpga/models/fifo.v
delete mode 100644 usrp/fpga/models/fifo_1c_1k.v
delete mode 100644 usrp/fpga/models/fifo_1c_2k.v
delete mode 100644 usrp/fpga/models/fifo_1c_4k.v
delete mode 100644 usrp/fpga/models/fifo_1k.v
delete mode 100644 usrp/fpga/models/fifo_2k.v
delete mode 100644 usrp/fpga/models/fifo_4k.v
delete mode 100644 usrp/fpga/models/fifo_4k_18.v
delete mode 100644 usrp/fpga/models/pll.v
delete mode 100644 usrp/fpga/models/ssram.v
delete mode 100644 usrp/fpga/sdr_lib/.gitignore
delete mode 100644 usrp/fpga/sdr_lib/adc_interface.v
delete mode 100644 usrp/fpga/sdr_lib/atr_delay.v
delete mode 100644 usrp/fpga/sdr_lib/bidir_reg.v
delete mode 100644 usrp/fpga/sdr_lib/cic_dec_shifter.v
delete mode 100755 usrp/fpga/sdr_lib/cic_decim.v
delete mode 100644 usrp/fpga/sdr_lib/cic_int_shifter.v
delete mode 100755 usrp/fpga/sdr_lib/cic_interp.v
delete mode 100755 usrp/fpga/sdr_lib/clk_divider.v
delete mode 100755 usrp/fpga/sdr_lib/cordic.v
delete mode 100755 usrp/fpga/sdr_lib/cordic_stage.v
delete mode 100755 usrp/fpga/sdr_lib/ddc.v
delete mode 100644 usrp/fpga/sdr_lib/dpram.v
delete mode 100755 usrp/fpga/sdr_lib/duc.v
delete mode 100644 usrp/fpga/sdr_lib/ext_fifo.v
delete mode 100755 usrp/fpga/sdr_lib/gen_cordic_consts.py
delete mode 100644 usrp/fpga/sdr_lib/gen_sync.v
delete mode 100644 usrp/fpga/sdr_lib/hb/acc.v
delete mode 100644 usrp/fpga/sdr_lib/hb/coeff_rom.v
delete mode 100644 usrp/fpga/sdr_lib/hb/halfband_decim.v
delete mode 100644 usrp/fpga/sdr_lib/hb/halfband_interp.v
delete mode 100644 usrp/fpga/sdr_lib/hb/hbd_tb/HBD
delete mode 100644 usrp/fpga/sdr_lib/hb/hbd_tb/really_golden
delete mode 100644 usrp/fpga/sdr_lib/hb/hbd_tb/regression
delete mode 100755 usrp/fpga/sdr_lib/hb/hbd_tb/run_hbd
delete mode 100644 usrp/fpga/sdr_lib/hb/hbd_tb/test_hbd.v
delete mode 100644 usrp/fpga/sdr_lib/hb/mac.v
delete mode 100644 usrp/fpga/sdr_lib/hb/mult.v
delete mode 100644 usrp/fpga/sdr_lib/hb/ram16_2port.v
delete mode 100644 usrp/fpga/sdr_lib/hb/ram16_2sum.v
delete mode 100644 usrp/fpga/sdr_lib/hb/ram32_2sum.v
delete mode 100644 usrp/fpga/sdr_lib/io_pins.v
delete mode 100644 usrp/fpga/sdr_lib/master_control.v
delete mode 100644 usrp/fpga/sdr_lib/master_control_multi.v
delete mode 100755 usrp/fpga/sdr_lib/phase_acc.v
delete mode 100644 usrp/fpga/sdr_lib/ram.v
delete mode 100644 usrp/fpga/sdr_lib/ram16.v
delete mode 100644 usrp/fpga/sdr_lib/ram32.v
delete mode 100644 usrp/fpga/sdr_lib/ram64.v
delete mode 100644 usrp/fpga/sdr_lib/rssi.v
delete mode 100644 usrp/fpga/sdr_lib/rx_buffer.v
delete mode 100644 usrp/fpga/sdr_lib/rx_chain.v
delete mode 100644 usrp/fpga/sdr_lib/rx_chain_dual.v
delete mode 100644 usrp/fpga/sdr_lib/rx_dcoffset.v
delete mode 100644 usrp/fpga/sdr_lib/serial_io.v
delete mode 100644 usrp/fpga/sdr_lib/setting_reg.v
delete mode 100644 usrp/fpga/sdr_lib/setting_reg_masked.v
delete mode 100644 usrp/fpga/sdr_lib/sign_extend.v
delete mode 100644 usrp/fpga/sdr_lib/strobe_gen.v
delete mode 100644 usrp/fpga/sdr_lib/tx_buffer.v
delete mode 100644 usrp/fpga/sdr_lib/tx_chain.v
delete mode 100644 usrp/fpga/sdr_lib/tx_chain_hb.v
delete mode 100644 usrp/fpga/tb/.gitignore
delete mode 100644 usrp/fpga/tb/cbus_tb.v
delete mode 100644 usrp/fpga/tb/cordic_tb.v
delete mode 100644 usrp/fpga/tb/decim_tb.v
delete mode 100755 usrp/fpga/tb/fullchip_tb.v
delete mode 100755 usrp/fpga/tb/interp_tb.v
delete mode 100644 usrp/fpga/tb/justinterp_tb.v
delete mode 100755 usrp/fpga/tb/makesine.pl
delete mode 100755 usrp/fpga/tb/run_cordic
delete mode 100755 usrp/fpga/tb/run_fullchip
delete mode 100755 usrp/fpga/tb/usrp_tasks.v
delete mode 100644 usrp/fpga/toplevel/include/common_config_1rxhb_1tx.vh
delete mode 100644 usrp/fpga/toplevel/include/common_config_2rx_0tx.vh
delete mode 100644 usrp/fpga/toplevel/include/common_config_2rxhb_0tx.vh
delete mode 100644 usrp/fpga/toplevel/include/common_config_2rxhb_2tx.vh
delete mode 100644 usrp/fpga/toplevel/include/common_config_4rx_0tx.vh
delete mode 100644 usrp/fpga/toplevel/include/common_config_bottom.vh
delete mode 100644 usrp/fpga/toplevel/mrfm/.gitignore
delete mode 100644 usrp/fpga/toplevel/mrfm/biquad_2stage.v
delete mode 100644 usrp/fpga/toplevel/mrfm/biquad_6stage.v
delete mode 100644 usrp/fpga/toplevel/mrfm/mrfm.csf
delete mode 100644 usrp/fpga/toplevel/mrfm/mrfm.esf
delete mode 100644 usrp/fpga/toplevel/mrfm/mrfm.psf
delete mode 100644 usrp/fpga/toplevel/mrfm/mrfm.py
delete mode 100644 usrp/fpga/toplevel/mrfm/mrfm.qpf
delete mode 100644 usrp/fpga/toplevel/mrfm/mrfm.qsf
delete mode 100644 usrp/fpga/toplevel/mrfm/mrfm.v
delete mode 100644 usrp/fpga/toplevel/mrfm/mrfm.vh
delete mode 100644 usrp/fpga/toplevel/mrfm/mrfm_compensator.v
delete mode 100755 usrp/fpga/toplevel/mrfm/mrfm_fft.py
delete mode 100644 usrp/fpga/toplevel/mrfm/mrfm_proc.v
delete mode 100644 usrp/fpga/toplevel/mrfm/shifter.v
delete mode 100644 usrp/fpga/toplevel/sizetest/.gitignore
delete mode 100644 usrp/fpga/toplevel/sizetest/sizetest.csf
delete mode 100644 usrp/fpga/toplevel/sizetest/sizetest.psf
delete mode 100644 usrp/fpga/toplevel/sizetest/sizetest.quartus
delete mode 100644 usrp/fpga/toplevel/sizetest/sizetest.ssf
delete mode 100644 usrp/fpga/toplevel/sizetest/sizetest.v
delete mode 100644 usrp/fpga/toplevel/usrp_inband_usb/.gitignore
delete mode 100644 usrp/fpga/toplevel/usrp_inband_usb/config.vh
delete mode 100644 usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.csf
delete mode 100644 usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.esf
delete mode 100644 usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.psf
delete mode 100644 usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qpf
delete mode 100644 usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
delete mode 100644 usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
delete mode 100644 usrp/fpga/toplevel/usrp_multi/.gitignore
delete mode 100644 usrp/fpga/toplevel/usrp_multi/config.vh
delete mode 100644 usrp/fpga/toplevel/usrp_multi/usrp_multi.csf
delete mode 100644 usrp/fpga/toplevel/usrp_multi/usrp_multi.esf
delete mode 100644 usrp/fpga/toplevel/usrp_multi/usrp_multi.psf
delete mode 100644 usrp/fpga/toplevel/usrp_multi/usrp_multi.qpf
delete mode 100644 usrp/fpga/toplevel/usrp_multi/usrp_multi.qsf
delete mode 100644 usrp/fpga/toplevel/usrp_multi/usrp_multi.v
delete mode 100644 usrp/fpga/toplevel/usrp_std/.gitignore
delete mode 100644 usrp/fpga/toplevel/usrp_std/config.vh
delete mode 100644 usrp/fpga/toplevel/usrp_std/usrp_std.csf
delete mode 100644 usrp/fpga/toplevel/usrp_std/usrp_std.esf
delete mode 100644 usrp/fpga/toplevel/usrp_std/usrp_std.psf
delete mode 100644 usrp/fpga/toplevel/usrp_std/usrp_std.qpf
delete mode 100644 usrp/fpga/toplevel/usrp_std/usrp_std.qsf
delete mode 100644 usrp/fpga/toplevel/usrp_std/usrp_std.v
copy usrp2/firmware/lib/{db_init_wbx.c => db_init_xcvr.c} (97%)
delete mode 100644 usrp2/fpga/.gitignore
create mode 100644 usrp2/fpga/README
delete mode 100644 usrp2/fpga/boot_cpld/.gitignore
delete mode 100755 usrp2/fpga/boot_cpld/_impact.cmd
delete mode 100755 usrp2/fpga/boot_cpld/boot_cpld.ipf
delete mode 100755 usrp2/fpga/boot_cpld/boot_cpld.ise
delete mode 100755 usrp2/fpga/boot_cpld/boot_cpld.lfp
delete mode 100755 usrp2/fpga/boot_cpld/boot_cpld.ucf
delete mode 100755 usrp2/fpga/boot_cpld/boot_cpld.v
delete mode 100644 usrp2/fpga/control_lib/.gitignore
delete mode 100644 usrp2/fpga/control_lib/CRC16_D16.v
delete mode 100644 usrp2/fpga/control_lib/SYSCTRL.sav
delete mode 100644 usrp2/fpga/control_lib/WB_SIM.sav
delete mode 100644 usrp2/fpga/control_lib/atr_controller.v
delete mode 100644 usrp2/fpga/control_lib/bin2gray.v
delete mode 100644 usrp2/fpga/control_lib/bootrom.mem
delete mode 100644 usrp2/fpga/control_lib/clock_bootstrap_rom.v
delete mode 100644 usrp2/fpga/control_lib/clock_control.v
delete mode 100644 usrp2/fpga/control_lib/clock_control_tb.sav
delete mode 100644 usrp2/fpga/control_lib/clock_control_tb.v
delete mode 100644 usrp2/fpga/control_lib/cmdfile
delete mode 100644 usrp2/fpga/control_lib/dcache.v
delete mode 100644 usrp2/fpga/control_lib/decoder_3_8.v
delete mode 100644 usrp2/fpga/control_lib/dpram32.v
delete mode 100644 usrp2/fpga/control_lib/fifo_tb.v
delete mode 100644 usrp2/fpga/control_lib/gray2bin.v
delete mode 100644 usrp2/fpga/control_lib/gray_send.v
delete mode 100644 usrp2/fpga/control_lib/icache.v
delete mode 100644 usrp2/fpga/control_lib/longfifo.v
delete mode 100644 usrp2/fpga/control_lib/medfifo.v
delete mode 100644 usrp2/fpga/control_lib/mux4.v
delete mode 100644 usrp2/fpga/control_lib/mux8.v
delete mode 100644 usrp2/fpga/control_lib/mux_32_4.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/.gitignore
delete mode 100644 usrp2/fpga/control_lib/newfifo/buffer_int.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/buffer_int_tb.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/buffer_pool.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/buffer_pool_tb.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo19_to_fifo36.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo19_to_ll8.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo36_to_fifo18.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo36_to_fifo19.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo36_to_ll8.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo_2clock.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo_2clock_cascade.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo_cascade.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo_long.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo_new_tb.vcd
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo_short.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo_spec.txt
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo_tb.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/ll8_shortfifo.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/ll8_to_fifo19.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/ll8_to_fifo36.v
delete mode 100644 usrp2/fpga/control_lib/nsgpio.v
delete mode 100644 usrp2/fpga/control_lib/oneshot_2clk.v
delete mode 100644 usrp2/fpga/control_lib/pic.v
delete mode 100644 usrp2/fpga/control_lib/priority_enc.v
delete mode 100644 usrp2/fpga/control_lib/ram_2port.v
delete mode 100644 usrp2/fpga/control_lib/ram_harv_cache.v
delete mode 100644 usrp2/fpga/control_lib/ram_loader.v
delete mode 100644 usrp2/fpga/control_lib/ram_wb_harvard.v
delete mode 100644 usrp2/fpga/control_lib/reset_sync.v
delete mode 100644 usrp2/fpga/control_lib/sd_spi.v
delete mode 100644 usrp2/fpga/control_lib/sd_spi_tb.v
delete mode 100644 usrp2/fpga/control_lib/sd_spi_wb.v
delete mode 100644 usrp2/fpga/control_lib/setting_reg.v
delete mode 100644 usrp2/fpga/control_lib/settings_bus.v
delete mode 100644 usrp2/fpga/control_lib/shortfifo.v
delete mode 100644 usrp2/fpga/control_lib/simple_uart.v
delete mode 100644 usrp2/fpga/control_lib/simple_uart_rx.v
delete mode 100644 usrp2/fpga/control_lib/simple_uart_tx.v
delete mode 100644 usrp2/fpga/control_lib/spi.v
delete mode 100644 usrp2/fpga/control_lib/srl.v
delete mode 100644 usrp2/fpga/control_lib/ss_rcvr.v
delete mode 100644 usrp2/fpga/control_lib/system_control.v
delete mode 100644 usrp2/fpga/control_lib/system_control_tb.v
delete mode 100644 usrp2/fpga/control_lib/traffic_cop.v
delete mode 100644 usrp2/fpga/control_lib/wb_1master.v
delete mode 100644 usrp2/fpga/control_lib/wb_bridge_16_32.v
delete mode 100644 usrp2/fpga/control_lib/wb_bus_writer.v
delete mode 100644 usrp2/fpga/control_lib/wb_output_pins32.v
delete mode 100644 usrp2/fpga/control_lib/wb_ram_block.v
delete mode 100644 usrp2/fpga/control_lib/wb_ram_dist.v
delete mode 100644 usrp2/fpga/control_lib/wb_readback_mux.v
delete mode 100644 usrp2/fpga/control_lib/wb_regfile_2clock.v
delete mode 100644 usrp2/fpga/control_lib/wb_semaphore.v
delete mode 100644 usrp2/fpga/control_lib/wb_sim.v
delete mode 100644 usrp2/fpga/coregen/.gitignore
delete mode 100644 usrp2/fpga/coregen/coregen.cgp
delete mode 100644 usrp2/fpga/coregen/fifo_generator_release_notes.txt
delete mode 100644 usrp2/fpga/coregen/fifo_generator_ug175.pdf
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.ngc
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.v
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.veo
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.xco
delete mode 100644
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
delete mode 100644
usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_flist.txt
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_readme.txt
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.asy
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.ngc
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.sym
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.v
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.veo
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vhd
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.vho
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk.xco
delete mode 100644
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso
delete mode 100644
usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_flist.txt
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_readme.txt
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.asy
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.ngc
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.sym
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.v
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.veo
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.vhd
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.vho
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_512x36_2clk.xco
delete mode 100644
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso
delete mode 100644
usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_flist.txt
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_readme.txt
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.ngc
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.v
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.veo
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.xco
delete mode 100644
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso
delete mode 100644
usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_flist.txt
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_readme.txt
delete mode 100644 usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl
delete mode 100644 usrp2/fpga/extram/.gitignore
delete mode 100644 usrp2/fpga/extram/extram_interface.v
delete mode 100644 usrp2/fpga/extram/extram_wb.v
delete mode 100644 usrp2/fpga/extram/wb_zbt16_b.v
delete mode 100644 usrp2/fpga/models/BUFG.v
delete mode 100644 usrp2/fpga/models/CY7C1356C/cy1356.inp
delete mode 100644 usrp2/fpga/models/CY7C1356C/cy1356.v
delete mode 100644 usrp2/fpga/models/CY7C1356C/readme.txt
delete mode 100644 usrp2/fpga/models/CY7C1356C/testbench.v
delete mode 100644 usrp2/fpga/models/FIFO_GENERATOR_V4_3.v
delete mode 100644 usrp2/fpga/models/M24LC024B.v
delete mode 100644 usrp2/fpga/models/M24LC02B.v
delete mode 100644 usrp2/fpga/models/MULT18X18S.v
delete mode 100644 usrp2/fpga/models/RAMB16_S36_S36.v
delete mode 100644 usrp2/fpga/models/SRL16E.v
delete mode 100644 usrp2/fpga/models/SRLC16E.v
delete mode 100644 usrp2/fpga/models/adc_model.v
delete mode 100644 usrp2/fpga/models/cpld_model.v
delete mode 100644 usrp2/fpga/models/math_real.v
delete mode 100644 usrp2/fpga/models/miim_model.v
delete mode 100644 usrp2/fpga/models/phy_sim.v
delete mode 100644 usrp2/fpga/models/serdes_model.v
delete mode 100644 usrp2/fpga/models/uart_rx.v
delete mode 100644 usrp2/fpga/models/xlnx_glbl.v
delete mode 100644 usrp2/fpga/opencores/8b10b/.gitignore
delete mode 100644 usrp2/fpga/opencores/8b10b/8b10b_a.mem
delete mode 100644 usrp2/fpga/opencores/8b10b/README
delete mode 100644 usrp2/fpga/opencores/8b10b/decode_8b10b.v
delete mode 100644 usrp2/fpga/opencores/8b10b/encode_8b10b.v
delete mode 100644 usrp2/fpga/opencores/8b10b/validate_8b10b.v
delete mode 100644 usrp2/fpga/opencores/README
delete mode 100644 usrp2/fpga/opencores/aemb/CVS/.gitignore
delete mode 100644 usrp2/fpga/opencores/aemb/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/aemb/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/aemb/CVS/Root
delete mode 100644 usrp2/fpga/opencores/aemb/CVS/Template
delete mode 100644 usrp2/fpga/opencores/aemb/doc/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/aemb/doc/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/aemb/doc/CVS/Root
delete mode 100644 usrp2/fpga/opencores/aemb/doc/CVS/Template
delete mode 100644 usrp2/fpga/opencores/aemb/doc/aeMB_datasheet.pdf
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/CVS/Root
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/CVS/Template
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/verilog/.gitignore
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Root
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Template
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_bpcu.v
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_core.v
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_core_BE.v
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ctrl.v
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_edk32.v
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_ibuf.v
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_regf.v
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_sim.v
delete mode 100644 usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_xecu.v
delete mode 100644 usrp2/fpga/opencores/aemb/sim/.gitignore
delete mode 100644 usrp2/fpga/opencores/aemb/sim/CODE_DEBUG.sav
delete mode 100644 usrp2/fpga/opencores/aemb/sim/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/aemb/sim/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/aemb/sim/CVS/Root
delete mode 100644 usrp2/fpga/opencores/aemb/sim/CVS/Template
delete mode 100755 usrp2/fpga/opencores/aemb/sim/cversim
delete mode 100755 usrp2/fpga/opencores/aemb/sim/iversim
delete mode 100644 usrp2/fpga/opencores/aemb/sim/verilog/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/aemb/sim/verilog/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/aemb/sim/verilog/CVS/Root
delete mode 100644 usrp2/fpga/opencores/aemb/sim/verilog/CVS/Template
delete mode 100644 usrp2/fpga/opencores/aemb/sim/verilog/aemb2.v
delete mode 100644 usrp2/fpga/opencores/aemb/sim/verilog/edk32.v
delete mode 100644 usrp2/fpga/opencores/aemb/sw/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/aemb/sw/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/aemb/sw/CVS/Root
delete mode 100644 usrp2/fpga/opencores/aemb/sw/CVS/Template
delete mode 100644 usrp2/fpga/opencores/aemb/sw/c/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/aemb/sw/c/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/aemb/sw/c/CVS/Root
delete mode 100644 usrp2/fpga/opencores/aemb/sw/c/CVS/Template
delete mode 100644 usrp2/fpga/opencores/aemb/sw/c/aeMB_testbench.c
delete mode 100644 usrp2/fpga/opencores/aemb/sw/c/endian-test.c
delete mode 100644 usrp2/fpga/opencores/aemb/sw/c/libaemb.h
delete mode 100755 usrp2/fpga/opencores/aemb/sw/gccrom
delete mode 100644 usrp2/fpga/opencores/i2c/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/bench/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/bench/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/bench/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/bench/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/bench/verilog/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/bench/verilog/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/bench/verilog/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/bench/verilog/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/bench/verilog/i2c_slave_model.v
delete mode 100644 usrp2/fpga/opencores/i2c/bench/verilog/spi_slave_model.v
delete mode 100644 usrp2/fpga/opencores/i2c/bench/verilog/tst_bench_top.v
delete mode 100644 usrp2/fpga/opencores/i2c/bench/verilog/wb_master_model.v
delete mode 100644 usrp2/fpga/opencores/i2c/doc/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/doc/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/doc/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/doc/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/doc/i2c_specs.pdf
delete mode 100644 usrp2/fpga/opencores/i2c/doc/src/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/doc/src/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/doc/src/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/doc/src/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/doc/src/I2C_specs.doc
delete mode 100644 usrp2/fpga/opencores/i2c/documentation/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/documentation/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/documentation/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/documentation/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/verilog/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/verilog/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/verilog/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/verilog/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_defines.v
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/verilog/i2c_master_top.v
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/verilog/timescale.v
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/vhdl/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/vhdl/I2C.VHD
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/vhdl/i2c_master_top.vhd
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/vhdl/readme
delete mode 100644 usrp2/fpga/opencores/i2c/rtl/vhdl/tst_ds1621.vhd
delete mode 100644 usrp2/fpga/opencores/i2c/sim/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/sim/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/sim/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/sim/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/sim/i2c_verilog/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/CVS/Template
delete mode 100644
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries
delete mode 100644
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository
delete mode 100644
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root
delete mode 100644
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/bench.vcd
delete mode 100644 usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/ncverilog.key
delete mode 100644 usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/ncverilog.log
delete mode 100755 usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/run
delete mode 100644
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries
delete mode 100644
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root
delete mode 100644
usrp2/fpga/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/software/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/software/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/software/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/software/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/software/drivers/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/software/drivers/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/software/drivers/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/software/drivers/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/software/include/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/software/include/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/software/include/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/software/include/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/software/include/oc_i2c_master.h
delete mode 100644 usrp2/fpga/opencores/i2c/verilog/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/verilog/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/verilog/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/verilog/CVS/Template
delete mode 100644 usrp2/fpga/opencores/i2c/vhdl/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/i2c/vhdl/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/i2c/vhdl/CVS/Root
delete mode 100644 usrp2/fpga/opencores/i2c/vhdl/CVS/Template
delete mode 100644 usrp2/fpga/opencores/simple_gpio/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/simple_gpio/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/simple_gpio/CVS/Root
delete mode 100644 usrp2/fpga/opencores/simple_gpio/CVS/Template
delete mode 100644 usrp2/fpga/opencores/simple_gpio/rtl/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/simple_gpio/rtl/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/simple_gpio/rtl/CVS/Root
delete mode 100644 usrp2/fpga/opencores/simple_gpio/rtl/CVS/Template
delete mode 100644 usrp2/fpga/opencores/simple_gpio/rtl/simple_gpio.v
delete mode 100644 usrp2/fpga/opencores/simple_pic/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/simple_pic/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/simple_pic/CVS/Root
delete mode 100644 usrp2/fpga/opencores/simple_pic/CVS/Template
delete mode 100644 usrp2/fpga/opencores/simple_pic/rtl/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/simple_pic/rtl/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/simple_pic/rtl/CVS/Root
delete mode 100644 usrp2/fpga/opencores/simple_pic/rtl/CVS/Template
delete mode 100644 usrp2/fpga/opencores/simple_pic/rtl/simple_pic.v
delete mode 100644 usrp2/fpga/opencores/spi/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi/bench/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi/bench/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi/bench/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi/bench/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi/bench/verilog/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi/bench/verilog/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi/bench/verilog/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi/bench/verilog/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi/bench/verilog/spi_slave_model.v
delete mode 100644 usrp2/fpga/opencores/spi/bench/verilog/tb_spi_top.v
delete mode 100644 usrp2/fpga/opencores/spi/bench/verilog/wb_master_model.v
delete mode 100644 usrp2/fpga/opencores/spi/doc/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi/doc/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi/doc/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi/doc/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi/doc/spi.pdf
delete mode 100644 usrp2/fpga/opencores/spi/doc/src/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi/doc/src/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi/doc/src/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi/doc/src/CVS/Template
delete mode 100755 usrp2/fpga/opencores/spi/doc/src/spi.doc
delete mode 100644 usrp2/fpga/opencores/spi/rtl/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi/rtl/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi/rtl/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi/rtl/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi/rtl/verilog/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi/rtl/verilog/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi/rtl/verilog/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi/rtl/verilog/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi/rtl/verilog/spi_clgen.v
delete mode 100644 usrp2/fpga/opencores/spi/rtl/verilog/spi_defines.v
delete mode 100644 usrp2/fpga/opencores/spi/rtl/verilog/spi_shift.v
delete mode 100644 usrp2/fpga/opencores/spi/rtl/verilog/spi_top.v
delete mode 100644 usrp2/fpga/opencores/spi/rtl/verilog/timescale.v
delete mode 100644 usrp2/fpga/opencores/spi/sim/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi/sim/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi/sim/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi/sim/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi/sim/rtl_sim/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi/sim/rtl_sim/run/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi/sim/rtl_sim/run/rtl.fl
delete mode 100755 usrp2/fpga/opencores/spi/sim/rtl_sim/run/run_sim
delete mode 100644 usrp2/fpga/opencores/spi/sim/rtl_sim/run/sim.fl
delete mode 100644 usrp2/fpga/opencores/spi/sim/run/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi/sim/run/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi/sim/run/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi/sim/run/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi_boot/COMPILE_LIST
delete mode 100644 usrp2/fpga/opencores/spi_boot/COPYING
delete mode 100644 usrp2/fpga/opencores/spi_boot/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi_boot/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi_boot/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi_boot/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi_boot/KNOWN_BUGS
delete mode 100644 usrp2/fpga/opencores/spi_boot/README
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/vhdl/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/vhdl/card-c.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/vhdl/card.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/vhdl/tb-c.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/vhdl/tb.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd
delete mode 100644
usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_elem.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/bench/vhdl/tb_rl.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/spi_boot.pdf
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/spi_boot_schematic.pdf
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/src/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/src/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/src/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/src/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/src/architecture.eps
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/src/architecture.fig
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/src/initialization.eps
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/src/initialization.fig
delete mode 100644
usrp2/fpga/opencores/spi_boot/doc/src/memory_organization.eps
delete mode 100644
usrp2/fpga/opencores/spi_boot/doc/src/memory_organization.fig
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/src/spi_boot.sxw
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/src/transfer.eps
delete mode 100644 usrp2/fpga/opencores/spi_boot/doc/src/transfer.fig
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-e.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/CVS/Template
delete mode 100644
usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/rtl/vhdl/spi_counter.vhd
delete mode 100644 usrp2/fpga/opencores/spi_boot/sim/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi_boot/sim/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi_boot/sim/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi_boot/sim/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi_boot/sim/rtl_sim/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi_boot/sim/rtl_sim/Makefile
delete mode 100644 usrp2/fpga/opencores/spi_boot/sw/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi_boot/sw/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi_boot/sw/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi_boot/sw/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Root
delete mode 100644 usrp2/fpga/opencores/spi_boot/sw/misc/CVS/Template
delete mode 100644 usrp2/fpga/opencores/spi_boot/sw/misc/bit_reverse.c
delete mode 100644 usrp2/fpga/opencores/wb_zbt/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/wb_zbt/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/wb_zbt/CVS/Root
delete mode 100644 usrp2/fpga/opencores/wb_zbt/CVS/Template
delete mode 100644 usrp2/fpga/opencores/wb_zbt/wb_zbt.v
delete mode 100644 usrp2/fpga/sdr_lib/.gitignore
delete mode 100644 usrp2/fpga/sdr_lib/HB.sav
delete mode 100644 usrp2/fpga/sdr_lib/SMALL_HB.sav
delete mode 100644 usrp2/fpga/sdr_lib/acc.v
delete mode 100644 usrp2/fpga/sdr_lib/add2.v
delete mode 100644 usrp2/fpga/sdr_lib/add2_and_round.v
delete mode 100644 usrp2/fpga/sdr_lib/add2_and_round_reg.v
delete mode 100644 usrp2/fpga/sdr_lib/add2_reg.v
delete mode 100644 usrp2/fpga/sdr_lib/cic_dec_shifter.v
delete mode 100755 usrp2/fpga/sdr_lib/cic_decim.v
delete mode 100644 usrp2/fpga/sdr_lib/cic_int_shifter.v
delete mode 100755 usrp2/fpga/sdr_lib/cic_interp.v
delete mode 100644 usrp2/fpga/sdr_lib/cic_strober.v
delete mode 100644 usrp2/fpga/sdr_lib/clip.v
delete mode 100644 usrp2/fpga/sdr_lib/clip_and_round.v
delete mode 100644 usrp2/fpga/sdr_lib/clip_and_round_reg.v
delete mode 100644 usrp2/fpga/sdr_lib/clip_reg.v
delete mode 100755 usrp2/fpga/sdr_lib/cordic.v
delete mode 100755 usrp2/fpga/sdr_lib/cordic_stage.v
delete mode 100644 usrp2/fpga/sdr_lib/cordic_z24.v
delete mode 100755 usrp2/fpga/sdr_lib/ddc.v
delete mode 100644 usrp2/fpga/sdr_lib/dsp_core_rx.v
delete mode 100644 usrp2/fpga/sdr_lib/dsp_core_tx.v
delete mode 100755 usrp2/fpga/sdr_lib/duc.v
delete mode 100644 usrp2/fpga/sdr_lib/dummy_rx.v
delete mode 100755 usrp2/fpga/sdr_lib/gen_cordic_consts.py
delete mode 100644 usrp2/fpga/sdr_lib/halfband_ideal.v
delete mode 100644 usrp2/fpga/sdr_lib/halfband_tb.v
delete mode 100644 usrp2/fpga/sdr_lib/hb/acc.v
delete mode 100644 usrp2/fpga/sdr_lib/hb/coeff_ram.v
delete mode 100644 usrp2/fpga/sdr_lib/hb/coeff_rom.v
delete mode 100644 usrp2/fpga/sdr_lib/hb/halfband_decim.v
delete mode 100644 usrp2/fpga/sdr_lib/hb/halfband_interp.v
delete mode 100644 usrp2/fpga/sdr_lib/hb/hbd_tb/HBD
delete mode 100644 usrp2/fpga/sdr_lib/hb/hbd_tb/really_golden
delete mode 100644 usrp2/fpga/sdr_lib/hb/hbd_tb/regression
delete mode 100755 usrp2/fpga/sdr_lib/hb/hbd_tb/run_hbd
delete mode 100644 usrp2/fpga/sdr_lib/hb/hbd_tb/test_hbd.v
delete mode 100644 usrp2/fpga/sdr_lib/hb/mac.v
delete mode 100644 usrp2/fpga/sdr_lib/hb/mult.v
delete mode 100644 usrp2/fpga/sdr_lib/hb/ram16_2port.v
delete mode 100644 usrp2/fpga/sdr_lib/hb/ram16_2sum.v
delete mode 100644 usrp2/fpga/sdr_lib/hb/ram32_2sum.v
delete mode 100644 usrp2/fpga/sdr_lib/hb_dec.v
delete mode 100644 usrp2/fpga/sdr_lib/hb_dec_tb.v
delete mode 100644 usrp2/fpga/sdr_lib/hb_interp.v
delete mode 100644 usrp2/fpga/sdr_lib/hb_interp_tb.v
delete mode 100644 usrp2/fpga/sdr_lib/hb_tb.v
delete mode 100644 usrp2/fpga/sdr_lib/input.dat
delete mode 100644 usrp2/fpga/sdr_lib/integrate.v
delete mode 100644 usrp2/fpga/sdr_lib/med_hb_int.v
delete mode 100644 usrp2/fpga/sdr_lib/output.dat
delete mode 100644 usrp2/fpga/sdr_lib/round.v
delete mode 100644 usrp2/fpga/sdr_lib/round_reg.v
delete mode 100644 usrp2/fpga/sdr_lib/rssi.v
delete mode 100644 usrp2/fpga/sdr_lib/rx_control.v
delete mode 100644 usrp2/fpga/sdr_lib/rx_dcoffset.v
delete mode 100644 usrp2/fpga/sdr_lib/rx_dcoffset_tb.v
delete mode 100644 usrp2/fpga/sdr_lib/sign_extend.v
delete mode 100644 usrp2/fpga/sdr_lib/small_hb_dec.v
delete mode 100644 usrp2/fpga/sdr_lib/small_hb_dec_tb.v
delete mode 100644 usrp2/fpga/sdr_lib/small_hb_int.v
delete mode 100644 usrp2/fpga/sdr_lib/small_hb_int_tb.v
delete mode 100644 usrp2/fpga/sdr_lib/tx_control.v
delete mode 100644 usrp2/fpga/serdes/serdes.v
delete mode 100644 usrp2/fpga/serdes/serdes_fc_rx.v
delete mode 100644 usrp2/fpga/serdes/serdes_fc_tx.v
delete mode 100644 usrp2/fpga/serdes/serdes_rx.v
delete mode 100644 usrp2/fpga/serdes/serdes_tb.v
delete mode 100644 usrp2/fpga/serdes/serdes_tx.v
delete mode 100644 usrp2/fpga/simple_gemac/.gitignore
delete mode 100644 usrp2/fpga/simple_gemac/address_filter.v
delete mode 100644 usrp2/fpga/simple_gemac/crc.v
delete mode 100644 usrp2/fpga/simple_gemac/delay_line.v
delete mode 100644 usrp2/fpga/simple_gemac/eth_tasks.v
delete mode 100644 usrp2/fpga/simple_gemac/eth_tasks_f36.v
delete mode 100644 usrp2/fpga/simple_gemac/flow_ctrl_rx.v
delete mode 100644 usrp2/fpga/simple_gemac/flow_ctrl_tx.v
delete mode 100644 usrp2/fpga/simple_gemac/ll8_shortfifo.v
delete mode 100644 usrp2/fpga/simple_gemac/ll8_to_txmac.v
delete mode 100644 usrp2/fpga/simple_gemac/miim/eth_clockgen.v
delete mode 100644 usrp2/fpga/simple_gemac/miim/eth_miim.v
delete mode 100644 usrp2/fpga/simple_gemac/miim/eth_outputcontrol.v
delete mode 100644 usrp2/fpga/simple_gemac/miim/eth_shiftreg.v
delete mode 100644 usrp2/fpga/simple_gemac/rxmac_to_ll8.v
delete mode 100644 usrp2/fpga/simple_gemac/simple_gemac.v
delete mode 100644 usrp2/fpga/simple_gemac/simple_gemac_rx.v
delete mode 100644 usrp2/fpga/simple_gemac/simple_gemac_tb.v
delete mode 100644 usrp2/fpga/simple_gemac/simple_gemac_tx.v
delete mode 100644 usrp2/fpga/simple_gemac/simple_gemac_wb.v
delete mode 100755 usrp2/fpga/simple_gemac/simple_gemac_wrapper.build
delete mode 100644 usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
delete mode 100644 usrp2/fpga/simple_gemac/simple_gemac_wrapper_f36_tb.v
delete mode 100644 usrp2/fpga/simple_gemac/simple_gemac_wrapper_tb.v
delete mode 100644 usrp2/fpga/simple_gemac/test_packet.mem
delete mode 100644 usrp2/fpga/testbench/.gitignore
delete mode 100644 usrp2/fpga/testbench/BOOTSTRAP.sav
delete mode 100644 usrp2/fpga/testbench/Makefile
delete mode 100644 usrp2/fpga/testbench/PAUSE.sav
delete mode 100644 usrp2/fpga/testbench/README
delete mode 100644 usrp2/fpga/testbench/SERDES.sav
delete mode 100644 usrp2/fpga/testbench/U2_SIM.sav
delete mode 100644 usrp2/fpga/testbench/cmdfile
delete mode 100644 usrp2/fpga/timing/.gitignore
delete mode 100644 usrp2/fpga/timing/time_64bit.v
delete mode 100644 usrp2/fpga/timing/time_receiver.v
delete mode 100644 usrp2/fpga/timing/time_sender.v
delete mode 100644 usrp2/fpga/timing/time_sync.v
delete mode 100644 usrp2/fpga/timing/time_transfer_tb.v
delete mode 100644 usrp2/fpga/timing/timer.v
delete mode 100644 usrp2/fpga/top/.gitignore
delete mode 100644 usrp2/fpga/top/eth_test/.gitignore
delete mode 100644 usrp2/fpga/top/eth_test/eth_sim_top.v
delete mode 100644 usrp2/fpga/top/eth_test/eth_tb.v
delete mode 100644 usrp2/fpga/top/single_u2_sim/single_u2_sim.v
delete mode 100644 usrp2/fpga/top/tcl/ise_helper.tcl
delete mode 100644 usrp2/fpga/top/u2_core/.gitignore
delete mode 100755 usrp2/fpga/top/u2_core/u2_core.v
delete mode 100644 usrp2/fpga/top/u2_rev1/.gitignore
delete mode 100644 usrp2/fpga/top/u2_rev1/Makefile
delete mode 100644 usrp2/fpga/top/u2_rev1/u2_fpga.ise
delete mode 100755 usrp2/fpga/top/u2_rev1/u2_fpga.ucf
delete mode 100644 usrp2/fpga/top/u2_rev1/u2_fpga_top.prj
delete mode 100644 usrp2/fpga/top/u2_rev1/u2_fpga_top.v
delete mode 100644 usrp2/fpga/top/u2_rev2/.gitignore
delete mode 100644 usrp2/fpga/top/u2_rev2/Makefile
delete mode 100644 usrp2/fpga/top/u2_rev2/u2_rev2.ucf
delete mode 100644 usrp2/fpga/top/u2_rev2/u2_rev2.v
delete mode 100644 usrp2/fpga/top/u2_rev3/.gitignore
delete mode 100644 usrp2/fpga/top/u2_rev3/Makefile
delete mode 100644 usrp2/fpga/top/u2_rev3/u2_rev3.ucf
delete mode 100644 usrp2/fpga/top/u2_rev3/u2_rev3.v
delete mode 100644 usrp2/fpga/top/u2_rev3_2rx_iad/Makefile
delete mode 100644 usrp2/fpga/top/u2_rev3_2rx_iad/README
delete mode 100644 usrp2/fpga/top/u2_rev3_2rx_iad/cmdfile
delete mode 100644 usrp2/fpga/top/u2_rev3_2rx_iad/dsp_core_rx.v
delete mode 100644 usrp2/fpga/top/u2_rev3_2rx_iad/dsp_core_tb.sav
delete mode 100644 usrp2/fpga/top/u2_rev3_2rx_iad/dsp_core_tb.v
delete mode 100644 usrp2/fpga/top/u2_rev3_2rx_iad/impulse.v
delete mode 100755 usrp2/fpga/top/u2_rev3_2rx_iad/u2_core.v
delete mode 100755 usrp2/fpga/top/u2_rev3_2rx_iad/wave.sh
delete mode 100644 usrp2/fpga/top/u2_rev3_iad/.gitignore
delete mode 100644 usrp2/fpga/top/u2_rev3_iad/Makefile
delete mode 100644 usrp2/fpga/top/u2_rev3_iad/cmdfile
delete mode 100644 usrp2/fpga/top/u2_rev3_iad/dsp_core_rx.v
delete mode 100644 usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.sav
delete mode 100644 usrp2/fpga/top/u2_rev3_iad/dsp_core_tb.v
delete mode 100644 usrp2/fpga/top/u2_rev3_iad/impulse.v
delete mode 100755 usrp2/fpga/top/u2_rev3_iad/wave.sh
delete mode 100755 usrp2/fpga/top/u2plus/u2plus.ucf
delete mode 100644 usrp2/fpga/top/u2plus/u2plus.v
hooks/post-receive
--
git://gnuradio.org/jblum
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Commit-gnuradio] git://gnuradio.org/jblum branch, master, updated. e259d4d2eeb0b152e1e042333a8b36e07f5ad094,
git repository hosting <=