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[Commit-gnuradio] git://gnuradio.org/jcorgan branch, distcheck, updated.

From: git repository hosting
Subject: [Commit-gnuradio] git://gnuradio.org/jcorgan branch, distcheck, updated. 3.3git-640-ga2c00f5
Date: Sun, 28 Feb 2010 20:49:15 +0000 (GMT) 
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The branch, distcheck has been updated
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- Log -----------------------------------------------------------------
commit a2c00f5cff7407ff10fc6c812d06fefe52c0b6a3
Author: Johnathan Corgan <address@hidden>
Date:   Sun Feb 28 12:47:43 2010 -0800

    Remove usrp1 and usrp2 FPGA files.  These are now hosted at:
    
    git://ettus.sourcerepo.com/ettus/fpga.git
    
    ...under the 'usrp1' and 'usrp2' top-level directories.

commit db29a2cfc18554ae0a3c55a4e13dc4cbfa86317f
Author: Josh Blum <address@hidden>
Date:   Wed Feb 24 13:48:36 2010 -0800

    updated wiki url

commit 48850cce5609941289c00fea9cd3493624bf7376
Merge: b2117ee60e60a7e7cf27c6b88d45195e70185175 
ab207bece948af27e4772cb482ba9a7973b9565e 
5c4b47526413c6793463fc3bd1f408e21f65b132
Author: Johnathan Corgan <address@hidden>
Date:   Sun Feb 21 10:32:22 2010 -0800

    Merge branches 'wbx_usrp2' and 'wbx_usrp1' of git://gnuradio.org/jabele

commit b2117ee60e60a7e7cf27c6b88d45195e70185175
Merge: ceeccd034f16f0e74cde8bad57f8975159b0d217 
8daf6e19c11184fcc8e61b00a9f17fa2ad6718fa
Author: Matt Ettus <address@hidden>
Date:   Sat Feb 20 09:59:15 2010 -0800

    Merge branch 'db_default'

commit 5c4b47526413c6793463fc3bd1f408e21f65b132
Author: Jason Abele <address@hidden>
Date:   Fri Feb 19 15:24:56 2010 -0800

    Clarified copyright and licensing

commit ceeccd034f16f0e74cde8bad57f8975159b0d217
Author: Johnathan Corgan <address@hidden>
Date:   Thu Feb 18 11:14:14 2010 -0800

    Fix linker path in gr-pager

commit 8daf6e19c11184fcc8e61b00a9f17fa2ad6718fa
Author: Matt Ettus <address@hidden>
Date:   Sun Feb 14 15:18:24 2010 -0800

    remove reference to nonexistant include

commit 82dd3940e79adbebe5b05edd8ee6499be017018f
Author: Matt Ettus <address@hidden>
Date:   Sun Feb 14 10:05:36 2010 -0800

    test the ability to read default eeprom values, for D. Symeonidis

commit e566be1bb983a0f4f284081760b6f91d9986d394
Merge: 8e4bed09059a00767a8aa1cb9800059aecde52ab 
a33cbffaf802c5c3018596fcf592e37c978acfb6
Author: Johnathan Corgan <address@hidden>
Date:   Thu Feb 11 08:18:46 2010 -0800

    Merge branch 'prefix' of git://gnuradio.org/jabele

commit a33cbffaf802c5c3018596fcf592e37c978acfb6
Author: Jason Abele <address@hidden>
Date:   Thu Feb 4 17:38:33 2010 -0800

    Fixed creation of burn-usrp2-eeprom, burn-usrp4-eeprom
    
    Added $prefix from configure to paths

commit ab207bece948af27e4772cb482ba9a7973b9565e
Author: Jason Abele <address@hidden>
Date:   Wed Jan 20 18:53:17 2010 -0800

    First pass WBX USRP2 driver

commit 8e4bed09059a00767a8aa1cb9800059aecde52ab
Author: Eric Blossom <address@hidden>
Date:   Mon Feb 8 15:13:14 2010 -0800

    Regenerate defective omnithread.pdf
    
    Thanks to Dimitris Symeonidis for pointing out the problem and solution.

commit 6b1bcb301ff4cb20ac62bf5400fa3001182cb069
Author: Eric Blossom <address@hidden>
Date:   Thu Feb 4 11:37:00 2010 -0800

    Fix pick_subdevice.
    
    Patch from Alexander Chemeris <address@hidden>

commit 69cbd4af0c44e71a73b6937cfc1f0b456040fe61
Merge: 4640708a2cb9740c41f0e27a6ce865a85473a4a0 
609624f2293f6abce93cf1a8f80645108417b6c9
Author: Tom <address@hidden>
Date:   Mon Feb 1 19:45:39 2010 -0500

    Merge branch 'master' of address@hidden:gnuradio

commit 4640708a2cb9740c41f0e27a6ce865a85473a4a0
Merge: 824aa242f143a088f04031840bc36ed54de74005 
3bac2fa547168ca52352892e5f9db3335724682e
Author: Tom <address@hidden>
Date:   Mon Feb 1 19:21:54 2010 -0500

    Merge branch 'fll'

commit 3bac2fa547168ca52352892e5f9db3335724682e
Author: Tom <address@hidden>
Date:   Mon Feb 1 19:11:03 2010 -0500

    Fixing DQPSK block to work with any real value samples per symbol and 
getting object names the same as DBPSK block.

commit 83369a926b2b23280ac4709335b0115f4c145602
Author: Tom <address@hidden>
Date:   Mon Feb 1 19:05:43 2010 -0500

    Changing Makefile so the new PAM examples are installed

commit cafa42f500337c3b4b9d54b8af1c9101727267b9
Author: Tom <address@hidden>
Date:   Mon Feb 1 18:59:56 2010 -0500

    Minor adjustments to FLL example

commit 8d4804c546be699a3c3088edc7de25cfee620562
Author: Tom <address@hidden>
Date:   Mon Feb 1 18:58:37 2010 -0500

    Simplifying and using PFB resampler to generate pusle shape filtered signal.

commit 9fc527b4735db31acb967ed1309b86fd76003b03
Author: Tom <address@hidden>
Date:   Mon Feb 1 18:55:24 2010 -0500

    Using PFB resampler to generate the pulse shaping filtered signal.

commit e6e29a45df8a97c80a213645968ac01fda904777
Author: Tom <address@hidden>
Date:   Sun Jan 31 17:10:18 2010 -0500

    Preventing an error message by casting an integer (0) to the requested 
float.

commit 98a0c00c7a922e1c5cbce155205b4e5de725bcf7
Author: Tom <address@hidden>
Date:   Sun Jan 31 17:08:03 2010 -0500

    Using PFB resampler to do the RRC filtering on the modulator. This along 
with the PFB clock recovery in the demod block allows arbitrary real numbers 
for the number of samples per symbol. We will have to chance the transmit and 
recieve path code in the examples to take advantage of this.

commit fd6fd94644330a29ae0598c3ff1e75ddc196e806
Author: Tom <address@hidden>
Date:   Sun Jan 31 17:03:36 2010 -0500

    Got this wrong before. Derivative filter taps are now calculated correctly 
which makes the rest of the code work. My previous test cases must have masked 
the problem.

commit 609624f2293f6abce93cf1a8f80645108417b6c9
Author: Philip Balister <address@hidden>
Date:   Sat Jan 30 12:52:52 2010 -0500

    Update cpu detection macro to work for native build on the OMAP3.

commit 824aa242f143a088f04031840bc36ed54de74005
Author: Eric Blossom <address@hidden>
Date:   Wed Jan 27 09:42:09 2010 -0800

    update config.guess, config.sub and INSTALL

commit fcf9efa7b711953fae5a1b177d405ed52f2957cb
Author: Josh Blum <address@hidden>
Date:   Sat Jan 23 11:53:14 2010 -0800

    grc bug fix from Dimitris Symeonidis

commit cf4e5e40a77a0579f97e4306d2d51860b3b3a3f0
Author: Tom <address@hidden>
Date:   Sun Jan 17 19:19:40 2010 -0500

    Doing the same with the resampler on the receiver side.

commit b484d4b751bc08e9324425eadd269e85932f7149
Author: Tom Rondeau <address@hidden>
Date:   Sun Jan 17 19:18:39 2010 -0500

    Playing with using the resampler to allow any bit rate requested.

commit 7fa4e9a1d1f1718991150ccbf3304c0bd1998e21
Author: Tom <address@hidden>
Date:   Sun Jan 17 18:14:08 2010 -0500

    Adding FLL correction to DQPSK2 block.

commit dafe4d73fec32dfa4cbc687e3b4489784c33db92
Author: Tom <address@hidden>
Date:   Sat Jan 2 16:47:00 2010 -0500

    Fixing up loopback benchmark program for new DBPSK receiver.

commit 991ffe1dcc5ddacc4e2083d8494a9e92034aa70a
Author: Tom <address@hidden>
Date:   Sat Jan 2 16:34:20 2010 -0500

    UIC files to go along with previous commit (for QT receiver code).

commit 4f03e43efdc8736c39ff6dad10052d0e31aca62f
Author: Tom <address@hidden>
Date:   Sat Jan 2 16:33:13 2010 -0500

    Adding a routine to exercise the new DBPSK receiver code with the QT GUI.

commit 345434daf74cf642f7f7fd7ee28e51e020eadfab
Author: Tom <address@hidden>
Date:   Sat Jan 2 16:31:35 2010 -0500

    Printing FLL gain value in verbose mode.

commit a3418ea4a658cefb02e28b23a5462149aa9d05c3
Author: Tom <address@hidden>
Date:   Sat Jan 2 16:30:57 2010 -0500

    Since I'm bothering to average the error, I might as well use it.

commit 977b0e098fc602e61b7cb40791d53dde0adf63aa
Author: Tom <address@hidden>
Date:   Sun Dec 20 22:16:51 2009 -0500

    Adding FLL to QT loopback example.

commit e4c8d59714eff4ef571a43f7952a9af2f3d28a98
Author: Tom <address@hidden>
Date:   Sun Dec 20 21:57:40 2009 -0500

    Adding FLL to DBPSK demodulator block. Need OTA testing.

commit 3507e4e3d44a85db37737460aa13f86997acfbdb
Author: Tom <address@hidden>
Date:   Sun Dec 20 16:58:53 2009 -0500

    Adding some documentation.

commit 78809d52b0d28d4f8bb4aaecfe4115312b0e9ce5
Author: Tom <address@hidden>
Date:   Sun Dec 20 15:41:17 2009 -0500

    Cleaning up functions.

commit 8cc51ce7749e5c5562d208a8efaf17828295c70d
Author: Tom <address@hidden>
Date:   Sun Dec 20 15:32:23 2009 -0500

    WIP: better access to setting FLL parameters and working on getting gain 
settings better.

-----------------------------------------------------------------------

Summary of changes:
 config/gr_set_md_cpu.m4                            |    2 +-
 docs/doxygen/other/omnithread.pdf                  |  Bin 126474 -> 44848 bytes
 .../src/lib/filter/gr_pfb_arb_resampler_ccf.cc     |   33 +-
 .../src/lib/filter/gr_pfb_arb_resampler_ccf.h      |    1 +
 .../src/lib/general/gr_fll_band_edge_cc.cc         |  104 +-
 .../src/lib/general/gr_fll_band_edge_cc.h          |   40 +-
 .../src/lib/general/gr_fll_band_edge_cc.i          |    1 +
 .../src/python/gnuradio/blks2impl/dbpsk2.py        |   64 +-
 .../src/python/gnuradio/blks2impl/dqpsk2.py        |   56 +-
 gnuradio-examples/grc/Makefile.am                  |    4 +-
 gnuradio-examples/grc/demod/digital_freq_lock.grc  |   80 +-
 gnuradio-examples/grc/demod/pam_sync.grc           |  602 +-
 gnuradio-examples/grc/demod/pam_timing.grc         |  608 +-
 .../python/digital/benchmark_qt_loopback2.py       |  125 +-
 .../python/digital/benchmark_qt_rx2.py             |  474 +
 .../python/digital/qt_digital_window2.py           |  178 +-
 .../python/digital/qt_digital_window2.ui           |  299 +-
 gnuradio-examples/python/digital/qt_rx_window2.py  |  179 +
 gnuradio-examples/python/digital/qt_rx_window2.ui  |  379 +
 .../python/digital/usrp_receive_path.py            |   14 +-
 .../python/digital/usrp_transmit_path.py           |   15 +-
 gr-howto-write-a-block/INSTALL                     |  114 +-
 gr-howto-write-a-block/config.guess                |  239 +-
 gr-howto-write-a-block/config.sub                  |   91 +-
 gr-pager/swig/Makefile.am                          |    2 +-
 gr-utils/src/python/usrp_fft.py                    |    2 +-
 gr-utils/src/python/usrp_oscope.py                 |    2 +-
 grc/blocks/gr_fll_band_edge_cc.xml                 |   15 +
 grc/python/Param.py                                |    2 +-
 grc/python/Platform.py                             |    4 +-
 usrp/firmware/src/common/build_eeprom.py           |   18 +-
 usrp/firmware/src/usrp2/Makefile.am                |    4 +-
 usrp/fpga/Makefile.am                              |    2 -
 usrp/fpga/Makefile.extra                           |  181 -
 usrp/fpga/TODO                                     |   23 -
 usrp/fpga/gen_makefile_extra.py                    |   67 -
 usrp/fpga/inband_lib/chan_fifo_reader.v            |  219 -
 usrp/fpga/inband_lib/channel_demux.v               |   78 -
 usrp/fpga/inband_lib/channel_ram.v                 |  107 -
 usrp/fpga/inband_lib/cmd_reader.v                  |  305 -
 usrp/fpga/inband_lib/packet_builder.v              |  152 -
 usrp/fpga/inband_lib/register_io.v                 |   82 -
 usrp/fpga/inband_lib/rx_buffer_inband.v            |  209 -
 usrp/fpga/inband_lib/tx_buffer_inband.v            |  143 -
 usrp/fpga/inband_lib/tx_packer.v                   |  119 -
 usrp/fpga/inband_lib/usb_packet_fifo.v             |  112 -
 usrp/fpga/megacells/.gitignore                     |    1 -
 usrp/fpga/megacells/accum32.bsf                    |   86 -
 usrp/fpga/megacells/accum32.cmp                    |   31 -
 usrp/fpga/megacells/accum32.inc                    |   32 -
 usrp/fpga/megacells/accum32.v                      |  765 -
 usrp/fpga/megacells/accum32_bb.v                   |   35 -
 usrp/fpga/megacells/accum32_inst.v                 |    7 -
 usrp/fpga/megacells/add32.bsf                      |   62 -
 usrp/fpga/megacells/add32.cmp                      |   29 -
 usrp/fpga/megacells/add32.inc                      |   30 -
 usrp/fpga/megacells/add32.v                        |  221 -
 usrp/fpga/megacells/add32_bb.v                     |   31 -
 usrp/fpga/megacells/add32_inst.v                   |    5 -
 usrp/fpga/megacells/addsub16.bsf                   |   96 -
 usrp/fpga/megacells/addsub16.cmp                   |   33 -
 usrp/fpga/megacells/addsub16.inc                   |   34 -
 usrp/fpga/megacells/addsub16.v                     |  438 -
 usrp/fpga/megacells/addsub16_bb.v                  |   39 -
 usrp/fpga/megacells/addsub16_inst.v                |    9 -
 usrp/fpga/megacells/bustri.bsf                     |   62 -
 usrp/fpga/megacells/bustri.cmp                     |   29 -
 usrp/fpga/megacells/bustri.inc                     |   30 -
 usrp/fpga/megacells/bustri.v                       |   71 -
 usrp/fpga/megacells/bustri_bb.v                    |   31 -
 usrp/fpga/megacells/bustri_inst.v                  |    5 -
 usrp/fpga/megacells/clk_doubler.v                  |  198 -
 usrp/fpga/megacells/clk_doubler_bb.v               |  143 -
 usrp/fpga/megacells/dspclkpll.v                    |  237 -
 usrp/fpga/megacells/dspclkpll_bb.v                 |   31 -
 usrp/fpga/megacells/fifo_1kx16.bsf                 |  107 -
 usrp/fpga/megacells/fifo_1kx16.cmp                 |   30 -
 usrp/fpga/megacells/fifo_1kx16.inc                 |   31 -
 usrp/fpga/megacells/fifo_1kx16.v                   |  175 -
 usrp/fpga/megacells/fifo_1kx16_bb.v                |  127 -
 usrp/fpga/megacells/fifo_1kx16_inst.v              |   12 -
 usrp/fpga/megacells/fifo_2k.v                      | 3343 -
 usrp/fpga/megacells/fifo_2k_bb.v                   |  131 -
 usrp/fpga/megacells/fifo_4k.v                      | 3495 -
 usrp/fpga/megacells/fifo_4k_18.v                   |  186 -
 usrp/fpga/megacells/fifo_4k_bb.v                   |  131 -
 usrp/fpga/megacells/fifo_4kx16_dc.bsf              |  117 -
 usrp/fpga/megacells/fifo_4kx16_dc.cmp              |   31 -
 usrp/fpga/megacells/fifo_4kx16_dc.inc              |   32 -
 usrp/fpga/megacells/fifo_4kx16_dc.v                |  178 -
 usrp/fpga/megacells/fifo_4kx16_dc_bb.v             |  130 -
 usrp/fpga/megacells/fifo_4kx16_dc_inst.v           |   13 -
 usrp/fpga/megacells/mylpm_addsub.bsf               |   80 -
 usrp/fpga/megacells/mylpm_addsub.cmp               |   31 -
 usrp/fpga/megacells/mylpm_addsub.inc               |   32 -
 usrp/fpga/megacells/mylpm_addsub.v                 |  102 -
 usrp/fpga/megacells/mylpm_addsub_bb.v              |   35 -
 usrp/fpga/megacells/mylpm_addsub_inst.v            |    7 -
 usrp/fpga/megacells/pll.v                          |  207 -
 usrp/fpga/megacells/pll_bb.v                       |   29 -
 usrp/fpga/megacells/pll_inst.v                     |    4 -
 usrp/fpga/megacells/sub32.bsf                      |   87 -
 usrp/fpga/megacells/sub32.cmp                      |   32 -
 usrp/fpga/megacells/sub32.inc                      |   33 -
 usrp/fpga/megacells/sub32.v                        |  675 -
 usrp/fpga/megacells/sub32_bb.v                     |   37 -
 usrp/fpga/megacells/sub32_inst.v                   |    8 -
 usrp/fpga/models/bustri.v                          |   17 -
 usrp/fpga/models/fifo.v                            |   82 -
 usrp/fpga/models/fifo_1c_1k.v                      |   81 -
 usrp/fpga/models/fifo_1c_2k.v                      |   81 -
 usrp/fpga/models/fifo_1c_4k.v                      |   76 -
 usrp/fpga/models/fifo_1k.v                         |   24 -
 usrp/fpga/models/fifo_2k.v                         |   24 -
 usrp/fpga/models/fifo_4k.v                         |   24 -
 usrp/fpga/models/fifo_4k_18.v                      |   26 -
 usrp/fpga/models/pll.v                             |   33 -
 usrp/fpga/models/ssram.v                           |   38 -
 usrp/fpga/sdr_lib/.gitignore                       |    2 -
 usrp/fpga/sdr_lib/adc_interface.v                  |   71 -
 usrp/fpga/sdr_lib/atr_delay.v                      |   83 -
 usrp/fpga/sdr_lib/bidir_reg.v                      |   29 -
 usrp/fpga/sdr_lib/cic_dec_shifter.v                |  100 -
 usrp/fpga/sdr_lib/cic_decim.v                      |   93 -
 usrp/fpga/sdr_lib/cic_int_shifter.v                |   94 -
 usrp/fpga/sdr_lib/cic_interp.v                     |   90 -
 usrp/fpga/sdr_lib/clk_divider.v                    |   43 -
 usrp/fpga/sdr_lib/cordic.v                         |  109 -
 usrp/fpga/sdr_lib/cordic_stage.v                   |   60 -
 usrp/fpga/sdr_lib/ddc.v                            |   97 -
 usrp/fpga/sdr_lib/dpram.v                          |   47 -
 usrp/fpga/sdr_lib/duc.v                            |   95 -
 usrp/fpga/sdr_lib/ext_fifo.v                       |  126 -
 usrp/fpga/sdr_lib/gen_cordic_consts.py             |   10 -
 usrp/fpga/sdr_lib/gen_sync.v                       |   43 -
 usrp/fpga/sdr_lib/hb/acc.v                         |   22 -
 usrp/fpga/sdr_lib/hb/coeff_rom.v                   |   19 -
 usrp/fpga/sdr_lib/hb/halfband_decim.v              |  163 -
 usrp/fpga/sdr_lib/hb/halfband_interp.v             |  121 -
 usrp/fpga/sdr_lib/hb/hbd_tb/HBD                    |   80 -
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