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[Commit-gnuradio] r11658 - in gnuradio/branches/developers/ets/inband/us
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From: |
ets |
|
Subject: |
[Commit-gnuradio] r11658 - in gnuradio/branches/developers/ets/inband/usrp/fpga: inband_lib inband_lib/tb toplevel/usrp_inband_usb |
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Date: |
Thu, 22 Oct 2009 01:54:09 -0600 (MDT) |
Author: ets
Date: 2009-10-22 01:54:08 -0600 (Thu, 22 Oct 2009)
New Revision: 11658
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/time_comparator_tb.v
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/time_comparator.v
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/cmd_reader.v
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/inband_packet_defs.v
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/packet_builder.v
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
Implemented drop flag to provide feedback when packets are dropped due to past
timestamps. Currently only on the command channel.
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/cmd_reader.v
===================================================================
--- gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/cmd_reader.v
2009-10-21 21:39:37 UTC (rev 11657)
+++ gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/cmd_reader.v
2009-10-22 07:54:08 UTC (rev 11658)
@@ -1,22 +1,38 @@
module cmd_reader
- (//System
- input reset, input txclk, input [31:0] timestamp_clock,
+ (
+ //System
+ input reset,
+ input txclk,
+ input [31:0] timestamp_clock,
+
//FX2 Side
- output reg skip, output reg rdreq,
- input [31:0] fifodata, input pkt_waiting,
+ output reg skip,
+ output reg rdreq,
+ input [31:0] fifodata,
+ input pkt_waiting,
+
//Rx side
- input rx_WR_enabled, output reg [15:0] rx_databus,
- output reg rx_WR, output reg rx_WR_done,
+ input rx_WR_enabled,
+ output reg [15:0] rx_databus,
+ output reg rx_WR,
+ output reg rx_WR_done,
+ output reg tx_dropped_packet,
+
//register io
- input wire [31:0] reg_data_out, output reg [31:0] reg_data_in,
- output reg [6:0] reg_addr, output reg [1:0] reg_io_enable,
- output wire [14:0] debug, output reg stop, output reg [15:0] stop_time);
+ input wire [31:0] reg_data_out,
+ output reg [31:0] reg_data_in,
+ output reg [6:0] reg_addr,
+ output reg [1:0] reg_io_enable,
+ output wire [14:0] debug,
+ output reg stop,
+ output reg [15:0] stop_time
+ );
// States
parameter IDLE = 4'd0;
parameter HEADER = 4'd1;
parameter TIMESTAMP = 4'd2;
- parameter WAIT = 4'd3;
+ parameter WAIT = 4'd3;
parameter TEST = 4'd4;
parameter SEND = 4'd5;
parameter PING = 4'd6;
@@ -45,15 +61,37 @@
reg [1:0] lines_in;
reg [1:0] lines_out;
reg [1:0] lines_out_total;
-
+
+ reg [31:0] time_delta; //for packet time calculations
+
`define JITTER 5
`define OP_CODE 31:24
`define PAYLOAD 8:2
+
+ wire time_match;
+ wire time_valid;
+
+ time_comparator time_check (
+ .clock(timestamp_clock),
+ .timestamp(value0),
+ .match(time_match),
+ .valid(time_valid)
+ );
wire [7:0] ops;
assign ops = value0[`OP_CODE];
assign debug = {state[3:0], lines_out[1:0], pending, rx_WR, rx_WR_enabled,
value0[2:0], ops[2:0]};
-
+
+ //dropped_packet flag logic
+ always @(posedge txclk)
+ begin
+ if (!reset && state == WAIT && !time_valid)
+ tx_dropped_packet <= 1;
+ else
+ tx_dropped_packet <= 0;
+ end
+
+ //General state machine logic
always @(posedge txclk)
if (reset)
begin
@@ -65,7 +103,7 @@
reg_io_enable <= 0;
reg_data_in <= 0;
reg_addr <= 0;
- stop <= 0;
+ stop <= 0;
end
else case (state)
IDLE :
@@ -94,23 +132,17 @@
end
WAIT :
- begin
- // Let's send it
- if ((value0 <= timestamp_clock + `JITTER
- && value0 > timestamp_clock)
- || value0 == 32'hFFFFFFFF)
- state <= TEST;
- // Wait a little bit more
- else if (value0 > timestamp_clock + `JITTER)
- state <= WAIT;
- // Outdated
- else if (value0 < timestamp_clock)
- begin
- state <= IDLE;
- skip <= 1;
- end
- end
-
+ begin
+ if (time_match || (value0 == 32'hffffffff))
+ state <= TEST;
+ //TODO: echo tag field to rx buffer as
feedback of command execution
+ else if (!time_valid) begin
+ state <= IDLE;
+ skip <= 1;
+ end
+ else
+ state <= WAIT;
+ end
TEST :
begin
reg_io_enable <= 0;
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/inband_packet_defs.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/inband_packet_defs.v
2009-10-21 21:39:37 UTC (rev 11657)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/inband_packet_defs.v
2009-10-22 07:54:08 UTC (rev 11658)
@@ -40,9 +40,9 @@
`define CB_RSSI 20:15 //6
`define CB_TIMESTAMP 52:21 //32
`define CB_UNDERRUN 53 //1
+`define CB_DROPPED 54 //1
//currently unused
-`define CB_DROPPED 54 //1
`define CB_TAG 58:55 //4
`define CB_BURST_END 59 //1
`define CB_BURST_START 60 //1
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/packet_builder.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/packet_builder.v
2009-10-21 21:39:37 UTC (rev 11657)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/packet_builder.v
2009-10-22 07:54:08 UTC (rev 11658)
@@ -9,7 +9,7 @@
// cycles while the header is being sent.
// Depending on the architecture, external logic may be
// required to capture and hold volitile values
-// such as timestamp during this period. The header_rd
+// such as timestamp during this period. The header_ack
// line will be set when the header values can be released.
// chan_data should be updated on every clock cyle as long
@@ -29,7 +29,7 @@
input rden, //read enable, resets state when
clear
// Header inputs
- output reg header_rd, //header_data read
signal TODO: ren header_ack
+ output reg header_ack, //header_data read
signal
input overrun,
input underrun,
@@ -42,7 +42,7 @@
input [8:0] payload_length,
input [31:0] timestamp,
- // ADC data
+ // Signal/Channel data
output reg chan_rd, //chan_data read signal
input [15:0] chan_data,
@@ -68,9 +68,6 @@
//We want the default postion to be RD_HEADER1
//The FX2 will already be reading data when rden
//is set, so make sure it is there waiting...
- //
- //We also need to be sure to set packet complete on the last read,
- //as the channel selector needs it.
always @(posedge clk) begin
if ( rden && !packet_complete )
read_count <= read_count + 8'd1;
@@ -103,8 +100,8 @@
padding_pos <= ( payload_length >> 1 ) + (
payload_length[0] ? RD_PAYLOAD1 - 1 : RD_PAYLOAD1 - 2 );
//ack the header fifo when we are done w/ it
- //header_rd <= ( read_count == (RD_TIMESTAMP2 - 1) ) ? 1'd1 :
1'd0; //On last header read
- header_rd <= ( read_count == (RD_PAYLOAD1 - 1) ) ? 1'd1 : 1'd0;
//Delay until payload
+ //header_ack <= ( read_count == (RD_TIMESTAMP2 - 1) ) ? 1'd1 :
1'd0; //On last header read
+ header_ack <= ( read_count == (RD_PAYLOAD1 - 1) ) ? 1'd1 :
1'd0; //Delay until payload
//and the chan fifo
chan_rd <= ((read_count >= (RD_PAYLOAD1 - 1)) && (read_count <=
padding_pos)) ? 1'd1 : 1'd0;
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2009-10-21 21:39:37 UTC (rev 11657)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2009-10-22 07:54:08 UTC (rev 11658)
@@ -36,6 +36,7 @@
// rx_channel_buffer.v
// packet_builder.v
//
+// TODO: latch underrun and dropped to that each signal is guaranteed to be
sent once
// TODO: handle single channel in dual chan config (channels input)
// TODO: Refactor. This interface was kept from the original version.
@@ -89,6 +90,7 @@
input rx_WR_done,
input [15:0] rx_databus,
input [1:0] tx_underrun,
+ input tx_dropped_packet,
output rx_WR_enabled
/////////////////////
@@ -129,7 +131,7 @@
//Packet Builder
,output [7:0] dbg_read_count
,output dbg_pkt_complete
- ,output dbg_header_rd
+ ,output dbg_header_ack
,output dbg_chan_rd
);
@@ -209,7 +211,7 @@
wire [63:0] mux_header_data;
wire [15:0] mux_chan_data;
- wire header_rd;
+ wire header_ack;
wire chan_rd;
//declare nets to be assigned by generate below
@@ -217,7 +219,7 @@
wire [63:0] i_header_data[NUM_CHAN:0];
- //wire header_rd[0:NUM_CHAN];
+ //wire header_ack[0:NUM_CHAN];
//wire data_rd[0:NUM_CHAN];
wire [63:0] o_header_data[NUM_CHAN:0];
@@ -264,7 +266,7 @@
.rdclk ( usbclk_inv
),
.rd_data_en ( chan_en[i] & chan_rd
),
- .rd_header_en ( chan_en[i] & header_rd ),
+ .rd_header_en ( chan_en[i] & header_ack ),
.num_packets ( num_pkt[i]
),
.packet_rdy ( chans_ready[i]
),
.overrun ( overrun[i]
),
@@ -311,13 +313,13 @@
.reset ( reset
),
.wrclk ( rxclk
),
- .interleaved ( 1'b0
),
+ .interleaved ( 1'b0
),
.wren ( rx_WR
),
.flush_packet ( cmd_flush
),
.rdclk ( usbclk_inv
),
.rd_data_en ( chan_en[0] & chan_rd
),
- .rd_header_en ( chan_en[0] & header_rd ),
+ .rd_header_en ( chan_en[0] & header_ack ),
.num_packets ( num_pkt[0]
),
.packet_rdy ( chans_ready[0]
),
.overrun ( overrun[0]
),
@@ -359,18 +361,33 @@
assign mux_header_data = o_header_data[chan_num];
assign mux_chan_data = o_chan_data[chan_num];
-
/////////////////////////////////////////////////////////////////////////
+ // Set dropped flag on all channels if (any are) set. This is required
+ // because channels may not be semetrical. e.g. We want to know if
+ // a command is dropped, but don't expect any data returned from the
+ // command channel.
+ //
+ // Latch tx_dropped_packet flag when set, (re)set only after packet
builder
+ // has read to ensure that the flag gets sent (once).
+ reg tx_dropped_latch;
+
+ always @ (posedge rxclk or posedge header_ack)
+ if ( header_ack )
+ tx_dropped_latch <= tx_dropped_packet;
+ else if ( rxclk && tx_dropped_packet )
+ tx_dropped_latch <= tx_dropped_packet;
+
+
/////////////////////////////////////////////////////////////////////////
// Packet Builder / FX2 interface
packet_builder pb (
.clk ( usbclk_inv
),
.rden ( RD
),
- .header_rd ( header_rd
),
+ .header_ack ( header_ack
),
.overrun ( mux_header_data[`CB_OVERRUN]
),
.underrun ( mux_header_data[`CB_UNDERRUN]
),
- .dropped_packet ( mux_header_data[`CB_DROPPED]
),
+ .dropped_packet ( tx_dropped_latch
),
.start_burst ( mux_header_data[`CB_BURST_START]
),
.end_burst (
mux_header_data[`CB_BURST_END] ),
.rssi ( mux_header_data[`CB_RSSI]
),
@@ -432,7 +449,7 @@
//Packet Builder
assign dbg_pkt_complete = pkt_complete;
- assign dbg_header_rd = header_rd;
+ assign dbg_header_ack = header_ack;
assign dbg_chan_rd = chan_rd;
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/time_comparator_tb.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/time_comparator_tb.v
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tb/time_comparator_tb.v
2009-10-22 07:54:08 UTC (rev 11658)
@@ -0,0 +1,57 @@
+module time_comparator_tb;
+
+ reg [31:0] clock;
+ reg [31:0] timestamp;
+
+ wire match;
+ wire valid;
+
+`define JITTER 4
+
+ time_comparator time_check (
+ .clock(clock),
+ .timestamp(timestamp),
+ .match(match),
+ .valid(valid)
+ );
+
+ integer i;
+
+ initial begin
+ $display("timestamp,clock,match,valid");
+ $monitor("%h %h %b %b",timestamp,clock,match,valid);
+
+ $display("Normal sequence");
+ timestamp = 32'h0000003;
+ clock = 32'h0000000;
+ #1 clock = clock + 31'h1;
+ #1 clock = clock + 31'h1;
+ #1 clock = clock + 31'h1;
+ #1 clock = clock + 31'h1;
+ #1 clock = clock + 31'h1;
+
+ #1 $display("Wrap around sequence");
+ clock = 32'hfffffffe;
+ timestamp = 32'h00000001;
+ #1 clock = clock + 31'h1;
+ #1 clock = clock + 31'h1;
+ #1 clock = clock + 31'h1;
+ #1 clock = clock + 31'h1;
+ #1 clock = clock + 31'h1;
+
+ #1 $display("Into range");
+ clock = 32'h00000000;
+ timestamp = 32'h80000002;
+ #1 clock = clock + 31'h1;
+ #1 clock = clock + 31'h1;
+ #1 clock = clock + 31'h1;
+ #1 clock = clock + 31'h1;
+ #1 clock = clock + 31'h1;
+
+
+ #1 $finish;
+ end
+
+
+endmodule
+
Added:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/time_comparator.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/time_comparator.v
(rev 0)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/time_comparator.v
2009-10-22 07:54:08 UTC (rev 11658)
@@ -0,0 +1,39 @@
+//Compare times taking in account for wrap around
+//time is assumed invalid if the difference is grater than
+//half the range (which will be true if the time is past)
+
+module time_comparator
+#(parameter BITS = 32)
+(
+ input [BITS-1:0] clock,
+ input [BITS-1:0] timestamp,
+ output reg match,
+ output reg valid
+);
+
+
+ reg [BITS-1:0] half_range;
+ reg [BITS-1:0] delta;
+
+ always @*
+ begin
+ //FIXME: this should be based on BITS
+ half_range = 32'h7fffffff;
+
+ delta = timestamp - clock; //this may wrap around here, which
is ok.
+
+ if ( delta > half_range ) begin //out of range
+ valid <= 0;
+ match <= 0;
+ end
+ else if (delta == 0) begin
+ valid <= 1;
+ match <= 1;
+ end
+ else begin
+ valid <= 1;
+ match <= 0;
+ end
+ end
+
+endmodule
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2009-10-21 21:39:37 UTC (rev 11657)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2009-10-22 07:54:08 UTC (rev 11658)
@@ -3,6 +3,7 @@
input wire usbclk, input wire bus_reset, input wire reset,
input wire [15:0] usbdata, output wire have_space, input wire [3:0]
channels,
input wire [31:0] timestamp,
+
//output transmit signals
output wire [15:0] tx_i_0, output wire [15:0] tx_q_0,
output wire [15:0] tx_i_1, output wire [15:0] tx_q_1,
@@ -10,18 +11,26 @@
output wire [15:0] tx_i_3, output wire [15:0] tx_q_3,
input wire txclk, input wire txstrobe, input wire WR,
input wire clear_status, output wire tx_empty, output wire [15:0]
debugbus,
+
//command reader io
- output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done,
- input wire rx_WR_enabled,
+ input wire rx_WR_enabled,
+ output wire [15:0] rx_databus,
+ output wire rx_WR,
+ output wire rx_WR_done,
+ output wire tx_dropped_packet,
+
//register io
output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output
wire [6:0] reg_addr,
input wire [31:0] reg_data_out,
+
//input characteristic signals
input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0]
rssi_2,
input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0]
threshhold,
output wire [1:0] tx_underrun,
+
//system stop
- output wire stop, output wire [15:0] stop_time);
+ output wire stop, output wire [15:0] stop_time
+ );
parameter NUM_CHAN = 1 ;
@@ -130,7 +139,10 @@
.pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
.rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
.reg_data_in(reg_data_in), .reg_data_out(reg_data_out),
.reg_addr(reg_addr),
- .reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop),
.stop_time(stop_time));
+ .reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop),
.stop_time(stop_time),
+
+ .tx_dropped_packet(tx_dropped_packet)
+ );
endmodule // tx_buffer
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2009-10-21 21:39:37 UTC (rev 11657)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2009-10-22 07:54:08 UTC (rev 11658)
@@ -431,4 +431,5 @@
set_global_assignment -name VERILOG_FILE ../../inband_lib/register_io.v
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING
ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
\ No newline at end of file
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
+set_global_assignment -name VERILOG_FILE ../../inband_lib/time_comparator.v
\ No newline at end of file
Modified:
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2009-10-21 21:39:37 UTC (rev 11657)
+++
gnuradio/branches/developers/ets/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2009-10-22 07:54:08 UTC (rev 11658)
@@ -128,10 +128,12 @@
//Connection RX inband <-> TX inband
- wire rx_WR;
- wire [15:0] rx_databus;
- wire rx_WR_done;
- wire rx_WR_enabled;
+ wire rx_WR;
+ wire [15:0] rx_databus;
+ wire rx_WR_done;
+ wire rx_WR_enabled;
+ wire tx_dropped_packet;
+
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
`ifdef TX_ON
@@ -144,15 +146,20 @@
`ifdef TX_IN_BAND
tx_buffer_inband tx_buffer
- ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
- .usbdata(usbdata),.WR(WR),.have_space(have_space),
+ ( .usbclk(usbclk),
+ .bus_reset(tx_bus_reset),
+ .reset(tx_dsp_reset),
+ .usbdata(usbdata),.WR(WR),
+ .have_space(have_space),
.timestamp(timestamp_counter),
- .tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}),
+ .tx_underrun(tx_underrun),
+ .channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
.tx_i_3(),.tx_q_3(),
- .txclk(clk64),.txstrobe(strobe_interp),
+ .txclk(clk64),
+ .txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty),
.rx_WR(rx_WR),
@@ -166,8 +173,11 @@
.debugbus(rx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
- .stop(stop), .stop_time(stop_time));
+ .stop(stop), .stop_time(stop_time),
+ .tx_dropped_packet(tx_dropped_packet)
+ );
+
`ifdef TX_DUAL
defparam tx_buffer.NUM_CHAN=2;
`endif
@@ -289,8 +299,11 @@
.rx_WR_enabled(rx_WR_enabled),
.debugbus(tx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
- .tx_underrun(tx_underrun));
+ .tx_underrun(tx_underrun),
+ .tx_dropped_packet(tx_dropped_packet)
+ );
+
`else
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
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- [Commit-gnuradio] r11658 - in gnuradio/branches/developers/ets/inband/usrp/fpga: inband_lib inband_lib/tb toplevel/usrp_inband_usb,
ets <=