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[Commit-gnuradio] gnuradio.git at gnuradio.org branch, distcheck, update
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[Commit-gnuradio] gnuradio.git at gnuradio.org branch, distcheck, updated. 0cd478fdc090123e09b7ee21c88e5657abab8ae0 |
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Thu, 1 Oct 2009 15:28:10 -0600 (MDT) |
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via 4bb01619d8a082bcf412762f3ee147e8cd4b37dd (commit)
via 962a57badaa349da12ca552f4752329aabd4ac6f (commit)
via 35ada01aa8ae838d6d75bf063725218fa7e18f5f (commit)
via 8d3550d330eeac88f4991db866288468be084ddf (commit)
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via 7f32e69cf2d599e0c5462164500ac2337f4417a7 (commit)
via 579c6354514d57d3f1881131203ba6bbd9648816 (commit)
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via 55e8ef7a4f94e7b6562ed29626a578cca1fcec34 (commit)
via 0f03f1c1d460d865aeff91b9538266b0b210a357 (commit)
via 2c30dff7d519987a0f239f29f09e340d203c0148 (commit)
via c6f6e69024bd21e99f5f8673dce2399c4bfd8bb8 (commit)
via 433432fed1e79ca93763eec2d9186744e08d5ad1 (commit)
via 265484bfaaaab4f83c43a53c9e0fd307e205e5c4 (commit)
via 98b30a4fc683d91458ccaefeaafbc8f4b783d17e (commit)
via e67bd8ae9773731c00d2636833a9120ed3cc2ec1 (commit)
via fff854782eb2fbfc2a49e07ed9941b3beccc3e83 (commit)
via e6cb4a4c14d9aa92d024727965bd45e68c6620ce (commit)
via 158caeaa92df7ffdf363236985f4b8e7825f3950 (commit)
via f79de610d42fdbe8425a1a4aa3c04a1ee3c58e06 (commit)
via c62085a66bd97f389f49167492f7dccfb0b02976 (commit)
via bdec6a37a474b961389e0ac590d0582e490ffb2c (commit)
via 117bee2b2b88b5d348db1a8f6beb28de8340f407 (commit)
via 0d7fa4aac5b01cf463e1a065205094cd494853ee (commit)
via 3d3888c40ac46cbbd8851e9bc5e83557e0415887 (commit)
via 0854c4604fcbdb64c74e4b93b87ac07be3d75f55 (commit)
via b5aa407ec2b1bdebc1c950a9428789fe50327776 (commit)
via ab47612cf0b6f2226d192fbc9db80c5b225a4f2d (commit)
via 1e585a79df197653b752427b4372895e12afc2d4 (commit)
via d657d1baa99af56f8a4c0ed4b3bc6464313b1773 (commit)
via 4623a334d042b0f982ead3dcc7ea63015a39ff72 (commit)
via db03fafeec9d360a9837303befcc2dbcce57a06b (commit)
via 8bb9923f542caae6eca47d42c35b1c00816e61f0 (commit)
via 9e05f0770b92f9c85f09e3629f875011e8f1ac24 (commit)
via 7ab7f93a1d7eecc873155026ea06d70d2d2b2846 (commit)
via 00da83704ec4a1c9eca3eb7e90f6a8a762799217 (commit)
via c452801ce73a8467e1d5ee14f7f497e08254ef6d (commit)
via 1048666fba8abf654c9abba84a849ba2d6885221 (commit)
via 1392a442651b9528537ca722df76090bbf4de0d9 (commit)
via 2d6ac5853644d805390df01367499922eca81368 (commit)
via 02c74ee9f1c07e20097f6cfc2e7426be3a7ad06c (commit)
via 62adc385b1ea87fa924dfd15a60706bdf6be18e2 (commit)
via a1d9c0b4de66eadfdd3f6a217af80f7eb4e22772 (commit)
via 6528672f2db205b6127f05ad7c7b9da66661b498 (commit)
via 802ab4104ca9bae8b21fe9618709d5a3d8cfd77f (commit)
via 49a17dca1ee9cf7c0fd02b6baf83814a68c4e5e8 (commit)
via 7cb806f71a3bcc52c3c2e5688a9b6b48e3401615 (commit)
via 9a100f391e52106ca872dd5df8287273eea64b0c (commit)
via e103e18f8b8111cd07edc2bb0294aa58a426e371 (commit)
via f945bc6d3188d15c767706a2edbbda950a101c61 (commit)
via 96b6c7b97e3fb9188bc6906153254dc36cedc2cb (commit)
via 5d040bc94b40cab5420303f959695d89fe83e031 (commit)
via 5965a434d0923738d49334eb5f3d74a259e7b431 (commit)
via 42b10fee5167354a2927c2874cec46fc0d71a245 (commit)
via 43dec22f22e9c47b4f908675ac880a05377993fa (commit)
via 77df49ed5d2cc99ea75f3e72e9387869b35ac603 (commit)
via 19094db4bd7ba13bd80e4baa9ecdf1e7d2ac547d (commit)
via 4fff2505ffd0779126d8a2036d63f1fcc53bdb52 (commit)
via 77dc1a9ba4ce9940d974edef8711d3eba85c0608 (commit)
via 3113a7bbf56462cde4a6be4a15d5f8296e37ae8a (commit)
via 80dbcc615f408bfdb23a269a54882adae0ab405b (commit)
via a5b340fa42de5c6cc087fd4f258f9f50254a7a8f (commit)
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via 72a570279574d717325a3d65a6b435ba4eb7a82c (commit)
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via f34764905524897c57fa871f04110903dd9c468f (commit)
via ac9859282e821854badf99addea58c14aad2bcd4 (commit)
via 2846230c1296b78aa003e4b02a21bcdba10310c1 (commit)
via 7e013c464ce04a7dc559a3f2798559c0716ccae8 (commit)
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- Log -----------------------------------------------------------------
commit 0cd478fdc090123e09b7ee21c88e5657abab8ae0
Merge: bf76534044a1bbcc665f0400a53d1070cae8caf0
f4a86ccaa23e7e513dbbfa45456ea5783c106ec0
Author: Johnathan Corgan <address@hidden>
Date: Thu Oct 1 14:24:08 2009 -0700
Merge branch 'wip/libusb-1.0' of http://gnuradio.org/git/jcorgan into master
This merge adds support for libusb1.0 in the usrp component. To enable,
you must add --with-fusb-tech=libusb1 to your configure command line.
Existing support for libusb0.1 is retained, no changes are needed.
Most of the work was done here by Thomas Tsou.
* 'wip/libusb-1.0' of http://gnuradio.org/git/jcorgan: (32 commits)
Cleanup in preparation for merge
Add required include directory for new header organization
Added config.h headers to fix win32 build
Consolidate conditional headers into libusb_types.h, use automake
Change write_internal_ram in usrp_prims to print signed error code
Allow fusb_sysconfig to build on non-linux libusb-0.12 impls
Comments for usrp_prims
Removed internal functions from external header file
Moved to single generated fusb.h, headers now generated out of lib
directory
Added copyright header
Removed preprocessor declrs out of fusb.h and created separate
fusb_libusb1_base.h
Fixed libusb1 configure bug, libusb1 updates for previous usrp_prims
integration
Commonized more usrp_prims code and renamed libusb-0.12 files to libusb0
Fixed bug usb_control_transfer bug
Combined additiona usrp_prims code
Fix glitch from previous commit
changes to build on windows / cygwin
Re-added non pkgconfig support for libusb
Autoconf support for checking the required version of libusb based on
fusb-tech
Use default arguments instead of overloaded virtual constructors for
cleaner interface
...
commit f4a86ccaa23e7e513dbbfa45456ea5783c106ec0
Author: Johnathan Corgan <address@hidden>
Date: Thu Oct 1 13:51:03 2009 -0700
Cleanup in preparation for merge
Fix trailing whitespace
Use standard include guards
Add more missing config.h includes
Fixup emacs mode strings
Update copyright notices
commit 6f820db7a8076d38eb2633f44916e2328708ea42
Author: Johnathan Corgan <address@hidden>
Date: Thu Oct 1 12:47:24 2009 -0700
Add required include directory for new header organization
commit bf76534044a1bbcc665f0400a53d1070cae8caf0
Merge: e5b76a1b9239f560b3aad21d56a7b417f3c8b0b5
4743bf771fed8405b08194d8c7fb72bf8110eab3
Author: Johnathan Corgan <address@hidden>
Date: Thu Oct 1 11:00:25 2009 -0700
Merge branch 'new_eth' of http://gnuradio.org/git/matt into master
* 'new_eth' of http://gnuradio.org/git/matt: (42 commits)
Fix warnings, mostly from implicitly defined wires or unspecified widths
fullchip sim now compiles again, after moving eth and models over to new
simple_gemac
remove unused opencores
remove debugging code
no idea where this came from, it shouldn't be here
Copied wb_1master back from quad radio
Remove old mac. Good riddance.
remove unused port
More xilinx fifos, more clean up of our fifos
might as well use a cascade fifo to help timing and give a little more
capacity
fix a typo which caused tx glitches
Untested fixes for getting serdes onto the new fifo system. Compiles, at
least
Implement Eth flow control using pause frames
parameterized fifo sizes, some reformatting
remove unused old style fifo
allow control of whether or not to honor flow control, adds some debug
lines
debug the rx side
no longer used, replaced by newfifo version
remove special last_line adjustment from ethernet port
Firmware now inserts mac source address value in each frame.
...
commit 152b281b03ab6386938c2cec4394b998c4bb44ef
Author: Thomas Tsou <address@hidden>
Date: Thu Oct 1 13:33:33 2009 -0400
Added config.h headers to fix win32 build
commit 4743bf771fed8405b08194d8c7fb72bf8110eab3
Author: Matt Ettus <address@hidden>
Date: Thu Oct 1 01:02:25 2009 -0700
Fix warnings, mostly from implicitly defined wires or unspecified widths
commit 21e931766545ff93dda5ef1b72dd03f3786967ab
Author: Matt Ettus <address@hidden>
Date: Thu Oct 1 00:21:24 2009 -0700
fullchip sim now compiles again, after moving eth and models over to new
simple_gemac
commit 413d26237e93b8b019c719ed186e228a8eeb41b8
Author: Matt Ettus <address@hidden>
Date: Thu Oct 1 00:06:11 2009 -0700
remove unused opencores
commit 147de5cd3e57a07914673a31fb73a35ebf18b3a2
Author: Matt Ettus <address@hidden>
Date: Wed Sep 30 19:55:05 2009 -0700
remove debugging code
commit d37030e27d9e9c922b432c04252b1636f5160c3c
Merge: 4dfa2ad7deab0a89784906b377dbea271ba08118
016b2fb7b8da8bf10e7ee9e6465adb8d317c0a43
Author: Matt Ettus <address@hidden>
Date: Wed Sep 30 19:12:23 2009 -0700
Merge branch 'new_wb_intercon' into new_eth
Functionality should not change at all
Conflicts:
usrp2/fpga/top/u2_core/u2_core.v
commit 4dfa2ad7deab0a89784906b377dbea271ba08118
Merge: 1e3521c90f63e70e8ec4dc97574bc8b46366fc1e
c88f64ad42a8473a1749275c0e579284b20eb283
Author: Matt Ettus <address@hidden>
Date: Wed Sep 30 18:59:54 2009 -0700
Merge branch 'master' into new_eth
commit 1e3521c90f63e70e8ec4dc97574bc8b46366fc1e
Author: Matt Ettus <address@hidden>
Date: Wed Sep 30 18:37:47 2009 -0700
no idea where this came from, it shouldn't be here
commit 016b2fb7b8da8bf10e7ee9e6465adb8d317c0a43
Author: Matt Ettus <address@hidden>
Date: Wed Sep 30 17:35:14 2009 -0700
Copied wb_1master back from quad radio
more sane config options, should be exactly the same memory map
commit e5b76a1b9239f560b3aad21d56a7b417f3c8b0b5
Author: Matt Ettus <address@hidden>
Date: Tue Sep 29 22:35:38 2009 -0700
Enable pps interrupts. Not sure why they were disabled in the first place.
commit df4edacd55663aecee58a9b3f95cbc08bceaab81
Author: Johnathan Corgan <address@hidden>
Date: Tue Sep 29 18:29:44 2009 -0700
Consolidate conditional headers into libusb_types.h, use automake
commit c88f64ad42a8473a1749275c0e579284b20eb283
Merge: fb4883e9d4b6d4b25f4167d074a51eb109c69e93
745a36295016a08bcf8e81e0246b53cd1a487716
Author: Johnathan Corgan <address@hidden>
Date: Mon Sep 28 17:52:53 2009 -0700
Merge branch 'wip/gr-noaa' of http://gnuradio.org/git/jcorgan into master
* 'wip/gr-noaa' of http://gnuradio.org/git/jcorgan:
Restored original HRPT GUI script and documented various script choices.
Renamed simplified HRPT script to allow restoring original
General improvements in HRPT receiver
commit fb4883e9d4b6d4b25f4167d074a51eb109c69e93
Author: Thomas Tsou <address@hidden>
Date: Mon Sep 28 18:14:31 2009 -0400
Removed multiple install of noaa_swig.i from Makefile.am
commit 745a36295016a08bcf8e81e0246b53cd1a487716
Author: Johnathan Corgan <address@hidden>
Date: Sun Sep 27 13:46:00 2009 -0700
Restored original HRPT GUI script and documented various script choices.
commit db2f60baf542ac35151eb7084e274701861bacc5
Author: Johnathan Corgan <address@hidden>
Date: Sun Sep 27 13:34:20 2009 -0700
Renamed simplified HRPT script to allow restoring original
commit ec8c8e0e9d68383279b0fb51a52adf04f11fd88a
Author: Johnathan Corgan <address@hidden>
Date: Sun Sep 27 10:15:04 2009 -0700
General improvements in HRPT receiver
Added usrp_rx_hrpt_nogui script
Simplified usrp_rx_hrpt script for lower CPU usage
Changed matched filtering taps to be whole symbol
commit 9a64a37f23ea4ea7571ad6dff873a2b43551b9aa
Merge: 368d4a0be388cd052510b06a3f3ddfbdf48be024
dcd4b6efd6e0a0130fbdc8f8aa5db1bc182e653f
Author: Johnathan Corgan <address@hidden>
Date: Fri Sep 25 13:24:53 2009 -0700
Merge branch 'grc' of http://gnuradio.org/git/jblum
* 'grc' of http://gnuradio.org/git/jblum:
hash the tuple of hashes to id the current params
commit 368d4a0be388cd052510b06a3f3ddfbdf48be024
Merge: 5d1ce94095bd2120a2fd2df087aae45085f53989
7b210507ae0f666e4e4f0ff5acf2abb0b803de74
Author: Johnathan Corgan <address@hidden>
Date: Fri Sep 25 13:14:58 2009 -0700
Merge branch 'gr-noaa-fixes' of http://gnuradio.org/git/balister into master
* 'gr-noaa-fixes' of http://gnuradio.org/git/balister:
Add missing cstdio include for gcc 4.4 compatibility.
commit 7b210507ae0f666e4e4f0ff5acf2abb0b803de74
Author: Philip Balister <address@hidden>
Date: Fri Sep 25 15:57:37 2009 -0400
Add missing cstdio include for gcc 4.4 compatibility.
commit dcd4b6efd6e0a0130fbdc8f8aa5db1bc182e653f
Author: Josh Blum <address@hidden>
Date: Fri Sep 25 12:54:33 2009 -0700
hash the tuple of hashes to id the current params
commit 5d1ce94095bd2120a2fd2df087aae45085f53989
Author: Johnathan Corgan <address@hidden>
Date: Fri Sep 25 12:27:29 2009 -0700
Revert "Merge branch 'grc' of http://gnuradio.org/git/jblum"
This reverts commit 06281feea16143ca97a77348f72e1c6dd0616c57.
commit 06281feea16143ca97a77348f72e1c6dd0616c57
Merge: ac4dd2f70f90081f5ae945a4fb1b585dc6326bb9
fd37328c778ea8014e9ea9d932e61e5d229dd012
Author: Johnathan Corgan <address@hidden>
Date: Fri Sep 25 11:58:45 2009 -0700
Merge branch 'grc' of http://gnuradio.org/git/jblum
* 'grc' of http://gnuradio.org/git/jblum:
Added a run options to the "no gui" generate options.
commit ac4dd2f70f90081f5ae945a4fb1b585dc6326bb9
Author: Johnathan Corgan <address@hidden>
Date: Fri Sep 25 11:29:49 2009 -0700
Add missing include file in gnuradio-core
commit 7ea3f2bd1755b260182ebbc2953aea1b3efcc4b1
Merge: 16474a0adb44dc81a8338a9c4a9a6dcab6f6328f
2af86109a0645d5f014205f519f50da22cc7cda9
Author: Johnathan Corgan <address@hidden>
Date: Fri Sep 25 08:06:45 2009 -0700
Merge branch 'wip/deb' of http://gnuradio.org/git/jcorgan
* 'wip/deb' of http://gnuradio.org/git/jcorgan:
Misc. packaging tweaks
Merged Bdale's 3.2.2-1 packaging
commit 2af86109a0645d5f014205f519f50da22cc7cda9
Author: Johnathan Corgan <address@hidden>
Date: Fri Sep 25 07:05:13 2009 -0700
Misc. packaging tweaks
Note gcell/apps/gen_script.py needs to use git
Install gnuradio-config-info in libgnuradio-core0
Add pfb examples to gnuradio-examples
Add missing python files in gnuradio-examples
commit fd37328c778ea8014e9ea9d932e61e5d229dd012
Author: Josh Blum <address@hidden>
Date: Fri Sep 25 00:24:48 2009 -0700
Added a run options to the "no gui" generate options.
The user can select between run to completion and prompt for exit.
Also fixed the props dialog is changed function to have better hashes.
Now we hash a tuple of all "relevant" items which is "order aware".
Since xoring the individual hashes proved faulty when 2 params alternated
hiding.
commit 5c46578ba936de57e80594540804c964aa408f73
Merge: 35ada01aa8ae838d6d75bf063725218fa7e18f5f
16474a0adb44dc81a8338a9c4a9a6dcab6f6328f
Author: Matt Ettus <address@hidden>
Date: Thu Sep 24 22:34:06 2009 -0700
Merge commit 'origin' into new_eth
Conflicts:
.gitignore
commit 16474a0adb44dc81a8338a9c4a9a6dcab6f6328f
Merge: 3c9b9b58f4ba22245f573da8d40d34b8fb5520ce
ef5a7328480827084d6c86e71f54c66bb42a2645
Author: Johnathan Corgan <address@hidden>
Date: Thu Sep 24 15:51:26 2009 -0700
Merge branch 'rx_mimo_hb_sync' of http://gnuradio.org/git/matt
* 'rx_mimo_hb_sync' of http://gnuradio.org/git/matt:
Synchronize the internal phase of the halfband filters to the
commit 047540337c60a4856d573d6919efd6a0ed3f491f
Author: Johnathan Corgan <address@hidden>
Date: Thu Sep 24 15:35:07 2009 -0700
Merged Bdale's 3.2.2-1 packaging
Three-way merge on files (3.2.2->bdale, 3.2.2->3.3git)
Merged control, rules, install, copyright, changelog
File renames to accomodate package renames
3.3git items updated to follow new pattern
Updated copyright notification
Some manual fixups needed
commit ef5a7328480827084d6c86e71f54c66bb42a2645
Author: Matt Ettus <address@hidden>
Date: Thu Sep 24 12:33:22 2009 -0700
Synchronize the internal phase of the halfband filters to the
start of the "run" signal. This is important for MIMO. Bug
reported by Christoph Hein and Hanwen .
commit 3c9b9b58f4ba22245f573da8d40d34b8fb5520ce
Author: Johnathan Corgan <address@hidden>
Date: Thu Sep 24 11:49:19 2009 -0700
Acknowledging the obvious
commit 4bb01619d8a082bcf412762f3ee147e8cd4b37dd
Author: Johnathan Corgan <address@hidden>
Date: Wed Sep 23 19:11:36 2009 -0700
Fix missing type specifier for mask
commit 962a57badaa349da12ca552f4752329aabd4ac6f
Author: Thomas Tsou <address@hidden>
Date: Wed Sep 23 17:50:48 2009 -0400
Change write_internal_ram in usrp_prims to print signed error code
commit 35ada01aa8ae838d6d75bf063725218fa7e18f5f
Merge: ab47612cf0b6f2226d192fbc9db80c5b225a4f2d
8bb9923f542caae6eca47d42c35b1c00816e61f0
Author: Matt Ettus <address@hidden>
Date: Sun Sep 20 17:30:27 2009 -0700
Merge branch 'serdes_newfifo' into new_eth
commit 8d3550d330eeac88f4991db866288468be084ddf
Author: ttsou <address@hidden>
Date: Thu Sep 17 11:24:55 2009 -0400
Allow fusb_sysconfig to build on non-linux libusb-0.12 impls
commit 943a61fcc94d7668c4abf5133806398e8d75148b
Author: ttsou <address@hidden>
Date: Wed Sep 16 16:39:35 2009 -0400
Comments for usrp_prims
commit 889a053c6171a6bc6746aa4e36056a073e8bec4f
Author: ttsou <address@hidden>
Date: Tue Sep 15 20:28:04 2009 -0400
Removed internal functions from external header file
commit 44269e7b15129102f93131269e7796fde70ddc05
Author: ttsou <address@hidden>
Date: Mon Sep 14 21:42:03 2009 -0400
Moved to single generated fusb.h, headers now generated out of lib directory
commit 7f32e69cf2d599e0c5462164500ac2337f4417a7
Author: ttsou <address@hidden>
Date: Mon Sep 14 19:56:53 2009 -0400
Added copyright header
commit 579c6354514d57d3f1881131203ba6bbd9648816
Author: ttsou <address@hidden>
Date: Mon Sep 14 19:50:26 2009 -0400
Removed preprocessor declrs out of fusb.h and created separate
fusb_libusb1_base.h
commit dce6d742c364daedda2f6e79da09e552ee910ede
Author: ttsou <address@hidden>
Date: Mon Sep 14 18:51:28 2009 -0400
Fixed libusb1 configure bug, libusb1 updates for previous usrp_prims
integration
commit 68b0364367f8d99a34f0c38e8a0db0a290f297fc
Author: ttsou <address@hidden>
Date: Mon Sep 14 14:43:37 2009 -0400
Commonized more usrp_prims code and renamed libusb-0.12 files to libusb0
commit 55e8ef7a4f94e7b6562ed29626a578cca1fcec34
Author: ttsou <address@hidden>
Date: Mon Sep 14 01:16:52 2009 -0400
Fixed bug usb_control_transfer bug
commit 0f03f1c1d460d865aeff91b9538266b0b210a357
Author: ttsou <address@hidden>
Date: Mon Sep 14 00:08:02 2009 -0400
Combined additiona usrp_prims code
commit 2c30dff7d519987a0f239f29f09e340d203c0148
Author: ttsou <address@hidden>
Date: Sun Sep 13 18:44:04 2009 -0400
Fix glitch from previous commit
commit c6f6e69024bd21e99f5f8673dce2399c4bfd8bb8
Author: U-CERVELO\ttsou <address@hidden(none)>
Date: Fri Sep 11 15:35:28 2009 -0400
changes to build on windows / cygwin
commit 433432fed1e79ca93763eec2d9186744e08d5ad1
Author: ttsou <address@hidden>
Date: Thu Sep 10 17:29:04 2009 -0400
Re-added non pkgconfig support for libusb
commit 265484bfaaaab4f83c43a53c9e0fd307e205e5c4
Author: ttsou <address@hidden>
Date: Thu Sep 10 16:33:49 2009 -0400
Autoconf support for checking the required version of libusb based on
fusb-tech
commit 98b30a4fc683d91458ccaefeaafbc8f4b783d17e
Author: ttsou <address@hidden>
Date: Thu Sep 10 15:08:16 2009 -0400
Use default arguments instead of overloaded virtual constructors for
cleaner interface
commit e67bd8ae9773731c00d2636833a9120ed3cc2ec1
Author: ttsou <address@hidden>
Date: Thu Sep 10 14:23:10 2009 -0400
Integrated more usrp_prims code
commit fff854782eb2fbfc2a49e07ed9941b3beccc3e83
Author: Thomas Tsou <address@hidden>
Date: Wed Sep 9 18:52:34 2009 -0400
Fixed swig and usrp apps to work with libusb-0.12 and libusb-1.0 plus minor
cleanup
commit e6cb4a4c14d9aa92d024727965bd45e68c6620ce
Author: ttsou <address@hidden>
Date: Wed Sep 9 14:46:57 2009 -0400
Intermediate fix to simplify usrp_one_time_init api
commit 158caeaa92df7ffdf363236985f4b8e7825f3950
Author: ttsou <address@hidden>
Date: Wed Sep 9 11:02:41 2009 -0400
Added autotools header generation and build time version checking
commit f79de610d42fdbe8425a1a4aa3c04a1ee3c58e06
Author: ttsou <address@hidden>
Date: Fri Aug 28 11:42:41 2009 -0400
Added libusb1 specific usrp_prims and usrp_basic
commit c62085a66bd97f389f49167492f7dccfb0b02976
Author: ttsou <address@hidden>
Date: Thu Aug 27 18:13:54 2009 -0400
first shot at re-adding libusb-0.12 support
commit bdec6a37a474b961389e0ac590d0582e490ffb2c
Author: ttsou <address@hidden>
Date: Wed Aug 26 10:46:56 2009 -0400
Modify apps and swig to reflect libusb_context use
commit 117bee2b2b88b5d348db1a8f6beb28de8340f407
Author: ttsou <address@hidden>
Date: Tue Aug 25 19:52:29 2009 -0400
Additional comments for reaping transactions
commit 0d7fa4aac5b01cf463e1a065205094cd494853ee
Author: ttsou <address@hidden>
Date: Tue Aug 25 19:30:39 2009 -0400
Additional comments for reaping transactions
commit 3d3888c40ac46cbbd8851e9bc5e83557e0415887
Author: ttsou <address@hidden>
Date: Tue Aug 25 18:46:14 2009 -0400
non-blocking reap and fusb default buffer size change
commit 0854c4604fcbdb64c74e4b93b87ac07be3d75f55
Author: ttsou <address@hidden>
Date: Tue Aug 25 14:53:34 2009 -0400
Fix for simultaneous tx-rx using libusb_contexts
commit b5aa407ec2b1bdebc1c950a9428789fe50327776
Author: Johnathan Corgan <address@hidden>
Date: Mon Aug 17 23:46:30 2009 -0400
Applied libusb-1.0 patch set from Thomas Tsou <address@hidden>:
This patch set updates the usrp to support libusb-1.0. Asynchronous I/O
through libusb is added with fusb_libusb1.*, which is heavily based on
fusb_linux.*. In short, URB's and ioctl calls are replaced with
libusb_transfer structs and native calls. Transfer reaping is handled by
libusb and associated callbacks. I get 32Mb/s on all of my machines using
test_usrp_standard_rx or tx. Due to the API rewrite in 1.0 from 0.12, there
are alot of changes, many are simply name changes.
Known Issues:
Transmit and receive both work, but not at same time
(e.g. usrp_benchmark_usb.py). libusb does not create any internal threads,
so for a single session fusb_libusb1 works in the same manner as
fusb_linux with the callback called at controlled times. With multiple
libusb sessions the callback may occur at any time and threading issues
come into play causing behavior to become undefined. The use of separate
libusb_contexts _might_ solve this issue; I have not had the time to look
into it.
commit ab47612cf0b6f2226d192fbc9db80c5b225a4f2d
Author: Matt Ettus <address@hidden>
Date: Thu Sep 10 23:11:44 2009 -0700
Remove old mac. Good riddance.
commit 1e585a79df197653b752427b4372895e12afc2d4
Author: Matt Ettus <address@hidden>
Date: Thu Sep 10 21:53:32 2009 -0700
remove unused port
commit d657d1baa99af56f8a4c0ed4b3bc6464313b1773
Author: Matt Ettus <address@hidden>
Date: Thu Sep 10 21:52:06 2009 -0700
More xilinx fifos, more clean up of our fifos
commit 4623a334d042b0f982ead3dcc7ea63015a39ff72
Author: Matt Ettus <address@hidden>
Date: Thu Sep 10 11:40:18 2009 -0700
might as well use a cascade fifo to help timing and give a little more
capacity
commit db03fafeec9d360a9837303befcc2dbcce57a06b
Author: Matt Ettus <address@hidden>
Date: Sat Sep 5 13:38:13 2009 -0700
fix a typo which caused tx glitches
commit 8bb9923f542caae6eca47d42c35b1c00816e61f0
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 22:33:30 2009 -0700
Untested fixes for getting serdes onto the new fifo system. Compiles, at
least
commit 9e05f0770b92f9c85f09e3629f875011e8f1ac24
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 22:23:27 2009 -0700
Implement Eth flow control using pause frames
Not fully tested, but it seems to work without frame errors, sequence
number errors or ethernet overruns. Still of course will get tx underruns
on a slow machine, and the transmitted signal has some issues though.
commit 7ab7f93a1d7eecc873155026ea06d70d2d2b2846
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 22:20:19 2009 -0700
parameterized fifo sizes, some reformatting
commit 00da83704ec4a1c9eca3eb7e90f6a8a762799217
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 22:14:21 2009 -0700
remove unused old style fifo
commit c452801ce73a8467e1d5ee14f7f497e08254ef6d
Merge: 1048666fba8abf654c9abba84a849ba2d6885221
02c74ee9f1c07e20097f6cfc2e7426be3a7ad06c
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 16:47:43 2009 -0700
Merge branch 'new_eth' of http://gnuradio.org/git/eb into new_eth
commit 1048666fba8abf654c9abba84a849ba2d6885221
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 16:43:11 2009 -0700
allow control of whether or not to honor flow control, adds some debug lines
commit 1392a442651b9528537ca722df76090bbf4de0d9
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 16:37:29 2009 -0700
debug the rx side
commit 2d6ac5853644d805390df01367499922eca81368
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 16:33:00 2009 -0700
no longer used, replaced by newfifo version
commit 02c74ee9f1c07e20097f6cfc2e7426be3a7ad06c
Merge: a1d9c0b4de66eadfdd3f6a217af80f7eb4e22772
62adc385b1ea87fa924dfd15a60706bdf6be18e2
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 15:58:33 2009 -0700
Merge branch 'new_eth' of http://gnuradio.org/git/matt into new_eth
* 'new_eth' of http://gnuradio.org/git/matt:
commit 62adc385b1ea87fa924dfd15a60706bdf6be18e2
Merge: 802ab4104ca9bae8b21fe9618709d5a3d8cfd77f
6528672f2db205b6127f05ad7c7b9da66661b498
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 15:53:46 2009 -0700
Merge branch 'new_eth' of http://gnuradio.org/git/eb into new_eth
commit a1d9c0b4de66eadfdd3f6a217af80f7eb4e22772
Merge: 6528672f2db205b6127f05ad7c7b9da66661b498
7cb806f71a3bcc52c3c2e5688a9b6b48e3401615
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 15:51:52 2009 -0700
Merge branch 'new_eth' of http://gnuradio.org/git/matt into new_eth
* 'new_eth' of http://gnuradio.org/git/matt:
properly set the address filter
stop sending short ethernet command packets.
Fix problem with commands timing out (specifically stop_rx_streaming)
Fix race condition that caused commands such as stop_rx_streaming to fail.
Fixing a line in the clock recovery algorithm. This works with a bit
larger error than there proably should be.
Better fix for broken AC_PROG_F77 macro
Fix Python header check failure due to invalid cached state
waterfall and fft use a common autoscale function
Fix so that the waterfall texture is initialized with a buffer of the
same size.
Modifications to usrp2 source and sink so that set center freq is called
afer set lo offset.
Modifications to the usrp blocks and wrapper so that the lo offset is set
with the lo frequency.
Removed subversion related configuration info.
Expand frequency ranges to match hardware capability.
Modified log power fft block so ref scale is peak to peak.
Adding clock sync algorithm using PFB. This works, but needs a bit more
work.
commit 6528672f2db205b6127f05ad7c7b9da66661b498
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 15:47:32 2009 -0700
remove special last_line adjustment from ethernet port
commit 802ab4104ca9bae8b21fe9618709d5a3d8cfd77f
Merge: 7cb806f71a3bcc52c3c2e5688a9b6b48e3401615
49a17dca1ee9cf7c0fd02b6baf83814a68c4e5e8
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 15:44:47 2009 -0700
Merge branch 'new_eth' of http://gnuradio.org/git/eb into new_eth
commit 49a17dca1ee9cf7c0fd02b6baf83814a68c4e5e8
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 15:35:01 2009 -0700
Firmware now inserts mac source address value in each frame.
The old mac used to do this automatically.
commit 7cb806f71a3bcc52c3c2e5688a9b6b48e3401615
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 15:31:26 2009 -0700
properly set the address filter
commit 9a100f391e52106ca872dd5df8287273eea64b0c
Merge: f945bc6d3188d15c767706a2edbbda950a101c61
5965a434d0923738d49334eb5f3d74a259e7b431
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 15:07:06 2009 -0700
Merge branch 'new_eth' of http://gnuradio.org/git/matt into new_eth
* 'new_eth' of http://gnuradio.org/git/matt:
seems to build a decent fpga, but still some issues with a full
connection.
commit e103e18f8b8111cd07edc2bb0294aa58a426e371
Merge: 5965a434d0923738d49334eb5f3d74a259e7b431
20006003431d7260b04964eb684b1746ffb0a85f
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 10:29:00 2009 -0700
Merge branch 'master' into new_eth
commit f945bc6d3188d15c767706a2edbbda950a101c61
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 03:48:15 2009 -0700
stop sending short ethernet command packets.
commit 96b6c7b97e3fb9188bc6906153254dc36cedc2cb
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 03:32:32 2009 -0700
Fix problem with commands timing out (specifically stop_rx_streaming)
After fixing the race, this change uses Tom's idea to stop enqueuing
data when trying to stop, and adds a new flush_rx_samples method
to drop any samples that may have already been accumulated.
I ran Tom's test case 500 times with 0 failures ;-)
commit 5d040bc94b40cab5420303f959695d89fe83e031
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 01:51:29 2009 -0700
Fix race condition that caused commands such as stop_rx_streaming to fail.
This fixes the bulk of the problem. Next step is to drop data packets
while waiting for the reply.
commit 5965a434d0923738d49334eb5f3d74a259e7b431
Author: Matt Ettus <address@hidden>
Date: Thu Sep 3 21:39:48 2009 -0700
seems to build a decent fpga, but still some issues with a full connection.
commit 42b10fee5167354a2927c2874cec46fc0d71a245
Author: Eric Blossom <address@hidden>
Date: Thu Sep 3 16:12:40 2009 -0700
removed hard-coded link_is_up = true;
commit 43dec22f22e9c47b4f908675ac880a05377993fa
Author: Matt Ettus <address@hidden>
Date: Thu Sep 3 14:13:44 2009 -0700
MAC transmit seems to work now. The root cause of the problem was
accidentally using the rx_clk in one stage of the fifos on the tx side.
commit 77df49ed5d2cc99ea75f3e72e9387869b35ac603
Author: Matt Ettus <address@hidden>
Date: Thu Sep 3 10:41:26 2009 -0700
set device to xc3s2000. Shouldn't make any differences.
commit 19094db4bd7ba13bd80e4baa9ecdf1e7d2ac547d
Author: Matt Ettus <address@hidden>
Date: Thu Sep 3 10:39:37 2009 -0700
misc ignores
commit 4fff2505ffd0779126d8a2036d63f1fcc53bdb52
Author: Matt Ettus <address@hidden>
Date: Thu Sep 3 10:37:35 2009 -0700
made a new block ram based fifo, 64 (65) elements long, all fifos now have
"enhanced level logic" for accurate fullness. Maybe this will help...
commit 77dc1a9ba4ce9940d974edef8711d3eba85c0608
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 21:27:18 2009 -0700
bring the testbench files up to date
commit 3113a7bbf56462cde4a6be4a15d5f8296e37ae8a
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 17:56:26 2009 -0700
major cleanup of 2 clock fifos
commit 80dbcc615f408bfdb23a269a54882adae0ab405b
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 17:28:57 2009 -0700
cleaning up the new fifos
commit a5b340fa42de5c6cc087fd4f258f9f50254a7a8f
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 17:23:12 2009 -0700
cascadefifo.v wasn't used, only the double cascade version. fifo_2clock.v
and fifo_2clock.v are empty
commit 95e6a1167b1de5d23053fda76678df297e43eedf
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 17:09:16 2009 -0700
never used, not needed
commit 72a570279574d717325a3d65a6b435ba4eb7a82c
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 17:05:45 2009 -0700
ignore .o files
commit 78588fb1608eaec95827da07c0bebee8e0fab3b6
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 17:04:53 2009 -0700
debug pins, cleaned ignores
commit f34764905524897c57fa871f04110903dd9c468f
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 17:01:28 2009 -0700
sort out active-low lines on locallink fifos, added debug pins
commit ac9859282e821854badf99addea58c14aad2bcd4
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 16:46:06 2009 -0700
Removed these files completely, they were for the old style of fifos
commit 2846230c1296b78aa003e4b02a21bcdba10310c1
Author: Matt Ettus <address@hidden>
Date: Tue Sep 1 23:19:15 2009 -0700
fixed addressing of registers, and added write enables to those that were
missing. MDIO seems ok.
commit 7e013c464ce04a7dc559a3f2798559c0716ccae8
Author: Eric Blossom <address@hidden>
Date: Tue Sep 1 18:43:07 2009 -0700
tell s/w link is up. additional debugging output
commit 7eea883c377f64862a4d83f1b33a83fdf3cfc392
Author: Johnathan Corgan <address@hidden>
Date: Mon Aug 31 12:08:30 2009 -0700
Merged SVN matt/new_eth r10782:11633 into new_eth
* svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth
-r10782:11633
* Patch applied with no conflicts or fuzz.
-----------------------------------------------------------------------
Summary of changes:
config/grc_usrp.m4 | 4 +-
config/usrp_fusb_tech.m4 | 15 +-
config/usrp_libusb.m4 | 64 +-
configure.ac | 3 +-
debian/.gitignore | 121 +-
debian/bin/gen-install-files.sh | 51 +-
debian/changelog | 99 +
debian/changelog.in | 122 -
debian/control | 134 +-
debian/copyright | 157 +-
debian/custom/{libusrp.udev => libusrp0.udev} | 0
.../custom/{libusrp2.limits => libusrp2-0.limits} | 0
debian/custom/usrp.hotplug | 47 -
debian/libgnuradio-core.install | 3 -
...ibgnuradio-core.dirs => libgnuradio-core0.dirs} | 0
debian/libgnuradio-core0.install | 4 +
...mnithread-dev.dirs => libgromnithread-dev.dirs} | 0
...ead-dev.install => libgromnithread-dev.install} | 0
...omnithread.install => libgromnithread0.install} | 0
debian/{libgruel.install => libgruel0.install} | 0
debian/{libmblock.install => libmblock0.install} | 0
debian/libusrp-inband.install | 2 -
debian/libusrp.postinst | 15 -
debian/libusrp.postrm | 10 -
debian/{libusrp.dirs => libusrp0.dirs} | 0
debian/{libusrp.install => libusrp0.install} | 0
debian/libusrp0.postinst | 16 +
debian/{libusrp2.dirs => libusrp2-0.dirs} | 0
debian/libusrp2-0.install | 5 +
debian/libusrp2-0.postinst | 20 +
debian/libusrp2.install | 5 -
debian/libusrp2.postinst | 18 -
debian/libusrp2.postrm | 10 -
debian/rules | 14 +-
gcell/apps/gen_script.py | 1 +
.../src/lib/filter/gr_pfb_channelizer_ccf.cc | 1 +
gr-noaa/README | 22 +-
gr-noaa/apps/Makefile.am | 4 +
gr-noaa/apps/demod_hrpt_file.grc | 331 +-
gr-noaa/apps/demod_hrpt_file.py | 55 +-
gr-noaa/apps/usrp_rx_hrpt.grc | 455 +-
gr-noaa/apps/usrp_rx_hrpt.py | 27 +-
gr-noaa/apps/usrp_rx_hrpt2.grc | 1418 +
gr-noaa/apps/usrp_rx_hrpt2.py | 401 +
gr-noaa/apps/usrp_rx_hrpt_nogui.grc | 869 +
gr-noaa/apps/usrp_rx_hrpt_nogui.py | 250 +
gr-noaa/lib/noaa_hrpt_deframer.cc | 3 +-
gr-noaa/swig/Makefile.am | 1 -
grc/base/Block.py | 2 +-
usrp/host/apps/test_usrp_standard_rx.cc | 1 -
usrp/host/apps/test_usrp_standard_tx.cc | 1 -
usrp/host/apps/usrp_cal_dc_offset.cc | 1 -
usrp/host/apps/usrper.cc | 11 +-
usrp/host/include/usrp/.gitignore | 3 +
usrp/host/include/usrp/Makefile.am | 4 +
usrp/host/include/usrp/libusb_types.h.in | 38 +
usrp/host/include/usrp/usrp_basic.h | 70 +-
usrp/host/include/usrp/usrp_prims.h | 144 +-
usrp/host/lib/Makefile.am | 57 +-
usrp/host/lib/db_base.cc | 4 +
usrp/host/lib/db_basic.cc | 4 +
usrp/host/lib/db_boards.cc | 4 +
usrp/host/lib/db_dbs_rx.cc | 6 +-
usrp/host/lib/db_dtt754.cc | 6 +-
usrp/host/lib/db_dtt768.cc | 6 +-
usrp/host/lib/db_flexrf.cc | 6 +-
usrp/host/lib/db_flexrf_mimo.cc | 4 +
usrp/host/lib/db_tv_rx.cc | 6 +-
usrp/host/lib/db_tv_rx_mimo.cc | 6 +-
usrp/host/lib/db_xcvr2450.cc | 4 +
usrp/host/lib/fusb.cc | 5 +-
usrp/host/lib/fusb.h | 26 +-
usrp/host/lib/fusb_libusb1.cc | 694 +
usrp/host/lib/fusb_libusb1.h | 131 +
usrp/host/lib/fusb_sysconfig_darwin.cc | 4 +-
usrp/host/lib/fusb_sysconfig_generic.cc | 4 +-
usrp/host/lib/fusb_sysconfig_libusb1.cc | 51 +
usrp/host/lib/fusb_sysconfig_linux.cc | 12 +-
usrp/host/lib/fusb_sysconfig_ra_wb.cc | 4 +-
usrp/host/lib/fusb_sysconfig_win32.cc | 4 +-
usrp/host/lib/usrp_basic.cc | 1552 -
usrp/host/lib/usrp_basic.h.in | 960 +
usrp/host/lib/usrp_basic_common.cc | 1475 +
usrp/host/lib/usrp_basic_libusb0.cc | 137 +
usrp/host/lib/usrp_basic_libusb1.cc | 145 +
usrp/host/lib/usrp_prims.cc | 1357 -
usrp/host/lib/usrp_prims_common.cc | 1231 +
usrp/host/lib/usrp_prims_libusb0.cc | 207 +
usrp/host/lib/usrp_prims_libusb1.cc | 202 +
usrp/host/lib/usrp_primsi.h | 59 +
usrp/host/lib/usrp_standard.cc | 4 +
usrp/host/swig/Makefile.am | 1 +
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usrp2/fpga/sdr_lib/dsp_core_rx.v | 8 +-
usrp2/fpga/sdr_lib/hb_dec.v | 5 +-
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usrp2/fpga/sdr_lib/small_hb_dec.v | 22 +-
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usrp2/fpga/simple_gemac/eth_tasks_f36.v | 92 +
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usrp2/fpga/simple_gemac/simple_gemac_rx.v | 50 +-
usrp2/fpga/simple_gemac/simple_gemac_tx.v | 16 +-
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rename debian/custom/{libusrp2.limits => libusrp2-0.limits} (100%)
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rename debian/{libgnuradio-omnithread-dev.dirs => libgromnithread-dev.dirs}
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libgromnithread-dev.install} (100%)
rename debian/{libgnuradio-omnithread.install => libgromnithread0.install}
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rename debian/{libmblock.install => libmblock0.install} (100%)
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create mode 100755 gr-noaa/apps/usrp_rx_hrpt_nogui.py
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fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso} (100%)
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create mode 100644 usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.ngc
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copy usrp2/fpga/coregen/{fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso =>
fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso} (100%)
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