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[Commit-gnuradio] gnuradio.git at gnuradio.org branch, master, updated.
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[Commit-gnuradio] gnuradio.git at gnuradio.org branch, master, updated. bf76534044a1bbcc665f0400a53d1070cae8caf0 |
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Thu, 1 Oct 2009 13:08:33 -0600 (MDT) |
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- Log -----------------------------------------------------------------
commit bf76534044a1bbcc665f0400a53d1070cae8caf0
Merge: e5b76a1b9239f560b3aad21d56a7b417f3c8b0b5
4743bf771fed8405b08194d8c7fb72bf8110eab3
Author: Johnathan Corgan <address@hidden>
Date: Thu Oct 1 11:00:25 2009 -0700
Merge branch 'new_eth' of http://gnuradio.org/git/matt into master
* 'new_eth' of http://gnuradio.org/git/matt: (42 commits)
Fix warnings, mostly from implicitly defined wires or unspecified widths
fullchip sim now compiles again, after moving eth and models over to new
simple_gemac
remove unused opencores
remove debugging code
no idea where this came from, it shouldn't be here
Copied wb_1master back from quad radio
Remove old mac. Good riddance.
remove unused port
More xilinx fifos, more clean up of our fifos
might as well use a cascade fifo to help timing and give a little more
capacity
fix a typo which caused tx glitches
Untested fixes for getting serdes onto the new fifo system. Compiles, at
least
Implement Eth flow control using pause frames
parameterized fifo sizes, some reformatting
remove unused old style fifo
allow control of whether or not to honor flow control, adds some debug
lines
debug the rx side
no longer used, replaced by newfifo version
remove special last_line adjustment from ethernet port
Firmware now inserts mac source address value in each frame.
...
commit 4743bf771fed8405b08194d8c7fb72bf8110eab3
Author: Matt Ettus <address@hidden>
Date: Thu Oct 1 01:02:25 2009 -0700
Fix warnings, mostly from implicitly defined wires or unspecified widths
commit 21e931766545ff93dda5ef1b72dd03f3786967ab
Author: Matt Ettus <address@hidden>
Date: Thu Oct 1 00:21:24 2009 -0700
fullchip sim now compiles again, after moving eth and models over to new
simple_gemac
commit 413d26237e93b8b019c719ed186e228a8eeb41b8
Author: Matt Ettus <address@hidden>
Date: Thu Oct 1 00:06:11 2009 -0700
remove unused opencores
commit 147de5cd3e57a07914673a31fb73a35ebf18b3a2
Author: Matt Ettus <address@hidden>
Date: Wed Sep 30 19:55:05 2009 -0700
remove debugging code
commit d37030e27d9e9c922b432c04252b1636f5160c3c
Merge: 4dfa2ad7deab0a89784906b377dbea271ba08118
016b2fb7b8da8bf10e7ee9e6465adb8d317c0a43
Author: Matt Ettus <address@hidden>
Date: Wed Sep 30 19:12:23 2009 -0700
Merge branch 'new_wb_intercon' into new_eth
Functionality should not change at all
Conflicts:
usrp2/fpga/top/u2_core/u2_core.v
commit 4dfa2ad7deab0a89784906b377dbea271ba08118
Merge: 1e3521c90f63e70e8ec4dc97574bc8b46366fc1e
c88f64ad42a8473a1749275c0e579284b20eb283
Author: Matt Ettus <address@hidden>
Date: Wed Sep 30 18:59:54 2009 -0700
Merge branch 'master' into new_eth
commit 1e3521c90f63e70e8ec4dc97574bc8b46366fc1e
Author: Matt Ettus <address@hidden>
Date: Wed Sep 30 18:37:47 2009 -0700
no idea where this came from, it shouldn't be here
commit 016b2fb7b8da8bf10e7ee9e6465adb8d317c0a43
Author: Matt Ettus <address@hidden>
Date: Wed Sep 30 17:35:14 2009 -0700
Copied wb_1master back from quad radio
more sane config options, should be exactly the same memory map
commit 5c46578ba936de57e80594540804c964aa408f73
Merge: 35ada01aa8ae838d6d75bf063725218fa7e18f5f
16474a0adb44dc81a8338a9c4a9a6dcab6f6328f
Author: Matt Ettus <address@hidden>
Date: Thu Sep 24 22:34:06 2009 -0700
Merge commit 'origin' into new_eth
Conflicts:
.gitignore
commit 35ada01aa8ae838d6d75bf063725218fa7e18f5f
Merge: ab47612cf0b6f2226d192fbc9db80c5b225a4f2d
8bb9923f542caae6eca47d42c35b1c00816e61f0
Author: Matt Ettus <address@hidden>
Date: Sun Sep 20 17:30:27 2009 -0700
Merge branch 'serdes_newfifo' into new_eth
commit ab47612cf0b6f2226d192fbc9db80c5b225a4f2d
Author: Matt Ettus <address@hidden>
Date: Thu Sep 10 23:11:44 2009 -0700
Remove old mac. Good riddance.
commit 1e585a79df197653b752427b4372895e12afc2d4
Author: Matt Ettus <address@hidden>
Date: Thu Sep 10 21:53:32 2009 -0700
remove unused port
commit d657d1baa99af56f8a4c0ed4b3bc6464313b1773
Author: Matt Ettus <address@hidden>
Date: Thu Sep 10 21:52:06 2009 -0700
More xilinx fifos, more clean up of our fifos
commit 4623a334d042b0f982ead3dcc7ea63015a39ff72
Author: Matt Ettus <address@hidden>
Date: Thu Sep 10 11:40:18 2009 -0700
might as well use a cascade fifo to help timing and give a little more
capacity
commit db03fafeec9d360a9837303befcc2dbcce57a06b
Author: Matt Ettus <address@hidden>
Date: Sat Sep 5 13:38:13 2009 -0700
fix a typo which caused tx glitches
commit 8bb9923f542caae6eca47d42c35b1c00816e61f0
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 22:33:30 2009 -0700
Untested fixes for getting serdes onto the new fifo system. Compiles, at
least
commit 9e05f0770b92f9c85f09e3629f875011e8f1ac24
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 22:23:27 2009 -0700
Implement Eth flow control using pause frames
Not fully tested, but it seems to work without frame errors, sequence
number errors or ethernet overruns. Still of course will get tx underruns
on a slow machine, and the transmitted signal has some issues though.
commit 7ab7f93a1d7eecc873155026ea06d70d2d2b2846
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 22:20:19 2009 -0700
parameterized fifo sizes, some reformatting
commit 00da83704ec4a1c9eca3eb7e90f6a8a762799217
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 22:14:21 2009 -0700
remove unused old style fifo
commit c452801ce73a8467e1d5ee14f7f497e08254ef6d
Merge: 1048666fba8abf654c9abba84a849ba2d6885221
02c74ee9f1c07e20097f6cfc2e7426be3a7ad06c
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 16:47:43 2009 -0700
Merge branch 'new_eth' of http://gnuradio.org/git/eb into new_eth
commit 1048666fba8abf654c9abba84a849ba2d6885221
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 16:43:11 2009 -0700
allow control of whether or not to honor flow control, adds some debug lines
commit 1392a442651b9528537ca722df76090bbf4de0d9
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 16:37:29 2009 -0700
debug the rx side
commit 2d6ac5853644d805390df01367499922eca81368
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 16:33:00 2009 -0700
no longer used, replaced by newfifo version
commit 02c74ee9f1c07e20097f6cfc2e7426be3a7ad06c
Merge: a1d9c0b4de66eadfdd3f6a217af80f7eb4e22772
62adc385b1ea87fa924dfd15a60706bdf6be18e2
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 15:58:33 2009 -0700
Merge branch 'new_eth' of http://gnuradio.org/git/matt into new_eth
* 'new_eth' of http://gnuradio.org/git/matt:
commit 62adc385b1ea87fa924dfd15a60706bdf6be18e2
Merge: 802ab4104ca9bae8b21fe9618709d5a3d8cfd77f
6528672f2db205b6127f05ad7c7b9da66661b498
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 15:53:46 2009 -0700
Merge branch 'new_eth' of http://gnuradio.org/git/eb into new_eth
commit a1d9c0b4de66eadfdd3f6a217af80f7eb4e22772
Merge: 6528672f2db205b6127f05ad7c7b9da66661b498
7cb806f71a3bcc52c3c2e5688a9b6b48e3401615
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 15:51:52 2009 -0700
Merge branch 'new_eth' of http://gnuradio.org/git/matt into new_eth
* 'new_eth' of http://gnuradio.org/git/matt:
properly set the address filter
stop sending short ethernet command packets.
Fix problem with commands timing out (specifically stop_rx_streaming)
Fix race condition that caused commands such as stop_rx_streaming to fail.
Fixing a line in the clock recovery algorithm. This works with a bit
larger error than there proably should be.
Better fix for broken AC_PROG_F77 macro
Fix Python header check failure due to invalid cached state
waterfall and fft use a common autoscale function
Fix so that the waterfall texture is initialized with a buffer of the
same size.
Modifications to usrp2 source and sink so that set center freq is called
afer set lo offset.
Modifications to the usrp blocks and wrapper so that the lo offset is set
with the lo frequency.
Removed subversion related configuration info.
Expand frequency ranges to match hardware capability.
Modified log power fft block so ref scale is peak to peak.
Adding clock sync algorithm using PFB. This works, but needs a bit more
work.
commit 6528672f2db205b6127f05ad7c7b9da66661b498
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 15:47:32 2009 -0700
remove special last_line adjustment from ethernet port
commit 802ab4104ca9bae8b21fe9618709d5a3d8cfd77f
Merge: 7cb806f71a3bcc52c3c2e5688a9b6b48e3401615
49a17dca1ee9cf7c0fd02b6baf83814a68c4e5e8
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 15:44:47 2009 -0700
Merge branch 'new_eth' of http://gnuradio.org/git/eb into new_eth
commit 49a17dca1ee9cf7c0fd02b6baf83814a68c4e5e8
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 15:35:01 2009 -0700
Firmware now inserts mac source address value in each frame.
The old mac used to do this automatically.
commit 7cb806f71a3bcc52c3c2e5688a9b6b48e3401615
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 15:31:26 2009 -0700
properly set the address filter
commit 9a100f391e52106ca872dd5df8287273eea64b0c
Merge: f945bc6d3188d15c767706a2edbbda950a101c61
5965a434d0923738d49334eb5f3d74a259e7b431
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 15:07:06 2009 -0700
Merge branch 'new_eth' of http://gnuradio.org/git/matt into new_eth
* 'new_eth' of http://gnuradio.org/git/matt:
seems to build a decent fpga, but still some issues with a full
connection.
commit e103e18f8b8111cd07edc2bb0294aa58a426e371
Merge: 5965a434d0923738d49334eb5f3d74a259e7b431
20006003431d7260b04964eb684b1746ffb0a85f
Author: Matt Ettus <address@hidden>
Date: Fri Sep 4 10:29:00 2009 -0700
Merge branch 'master' into new_eth
commit f945bc6d3188d15c767706a2edbbda950a101c61
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 03:48:15 2009 -0700
stop sending short ethernet command packets.
commit 96b6c7b97e3fb9188bc6906153254dc36cedc2cb
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 03:32:32 2009 -0700
Fix problem with commands timing out (specifically stop_rx_streaming)
After fixing the race, this change uses Tom's idea to stop enqueuing
data when trying to stop, and adds a new flush_rx_samples method
to drop any samples that may have already been accumulated.
I ran Tom's test case 500 times with 0 failures ;-)
commit 5d040bc94b40cab5420303f959695d89fe83e031
Author: Eric Blossom <address@hidden>
Date: Fri Sep 4 01:51:29 2009 -0700
Fix race condition that caused commands such as stop_rx_streaming to fail.
This fixes the bulk of the problem. Next step is to drop data packets
while waiting for the reply.
commit 5965a434d0923738d49334eb5f3d74a259e7b431
Author: Matt Ettus <address@hidden>
Date: Thu Sep 3 21:39:48 2009 -0700
seems to build a decent fpga, but still some issues with a full connection.
commit 42b10fee5167354a2927c2874cec46fc0d71a245
Author: Eric Blossom <address@hidden>
Date: Thu Sep 3 16:12:40 2009 -0700
removed hard-coded link_is_up = true;
commit 43dec22f22e9c47b4f908675ac880a05377993fa
Author: Matt Ettus <address@hidden>
Date: Thu Sep 3 14:13:44 2009 -0700
MAC transmit seems to work now. The root cause of the problem was
accidentally using the rx_clk in one stage of the fifos on the tx side.
commit 77df49ed5d2cc99ea75f3e72e9387869b35ac603
Author: Matt Ettus <address@hidden>
Date: Thu Sep 3 10:41:26 2009 -0700
set device to xc3s2000. Shouldn't make any differences.
commit 19094db4bd7ba13bd80e4baa9ecdf1e7d2ac547d
Author: Matt Ettus <address@hidden>
Date: Thu Sep 3 10:39:37 2009 -0700
misc ignores
commit 4fff2505ffd0779126d8a2036d63f1fcc53bdb52
Author: Matt Ettus <address@hidden>
Date: Thu Sep 3 10:37:35 2009 -0700
made a new block ram based fifo, 64 (65) elements long, all fifos now have
"enhanced level logic" for accurate fullness. Maybe this will help...
commit 77dc1a9ba4ce9940d974edef8711d3eba85c0608
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 21:27:18 2009 -0700
bring the testbench files up to date
commit 3113a7bbf56462cde4a6be4a15d5f8296e37ae8a
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 17:56:26 2009 -0700
major cleanup of 2 clock fifos
commit 80dbcc615f408bfdb23a269a54882adae0ab405b
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 17:28:57 2009 -0700
cleaning up the new fifos
commit a5b340fa42de5c6cc087fd4f258f9f50254a7a8f
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 17:23:12 2009 -0700
cascadefifo.v wasn't used, only the double cascade version. fifo_2clock.v
and fifo_2clock.v are empty
commit 95e6a1167b1de5d23053fda76678df297e43eedf
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 17:09:16 2009 -0700
never used, not needed
commit 72a570279574d717325a3d65a6b435ba4eb7a82c
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 17:05:45 2009 -0700
ignore .o files
commit 78588fb1608eaec95827da07c0bebee8e0fab3b6
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 17:04:53 2009 -0700
debug pins, cleaned ignores
commit f34764905524897c57fa871f04110903dd9c468f
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 17:01:28 2009 -0700
sort out active-low lines on locallink fifos, added debug pins
commit ac9859282e821854badf99addea58c14aad2bcd4
Author: Matt Ettus <address@hidden>
Date: Wed Sep 2 16:46:06 2009 -0700
Removed these files completely, they were for the old style of fifos
commit 2846230c1296b78aa003e4b02a21bcdba10310c1
Author: Matt Ettus <address@hidden>
Date: Tue Sep 1 23:19:15 2009 -0700
fixed addressing of registers, and added write enables to those that were
missing. MDIO seems ok.
commit 7e013c464ce04a7dc559a3f2798559c0716ccae8
Author: Eric Blossom <address@hidden>
Date: Tue Sep 1 18:43:07 2009 -0700
tell s/w link is up. additional debugging output
commit 7eea883c377f64862a4d83f1b33a83fdf3cfc392
Author: Johnathan Corgan <address@hidden>
Date: Mon Aug 31 12:08:30 2009 -0700
Merged SVN matt/new_eth r10782:11633 into new_eth
* svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth
-r10782:11633
* Patch applied with no conflicts or fuzz.
-----------------------------------------------------------------------
Summary of changes:
usrp2/firmware/apps/app_common_v2.c | 3 +-
usrp2/firmware/apps/app_passthru_v2.c | 1 +
usrp2/firmware/apps/factory_test.c | 1 +
usrp2/firmware/apps/gen_eth_packets.c | 14 +-
usrp2/firmware/apps/gen_pause_frames.c | 4 +-
usrp2/firmware/apps/mimo_app_common_v2.c | 1 +
usrp2/firmware/apps/mimo_tx.c | 1 +
usrp2/firmware/apps/mimo_tx_slave.c | 1 +
usrp2/firmware/apps/rcv_eth_packets.c | 2 +-
usrp2/firmware/apps/serdes_txrx.c | 1 +
usrp2/firmware/apps/tx_standalone.c | 1 +
usrp2/firmware/apps/txrx.c | 4 +-
usrp2/firmware/lib/.gitignore | 1 +
usrp2/firmware/lib/dbsm.c | 3 +-
usrp2/firmware/lib/eth_mac.c | 55 +-
usrp2/firmware/lib/eth_mac_regs.h | 82 +-
usrp2/firmware/lib/ethernet.c | 24 +-
usrp2/fpga/.gitignore | 2 +
usrp2/fpga/control_lib/buffer_int.v | 251 -
usrp2/fpga/control_lib/buffer_int_tb.v | 447 -
usrp2/fpga/control_lib/buffer_pool.v | 323 -
usrp2/fpga/control_lib/buffer_pool_tb.v | 50 -
usrp2/fpga/control_lib/cascadefifo.v | 50 -
usrp2/fpga/control_lib/cascadefifo2.v | 56 -
usrp2/fpga/control_lib/fifo_2clock.v | 66 -
usrp2/fpga/control_lib/fifo_2clock_casc.v | 31 -
usrp2/fpga/control_lib/fifo_reader.v | 28 -
usrp2/fpga/control_lib/fifo_tb.v | 8 +-
usrp2/fpga/control_lib/fifo_writer.v | 31 -
usrp2/fpga/control_lib/giantfifo.v | 209 -
usrp2/fpga/control_lib/giantfifo_tb.v | 173 -
usrp2/fpga/control_lib/newfifo/.gitignore | 1 +
usrp2/fpga/control_lib/newfifo/fifo18_to_ll8.v | 58 -
usrp2/fpga/control_lib/newfifo/fifo36_to_ll8.v | 2 +-
usrp2/fpga/control_lib/newfifo/fifo_2clock.v | 61 +-
usrp2/fpga/control_lib/newfifo/fifo_2clock_casc.v | 31 -
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usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.ngc | 3 +
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usrp2/fpga/opencores/uart16550/doc/UART_spec.pdf | Bin 163447 -> 0 bytes
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.../opencores/uart16550/rtl/verilog/uart_regs.v | 903 -
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usrp2/fpga/sdr_lib/rx_control.v | 77 +-
usrp2/fpga/sdr_lib/tx_control.v | 72 +-
usrp2/fpga/serdes/serdes.v | 16 +-
usrp2/fpga/serdes/serdes_rx.v | 111 +-
usrp2/fpga/serdes/serdes_tx.v | 51 +-
usrp2/fpga/simple_gemac/.gitignore | 3 +-
usrp2/fpga/simple_gemac/delay_line.v | 2 +-
usrp2/fpga/simple_gemac/eth_tasks_f36.v | 92 +
usrp2/fpga/simple_gemac/flow_ctrl_rx.v | 106 +-
usrp2/fpga/simple_gemac/ll8_shortfifo.v | 13 -
usrp2/fpga/simple_gemac/rxmac_to_ll8.v | 14 +-
usrp2/fpga/simple_gemac/simple_gemac.v | 9 +-
usrp2/fpga/simple_gemac/simple_gemac_rx.v | 50 +-
usrp2/fpga/simple_gemac/simple_gemac_tx.v | 16 +-
usrp2/fpga/simple_gemac/simple_gemac_wb.v | 35 +-
usrp2/fpga/simple_gemac/simple_gemac_wrapper.build | 1 +
usrp2/fpga/simple_gemac/simple_gemac_wrapper.v | 159 +-
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usrp2/fpga/simple_gemac/simple_gemac_wrapper_tb.v | 140 +-
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usrp2/fpga/top/single_u2_sim/single_u2_sim.v | 2 +-
usrp2/fpga/top/u2_core/.gitignore | 1 +
usrp2/fpga/top/u2_core/u2_core.v | 298 +-
usrp2/fpga/top/u2_rev3/Makefile | 67 +-
545 files changed, 2700 insertions(+), 90245 deletions(-)
create mode 100644 usrp2/fpga/.gitignore
delete mode 100644 usrp2/fpga/control_lib/buffer_int.v
delete mode 100644 usrp2/fpga/control_lib/buffer_int_tb.v
delete mode 100644 usrp2/fpga/control_lib/buffer_pool.v
delete mode 100644 usrp2/fpga/control_lib/buffer_pool_tb.v
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delete mode 100644 usrp2/fpga/control_lib/cascadefifo2.v
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delete mode 100644 usrp2/fpga/control_lib/fifo_reader.v
delete mode 100644 usrp2/fpga/control_lib/fifo_writer.v
delete mode 100644 usrp2/fpga/control_lib/giantfifo.v
delete mode 100644 usrp2/fpga/control_lib/giantfifo_tb.v
create mode 100644 usrp2/fpga/control_lib/newfifo/.gitignore
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo18_to_ll8.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo_2clock_casc.v
create mode 100644 usrp2/fpga/control_lib/newfifo/fifo_2clock_cascade.v
delete mode 100644 usrp2/fpga/control_lib/newfifo/fifo_new_tb.v
copy usrp2/fpga/{simple_gemac => control_lib/newfifo}/ll8_shortfifo.v (100%)
create mode 100644 usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.ngc
create mode 100644 usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.v
create mode 100644 usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.veo
create mode 100644 usrp2/fpga/coregen/fifo_xlnx_16x19_2clk.xco
copy usrp2/fpga/coregen/{fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso =>
fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso} (100%)
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create mode 100644 usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_flist.txt
create mode 100644 usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_readme.txt
create mode 100644 usrp2/fpga/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl
create mode 100644 usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.ngc
create mode 100644 usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.v
create mode 100644 usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.veo
create mode 100644 usrp2/fpga/coregen/fifo_xlnx_64x36_2clk.xco
copy usrp2/fpga/coregen/{fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso =>
fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso} (100%)
create mode 100644
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create mode 100644 usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_readme.txt
create mode 100644 usrp2/fpga/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl
delete mode 100644 usrp2/fpga/eth/bench/verilog/.gitignore
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delete mode 100644 usrp2/fpga/eth/bench/verilog/User_int_sim.v
delete mode 100644 usrp2/fpga/eth/bench/verilog/error.scr
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delete mode 100644 usrp2/fpga/eth/bench/verilog/isim.bat
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delete mode 100644 usrp2/fpga/eth/demo/verilog/tb_demo.v
delete mode 100644 usrp2/fpga/eth/header_ram.v
delete mode 100644 usrp2/fpga/eth/mac_rxfifo_int.v
delete mode 100644 usrp2/fpga/eth/mac_txfifo_int.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/Clk_ctrl.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/MAC_rx.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/MAC_rx/Broadcast_filter.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/MAC_rx/CRC_chk.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v
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delete mode 100644 usrp2/fpga/eth/rtl/verilog/MAC_tx/CRC_gen.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/MAC_tx/Random_gen.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/Phy_int.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/RMON.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/RMON/RMON_addr_gen.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/RMON/RMON_ctrl.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/Reg_int.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_div2.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/TECH/eth_clk_switch.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/TECH/xilinx/BUFGMUX.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/elastic_buffer.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/elastic_buffer_tb.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/eth_miim.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/flow_ctrl_tx.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/header.vh
delete mode 100644 usrp2/fpga/eth/rtl/verilog/miim/eth_clockgen.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/miim/eth_outputcontrol.v
delete mode 100644 usrp2/fpga/eth/rtl/verilog/miim/eth_shiftreg.v
delete mode 100644 usrp2/fpga/eth/rx_prot_engine.v
delete mode 100644 usrp2/fpga/eth/tx_prot_engine.v
rename usrp2/fpga/{eth/bench/verilog => models}/miim_model.v (100%)
create mode 100644 usrp2/fpga/models/phy_sim.v
rename usrp2/fpga/{eth/bench/verilog => models}/xlnx_glbl.v (100%)
delete mode 100644 usrp2/fpga/opencores/ethernet_tri_mode/.gitignore
delete mode 100644 usrp2/fpga/opencores/ethernet_tri_mode/CVS/Entries
delete mode 100644 usrp2/fpga/opencores/ethernet_tri_mode/CVS/Repository
delete mode 100644 usrp2/fpga/opencores/ethernet_tri_mode/CVS/Root
delete mode 100644 usrp2/fpga/opencores/ethernet_tri_mode/CVS/Template
delete mode 100644 usrp2/fpga/opencores/ethernet_tri_mode/bench/CVS/Entries
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