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[Commit-gnuradio] r11624 - gnuradio/trunk/usrp2/fpga/top/u2plus
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r11624 - gnuradio/trunk/usrp2/fpga/top/u2plus |
|
Date: |
Sun, 30 Aug 2009 22:05:00 -0600 (MDT) |
Author: matt
Date: 2009-08-30 22:05:00 -0600 (Sun, 30 Aug 2009)
New Revision: 11624
Added:
gnuradio/trunk/usrp2/fpga/top/u2plus/Makefile
Modified:
gnuradio/trunk/usrp2/fpga/top/u2plus/
gnuradio/trunk/usrp2/fpga/top/u2plus/u2plus.ucf
gnuradio/trunk/usrp2/fpga/top/u2plus/u2plus.v
Log:
snapshot of u2plus progress
Property changes on: gnuradio/trunk/usrp2/fpga/top/u2plus
___________________________________________________________________
Added: svn:ignore
+ build
Added: gnuradio/trunk/usrp2/fpga/top/u2plus/Makefile
===================================================================
--- gnuradio/trunk/usrp2/fpga/top/u2plus/Makefile
(rev 0)
+++ gnuradio/trunk/usrp2/fpga/top/u2plus/Makefile 2009-08-31 04:05:00 UTC
(rev 11624)
@@ -0,0 +1,248 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u2plus
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package fg676 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/buffer_int.v \
+control_lib/buffer_pool.v \
+control_lib/cascadefifo2.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/fifo_2clock.v \
+control_lib/fifo_2clock_casc.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/longfifo.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+eth/mac_rxfifo_int.v \
+eth/mac_txfifo_int.v \
+eth/rtl/verilog/Clk_ctrl.v \
+eth/rtl/verilog/MAC_rx.v \
+eth/rtl/verilog/MAC_rx/Broadcast_filter.v \
+eth/rtl/verilog/MAC_rx/CRC_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \
+eth/rtl/verilog/MAC_top.v \
+eth/rtl/verilog/MAC_tx.v \
+eth/rtl/verilog/MAC_tx/CRC_gen.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \
+eth/rtl/verilog/MAC_tx/Random_gen.v \
+eth/rtl/verilog/Phy_int.v \
+eth/rtl/verilog/RMON.v \
+eth/rtl/verilog/RMON/RMON_addr_gen.v \
+eth/rtl/verilog/RMON/RMON_ctrl.v \
+eth/rtl/verilog/Reg_int.v \
+eth/rtl/verilog/eth_miim.v \
+eth/rtl/verilog/flow_ctrl_rx.v \
+eth/rtl/verilog/flow_ctrl_tx.v \
+eth/rtl/verilog/miim/eth_clockgen.v \
+eth/rtl/verilog/miim/eth_outputcontrol.v \
+eth/rtl/verilog/miim/eth_shiftreg.v \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/u2plus/u2plus.ucf \
+top/u2plus/u2plus.v
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+#"Number of Clock Buffers" 6 \
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+ @echo make proj, check, synth, bin, or clean
+
+proj:
+ PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)
+
+check:
+ PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)
+
+synth:
+ PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)
+
+bin:
+ PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)
+
+clean:
+ rm -rf $(BUILD_DIR)
+
+
Modified: gnuradio/trunk/usrp2/fpga/top/u2plus/u2plus.ucf
===================================================================
--- gnuradio/trunk/usrp2/fpga/top/u2plus/u2plus.ucf 2009-08-31 03:12:37 UTC
(rev 11623)
+++ gnuradio/trunk/usrp2/fpga/top/u2plus/u2plus.ucf 2009-08-31 04:05:00 UTC
(rev 11624)
@@ -7,13 +7,13 @@
NET "io_rx<12>" LOC = "AC3" ;
NET "io_rx<11>" LOC = "W7" ;
NET "io_rx<10>" LOC = "W6" ;
-NET "io_rx<09>" LOC = "U9" ;
-NET "io_rx<08>" LOC = "V8" ;
-NET "io_rx<07>" LOC = "AB1" ;
-NET "io_rx<06>" LOC = "AC1" ;
-NET "io_rx<05>" LOC = "V7" ;
-NET "io_rx<04>" LOC = "V6" ;
-NET "io_rx<03>" LOC = "Y5" ;
+NET "io_rx<9>" LOC = "U9" ;
+NET "io_rx<8>" LOC = "V8" ;
+NET "io_rx<7>" LOC = "AB1" ;
+NET "io_rx<6>" LOC = "AC1" ;
+NET "io_rx<5>" LOC = "V7" ;
+NET "io_rx<4>" LOC = "V6" ;
+NET "io_rx<3>" LOC = "Y5" ;
NET "ADCB_2_3_p" LOC = "U7" ;
NET "ADCB_2_3_n" LOC = "U8" ;
NET "ADCB_0_1_p" LOC = "AA2" ;
@@ -32,54 +32,54 @@
NET "ADCA_2_3_n" LOC = "V2" ;
NET "ADCA_0_1_p" LOC = "R8" ;
NET "ADCA_0_1_n" LOC = "R7" ;
-NET "TX00_A" LOC = "P8" ;
-NET "TX01_A" LOC = "P9" ;
-NET "TX02_A" LOC = "R5" ;
-NET "TX03_A" LOC = "R6" ;
-NET "TX04_A" LOC = "P7" ;
-NET "TX05_A" LOC = "P6" ;
-NET "TX06_A" LOC = "T3" ;
-NET "TX07_A" LOC = "T4" ;
-NET "TX08_A" LOC = "R3" ;
-NET "TX09_A" LOC = "R4" ;
-NET "TX10_A" LOC = "R2" ;
-NET "TX11_A" LOC = "N1" ;
-NET "TX12_A" LOC = "N2" ;
-NET "TX13_A" LOC = "N5" ;
-NET "TX14_A" LOC = "N4" ;
-NET "TX15_A" LOC = "M2" ;
-NET "TX00_B" LOC = "M5" ;
-NET "TX01_B" LOC = "M6" ;
-NET "TX02_B" LOC = "M4" ;
-NET "TX03_B" LOC = "M3" ;
-NET "TX04_B" LOC = "M8" ;
-NET "TX05_B" LOC = "M7" ;
-NET "TX06_B" LOC = "L4" ;
-NET "TX07_B" LOC = "L3" ;
-NET "TX08_B" LOC = "K3" ;
-NET "TX09_B" LOC = "K2" ;
-NET "TX10_B" LOC = "K5" ;
-NET "TX11_B" LOC = "K4" ;
-NET "TX12_B" LOC = "M10" ;
-NET "TX13_B" LOC = "M9" ;
-NET "TX14_B" LOC = "J5" ;
-NET "TX15_B" LOC = "J4" ;
+NET "TXA<0>" LOC = "P8" ;
+NET "TXA<1>" LOC = "P9" ;
+NET "TXA<2>" LOC = "R5" ;
+NET "TXA<3>" LOC = "R6" ;
+NET "TXA<4>" LOC = "P7" ;
+NET "TXA<5>" LOC = "P6" ;
+NET "TXA<6>" LOC = "T3" ;
+NET "TXA<7>" LOC = "T4" ;
+NET "TXA<8>" LOC = "R3" ;
+NET "TXA<9>" LOC = "R4" ;
+NET "TXA<10>" LOC = "R2" ;
+NET "TXA<11>" LOC = "N1" ;
+NET "TXA<12>" LOC = "N2" ;
+NET "TXA<13>" LOC = "N5" ;
+NET "TXA<14>" LOC = "N4" ;
+NET "TXA<15>" LOC = "M2" ;
+NET "TXB<0>" LOC = "M5" ;
+NET "TXB<1>" LOC = "M6" ;
+NET "TXB<2>" LOC = "M4" ;
+NET "TXB<3>" LOC = "M3" ;
+NET "TXB<4>" LOC = "M8" ;
+NET "TXB<5>" LOC = "M7" ;
+NET "TXB<6>" LOC = "L4" ;
+NET "TXB<7>" LOC = "L3" ;
+NET "TXB<8>" LOC = "K3" ;
+NET "TXB<9>" LOC = "K2" ;
+NET "TXB<10>" LOC = "K5" ;
+NET "TXB<11>" LOC = "K4" ;
+NET "TXB<12>" LOC = "M10" ;
+NET "TXB<13>" LOC = "M9" ;
+NET "TXB<14>" LOC = "J5" ;
+NET "TXB<15>" LOC = "J4" ;
NET "io_tx<15>" LOC = "K6" ;
NET "io_tx<14>" LOC = "L7" ;
NET "io_tx<13>" LOC = "H2" ;
NET "io_tx<12>" LOC = "H1" ;
NET "io_tx<11>" LOC = "L10" ;
NET "io_tx<10>" LOC = "L9" ;
-NET "io_tx<09>" LOC = "G3" ;
-NET "io_tx<08>" LOC = "F3" ;
-NET "io_tx<07>" LOC = "K7" ;
-NET "io_tx<06>" LOC = "J6" ;
-NET "io_tx<05>" LOC = "E1" ;
-NET "io_tx<04>" LOC = "F2" ;
-NET "io_tx<03>" LOC = "J7" ;
-NET "io_tx<02>" LOC = "H6" ;
-NET "io_tx<01>" LOC = "F5" ;
-NET "io_tx<00>" LOC = "G4" ;
+NET "io_tx<9>" LOC = "G3" ;
+NET "io_tx<8>" LOC = "F3" ;
+NET "io_tx<7>" LOC = "K7" ;
+NET "io_tx<6>" LOC = "J6" ;
+NET "io_tx<5>" LOC = "E1" ;
+NET "io_tx<4>" LOC = "F2" ;
+NET "io_tx<3>" LOC = "J7" ;
+NET "io_tx<2>" LOC = "H6" ;
+NET "io_tx<1>" LOC = "F5" ;
+NET "io_tx<0>" LOC = "G4" ;
NET "MOSI_RX_ADC" LOC = "E3" ;
NET "SCLK_RX_ADC" LOC = "F4" ;
NET "SEN_RX_ADC" LOC = "D3" ;
@@ -107,9 +107,9 @@
NET "MISO_TX_DB" LOC = "AA5" ;
NET "MISO_DAC" LOC = "Y3" ;
NET "MISO_TX_ADC" LOC = "G1" ;
-NET "io_rx<02>" LOC = "R10" ;
-NET "io_rx<01>" LOC = "R1" ;
-NET "io_rx<00>" LOC = "M1" ;
+NET "io_rx<2>" LOC = "R10" ;
+NET "io_rx<1>" LOC = "R1" ;
+NET "io_rx<0>" LOC = "M1" ;
NET "exp_user_out_p" LOC = "AF14" ;
NET "exp_user_out_n" LOC = "AE14" ;
NET "exp_time_out_p" LOC = "Y14" ;
@@ -135,16 +135,16 @@
NET "TXD3" LOC = "AD20" ;
NET "TXD2" LOC = "AC20" ;
NET "TXD1" LOC = "AD19" ;
-NET "debug<00>" LOC = "AC19" ;
-NET "debug<01>" LOC = "AF20" ;
-NET "debug<02>" LOC = "AE20" ;
-NET "debug<03>" LOC = "AC16" ;
-NET "debug<04>" LOC = "AB16" ;
-NET "debug<05>" LOC = "AF19" ;
-NET "debug<06>" LOC = "AE19" ;
-NET "debug<07>" LOC = "V15" ;
-NET "debug<08>" LOC = "U15" ;
-NET "debug<09>" LOC = "AE17" ;
+NET "debug<0>" LOC = "AC19" ;
+NET "debug<1>" LOC = "AF20" ;
+NET "debug<2>" LOC = "AE20" ;
+NET "debug<3>" LOC = "AC16" ;
+NET "debug<4>" LOC = "AB16" ;
+NET "debug<5>" LOC = "AF19" ;
+NET "debug<6>" LOC = "AE19" ;
+NET "debug<7>" LOC = "V15" ;
+NET "debug<8>" LOC = "U15" ;
+NET "debug<9>" LOC = "AE17" ;
NET "debug<10>" LOC = "AD17" ;
NET "debug<11>" LOC = "V14" ;
NET "debug<12>" LOC = "W15" ;
@@ -193,25 +193,25 @@
NET "GMII_TX_CLK" LOC = "P25" ;
NET "GMII_RX_CLK" LOC = "P21" ;
NET "ETH_LED" LOC = "H20" ;
-NET "GMII_TXD7" LOC = "G21" ;
-NET "GMII_TXD6" LOC = "C26" ;
-NET "GMII_TXD5" LOC = "C25" ;
-NET "GMII_TXD4" LOC = "J21" ;
-NET "GMII_TXD3" LOC = "H21" ;
-NET "GMII_TXD2" LOC = "D25" ;
-NET "GMII_TXD1" LOC = "D24" ;
-NET "GMII_TXD0" LOC = "E26" ;
+NET "GMII_TXD<7>" LOC = "G21" ;
+NET "GMII_TXD<6>" LOC = "C26" ;
+NET "GMII_TXD<5>" LOC = "C25" ;
+NET "GMII_TXD<4>" LOC = "J21" ;
+NET "GMII_TXD<3>" LOC = "H21" ;
+NET "GMII_TXD<2>" LOC = "D25" ;
+NET "GMII_TXD<1>" LOC = "D24" ;
+NET "GMII_TXD<0>" LOC = "E26" ;
NET "GMII_TX_EN" LOC = "D26" ;
NET "GMII_TX_ER" LOC = "J19" ;
NET "GMII_GTX_CLK" LOC = "J20" ;
-NET "GMII_RXD7" LOC = "G22" ;
-NET "GMII_RXD6" LOC = "K19" ;
-NET "GMII_RXD5" LOC = "K18" ;
-NET "GMII_RXD4" LOC = "E24" ;
-NET "GMII_RXD3" LOC = "F23" ;
-NET "GMII_RXD2" LOC = "L18" ;
-NET "GMII_RXD1" LOC = "L17" ;
-NET "GMII_RXD0" LOC = "F25" ;
+NET "GMII_RXD<7>" LOC = "G22" ;
+NET "GMII_RXD<6>" LOC = "K19" ;
+NET "GMII_RXD<5>" LOC = "K18" ;
+NET "GMII_RXD<4>" LOC = "E24" ;
+NET "GMII_RXD<3>" LOC = "F23" ;
+NET "GMII_RXD<2>" LOC = "L18" ;
+NET "GMII_RXD<1>" LOC = "L17" ;
+NET "GMII_RXD<0>" LOC = "F25" ;
NET "GMII_RX_DV" LOC = "F24" ;
NET "GMII_RX_ER" LOC = "L20" ;
NET "GMII_CRS" LOC = "K20" ;
@@ -219,7 +219,7 @@
NET "PHY_INTn" LOC = "L22" ;
NET "MDIO" LOC = "K21" ;
NET "MDC" LOC = "J23" ;
-NET "PHY_RESET" LOC = "J22" ;
+NET "PHY_RESETn" LOC = "J22" ;
NET "exp_time_in_p" LOC = "N18" ;
NET "exp_time_in_n" LOC = "N17" ;
NET "exp_user_in_p" LOC = "L24" ;
@@ -233,16 +233,16 @@
NET "ser_t<12>" LOC = "V25" ;
NET "ser_t<11>" LOC = "W23" ;
NET "ser_t<10>" LOC = "V22" ;
-NET "ser_t<09>" LOC = "T18" ;
-NET "ser_t<08>" LOC = "T17" ;
-NET "ser_t<07>" LOC = "Y24" ;
-NET "ser_t<06>" LOC = "Y25" ;
-NET "ser_t<05>" LOC = "U21" ;
-NET "ser_t<04>" LOC = "T20" ;
-NET "ser_t<03>" LOC = "Y22" ;
-NET "ser_t<02>" LOC = "Y23" ;
-NET "ser_t<01>" LOC = "U19" ;
-NET "ser_t<00>" LOC = "U18" ;
+NET "ser_t<9>" LOC = "T18" ;
+NET "ser_t<8>" LOC = "T17" ;
+NET "ser_t<7>" LOC = "Y24" ;
+NET "ser_t<6>" LOC = "Y25" ;
+NET "ser_t<5>" LOC = "U21" ;
+NET "ser_t<4>" LOC = "T20" ;
+NET "ser_t<3>" LOC = "Y22" ;
+NET "ser_t<2>" LOC = "Y23" ;
+NET "ser_t<1>" LOC = "U19" ;
+NET "ser_t<0>" LOC = "U18" ;
NET "ser_tkmsb" LOC = "AA24" ;
NET "ser_tklsb" LOC = "AA25" ;
NET "ser_r<15>" LOC = "V21" ;
@@ -251,16 +251,16 @@
NET "ser_r<12>" LOC = "AA23" ;
NET "ser_r<11>" LOC = "V18" ;
NET "ser_r<10>" LOC = "V19" ;
-NET "ser_r<09>" LOC = "AB23" ;
-NET "ser_r<08>" LOC = "AC26" ;
-NET "ser_r<07>" LOC = "AB26" ;
-NET "ser_r<06>" LOC = "AD26" ;
-NET "ser_r<05>" LOC = "AC25" ;
-NET "ser_r<04>" LOC = "W20" ;
-NET "ser_r<03>" LOC = "W21" ;
-NET "ser_r<02>" LOC = "AC23" ;
-NET "ser_r<01>" LOC = "AC24" ;
-NET "ser_r<00>" LOC = "AE26" ;
+NET "ser_r<9>" LOC = "AB23" ;
+NET "ser_r<8>" LOC = "AC26" ;
+NET "ser_r<7>" LOC = "AB26" ;
+NET "ser_r<6>" LOC = "AD26" ;
+NET "ser_r<5>" LOC = "AC25" ;
+NET "ser_r<4>" LOC = "W20" ;
+NET "ser_r<3>" LOC = "W21" ;
+NET "ser_r<2>" LOC = "AC23" ;
+NET "ser_r<1>" LOC = "AC24" ;
+NET "ser_r<0>" LOC = "AE26" ;
NET "ser_rkmsb" LOC = "AD25" ;
NET "ser_rklsb" LOC = "Y20" ;
NET "ser_rx_en" LOC = "Y21" ;
@@ -273,16 +273,16 @@
NET "RAM_D<12>" LOC = "H10" ;
NET "RAM_D<11>" LOC = "A4" ;
NET "RAM_D<10>" LOC = "B4" ;
-NET "RAM_D<09>" LOC = "C5" ;
-NET "RAM_D<08>" LOC = "D6" ;
-NET "RAM_D<07>" LOC = "J11" ;
-NET "RAM_D<06>" LOC = "K11" ;
-NET "RAM_D<05>" LOC = "B7" ;
-NET "RAM_D<04>" LOC = "C7" ;
-NET "RAM_D<03>" LOC = "B6" ;
-NET "RAM_D<02>" LOC = "C6" ;
-NET "RAM_D<01>" LOC = "C8" ;
-NET "RAM_D<00>" LOC = "D8" ;
+NET "RAM_D<9>" LOC = "C5" ;
+NET "RAM_D<8>" LOC = "D6" ;
+NET "RAM_D<7>" LOC = "J11" ;
+NET "RAM_D<6>" LOC = "K11" ;
+NET "RAM_D<5>" LOC = "B7" ;
+NET "RAM_D<4>" LOC = "C7" ;
+NET "RAM_D<3>" LOC = "B6" ;
+NET "RAM_D<2>" LOC = "C6" ;
+NET "RAM_D<1>" LOC = "C8" ;
+NET "RAM_D<0>" LOC = "D8" ;
NET "RAM_ZZ" LOC = "J12" ;
NET "RAM_BWn<3>" LOC = "D9" ;
NET "RAM_BWn<2>" LOC = "A9" ;
@@ -293,16 +293,16 @@
NET "RAM_WEn" LOC = "D10" ;
NET "RAM_CLK" LOC = "A10" ;
NET "RAM_CENn" LOC = "B10" ;
-NET "RAM_A<00>" LOC = "C11" ;
-NET "RAM_A<01>" LOC = "E12" ;
-NET "RAM_A<02>" LOC = "F12" ;
-NET "RAM_A<03>" LOC = "D13" ;
-NET "RAM_A<04>" LOC = "C12" ;
-NET "RAM_A<05>" LOC = "A12" ;
-NET "RAM_A<06>" LOC = "B12" ;
-NET "RAM_A<07>" LOC = "E14" ;
-NET "RAM_A<08>" LOC = "F14" ;
-NET "RAM_A<09>" LOC = "B15" ;
+NET "RAM_A<0>" LOC = "C11" ;
+NET "RAM_A<1>" LOC = "E12" ;
+NET "RAM_A<2>" LOC = "F12" ;
+NET "RAM_A<3>" LOC = "D13" ;
+NET "RAM_A<4>" LOC = "C12" ;
+NET "RAM_A<5>" LOC = "A12" ;
+NET "RAM_A<6>" LOC = "B12" ;
+NET "RAM_A<7>" LOC = "E14" ;
+NET "RAM_A<8>" LOC = "F14" ;
+NET "RAM_A<9>" LOC = "B15" ;
NET "RAM_A<10>" LOC = "A15" ;
NET "RAM_A<11>" LOC = "D16" ;
NET "RAM_A<12>" LOC = "C15" ;
@@ -333,12 +333,12 @@
NET "RAM_D<19>" LOC = "G20" ;
NET "RAM_D<18>" LOC = "F20" ;
#NET "unnamed_net20" LOC = "V20" ; # SUSPEND
-NET "PROG_B" LOC = "A2" ;
-NET "PUDC_B" LOC = "G8" ;
-NET "DONE" LOC = "AB21" ;
+#NET "PROG_B" LOC = "A2" ;
+#NET "PUDC_B" LOC = "G8" ;
+#NET "DONE" LOC = "AB21" ;
NET "flash_miso" LOC = "AF24" ;
NET "flash_clk" LOC = "AE24" ;
-NET "INIT_B" LOC = "AA15" ;
+#NET "INIT_B" LOC = "AA15" ;
NET "flash_mosi" LOC = "AB15" ;
#NET "unnamed_net19" LOC = "AE9" ; # VS1
#NET "unnamed_net18" LOC = "AF9" ; # VS0
Modified: gnuradio/trunk/usrp2/fpga/top/u2plus/u2plus.v
===================================================================
--- gnuradio/trunk/usrp2/fpga/top/u2plus/u2plus.v 2009-08-31 03:12:37 UTC
(rev 11623)
+++ gnuradio/trunk/usrp2/fpga/top/u2plus/u2plus.v 2009-08-31 04:05:00 UTC
(rev 11624)
@@ -4,18 +4,21 @@
module u2plus
(
// Misc, debug
- output [4:0] leds, // LED4 is shared w/INIT_B
- input [3:0] dipsw,
+ output [5:1] leds,
+ output ETH_LED,
output [31:0] debug,
output [1:0] debug_clk,
- output uart_tx_o,
- input uart_rx_i,
+ output TXD1, input RXD1, output TXD2, input RXD2, output TXD3, input RXD3,
// Expansion
- input exp_pps_in_p, // Diff
- input exp_pps_in_n, // Diff
- output exp_pps_out_p, // Diff
- output exp_pps_out_n, // Diff
+ input exp_time_in_p, // Diff
+ input exp_time_in_n, // Diff
+ output exp_time_out_p, // Diff
+ output exp_time_out_n, // Diff
+ input exp_user_in_p, // Diff
+ input exp_user_in_n, // Diff
+ output exp_user_out_p, // Diff
+ output exp_user_out_n, // Diff
// GMII
// GMII-CTRL
@@ -41,8 +44,17 @@
input PHY_INTn, // open drain
output PHY_RESETn,
input PHY_CLK, // possibly use on-board osc
- input clk_to_mac,
- output eth_led,
+
+ // RAM
+ inout [35:0] RAM_D,
+ output [20:0] RAM_A,
+ output [3:0] RAM_BWn,
+ output RAM_CE1n,
+ output RAM_CENn,
+ output RAM_CLK,
+ output RAM_WEn,
+ output RAM_OEn,
+ output RAM_LDn,
// SERDES
output ser_enable,
@@ -60,6 +72,8 @@
input ser_rklsb,
input ser_rkmsb,
+ input FPGA_RESET,
+
// ADC
input [13:0] adc_a,
input adc_ovf_a,
@@ -72,8 +86,8 @@
output adc_pdn_b,
// DAC
- output [15:0] dac_a,
- output [15:0] dac_b,
+ output reg [15:0] TXA,
+ output reg [15:0] TXB,
input dac_lock, // unused for now
// I2C
@@ -89,27 +103,26 @@
// Clocks
input clk_fpga_p, // Diff
input clk_fpga_n, // Diff
- input pps_in,
- input POR,
+ input clk_to_mac,
+ input PPS_IN,
+ input PPS2_IN,
+
+ // SPI
+ output flash_mosi, input flash_miso, output flash_clk, output flash_cs,
+ output MOSI_CLK, input MISO_CLK, output SCLK_CLK, output SEN_CLK,
+ output MOSI_ADC, input MISO_ADC, output SCLK_ADC, output SEN_ADC,
+ output MOSI_RX_DB, input MISO_RX_DB, output SCLK_RX_DB, output SEN_RX_DB,
+ output MOSI_RX_DAC, input MISO_RX_DAC, output SCLK_RX_DAC, output
SEN_RX_DAC,
+ output MOSI_RX_ADC, input MISO_RX_ADC, output SCLK_RX_ADC, output
SEN_RX_ADC,
+ output MOSI_DAC, input MISO_DAC, output SCLK_DAC, output SEN_DAC,
+ output MOSI_TX_DB, input MISO_TX_DB, output SCLK_TX_DB, output SEN_TX_DB,
+ output MOSI_TX_DAC, input MISO_TX_DAC, output SCLK_TX_DAC, output
SEN_TX_DAC,
+ output MOSI_TX_ADC, input MISO_TX_ADC, output SCLK_TX_ADC, output
SEN_TX_ADC,
- // AD9510 SPI
- output sclk,
- output sen_clk,
- output sdi,
- input sdo,
+ // TX DBoard
+ inout [15:0] io_tx,
- // TX side SPI -- tx_db, tx_adc, tx_dac, 9777
- output sen_dac,
- output sen_tx_db,
- output sen_tx_adc,
- output sen_tx_dac,
- output mosi_tx,
- input miso_dac,
- input miso_tx_db,
- input miso_tx_adc,
- output sclk_tx,
-
- // RX side SPI
+ // RX DBoard
output sen_rx_db,
output sclk_rx_db,
input sdo_rx_db,
@@ -123,50 +136,116 @@
output sen_rx_dac,
output sclk_rx_dac,
output sdi_rx_dac,
-
- // DB IO Pins
- inout [15:0] io_tx,
+
inout [15:0] io_rx,
- // SPI Flash
- output flash_cs,
- output flash_clk,
- output flash_mosi,
- input flash_miso
+ // NEW
+ input ADC_clkout_p, input ADC_clkout_n,
+ input ADCB_12_13_p, input ADCB_12_13_n,
+ input ADCB_10_11_p, input ADCB_10_11_n,
+ input ADCB_8_9_p, input ADCB_8_9_n,
+ input ADCB_6_7_p, input ADCB_6_7_n,
+ input ADCB_4_5_p, input ADCB_4_5_n,
+ input ADCB_2_3_p, input ADCB_2_3_n,
+ input ADCB_0_1_p, input ADCB_0_1_n,
+ input ADCA_12_13_p, input ADCA_12_13_n,
+ input ADCA_10_11_p, input ADCA_10_11_n,
+ input ADCA_8_9_p, input ADCA_8_9_n,
+ input ADCA_6_7_p, input ADCA_6_7_n,
+ input ADCA_4_5_p, input ADCA_4_5_n,
+ input ADCA_2_3_p, input ADCA_2_3_n,
+ input ADCA_0_1_p, input ADCA_0_1_n,
+
+ output RAM_ZZ
);
+ wire CLK_ADC;
+ wire [13:0] DA, DB;
+ wire [6:0] DA_DDR, DB_DDR;
+
+ IBUFGDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) dbd_10 (.O(CLK_ADC),
.I(ADC_clkout_p), .IB(ADC_clkout_n) );
+ IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) dbd_00 (.O(DB_DDR[6]),
.I(ADCB_12_13_p), .IB(ADCB_12_13_n) );
+ IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) dbd_01 (.O(DB_DDR[5]),
.I(ADCB_10_11_p), .IB(ADCB_10_11_n) );
+ IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) dbd_02 (.O(DB_DDR[4]),
.I(ADCB_8_9_p), .IB(ADCB_8_9_n) );
+ IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) dbd_03 (.O(DB_DDR[3]),
.I(ADCB_6_7_p), .IB(ADCB_6_7_n) );
+ IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) dbd_04 (.O(DB_DDR[2]),
.I(ADCB_4_5_p), .IB(ADCB_4_5_n) );
+ IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) dbd_05 (.O(DB_DDR[1]),
.I(ADCB_2_3_p), .IB(ADCB_2_3_n) );
+ IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) dbd_06 (.O(DB_DDR[0]),
.I(ADCB_0_1_p), .IB(ADCB_0_1_n) );
+ IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) dbd_07 (.O(DA_DDR[6]),
.I(ADCA_12_13_p), .IB(ADCA_12_13_n) );
+ IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) dbd_08 (.O(DA_DDR[5]),
.I(ADCA_10_11_p), .IB(ADCA_10_11_n) );
+ IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) dbd_09 (.O(DA_DDR[4]),
.I(ADCA_8_9_p), .IB(ADCA_8_9_n) );
+ IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) dbd_11 (.O(DA_DDR[3]),
.I(ADCA_6_7_p), .IB(ADCA_6_7_n) );
+ IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) dbd_12 (.O(DA_DDR[2]),
.I(ADCA_4_5_p), .IB(ADCA_4_5_n) );
+ IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) dbd_13 (.O(DA_DDR[1]),
.I(ADCA_2_3_p), .IB(ADCA_2_3_n) );
+ IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("TRUE")) dbd_14 (.O(DA_DDR[0]),
.I(ADCA_0_1_p), .IB(ADCA_0_1_n) );
+
+ IDDR2 #(.DDR_ALIGNMENT("NONE")) IDDR2_00 (.Q0(DA[0]), .Q1(DA[1]),
.C0(CLK_ADC), .C1(~CLK_ADC), .CE(1'b1), .D(DA_DDR[0]), .R(1'b0), .S(1'b0));
+ IDDR2 #(.DDR_ALIGNMENT("NONE")) IDDR2_01 (.Q0(DA[2]), .Q1(DA[3]),
.C0(CLK_ADC), .C1(~CLK_ADC), .CE(1'b1), .D(DA_DDR[1]), .R(1'b0), .S(1'b0));
+ IDDR2 #(.DDR_ALIGNMENT("NONE")) IDDR2_02 (.Q0(DA[4]), .Q1(DA[5]),
.C0(CLK_ADC), .C1(~CLK_ADC), .CE(1'b1), .D(DA_DDR[2]), .R(1'b0), .S(1'b0));
+ IDDR2 #(.DDR_ALIGNMENT("NONE")) IDDR2_03 (.Q0(DA[6]), .Q1(DA[7]),
.C0(CLK_ADC), .C1(~CLK_ADC), .CE(1'b1), .D(DA_DDR[3]), .R(1'b0), .S(1'b0));
+ IDDR2 #(.DDR_ALIGNMENT("NONE")) IDDR2_04 (.Q0(DA[8]), .Q1(DA[9]),
.C0(CLK_ADC), .C1(~CLK_ADC), .CE(1'b1), .D(DA_DDR[4]), .R(1'b0), .S(1'b0));
+ IDDR2 #(.DDR_ALIGNMENT("NONE")) IDDR2_05 (.Q0(DA[10]), .Q1(DA[11]),
.C0(CLK_ADC), .C1(~CLK_ADC), .CE(1'b1), .D(DA_DDR[5]), .R(1'b0), .S(1'b0));
+ IDDR2 #(.DDR_ALIGNMENT("NONE")) IDDR2_06 (.Q0(DA[12]), .Q1(DA[13]),
.C0(CLK_ADC), .C1(~CLK_ADC), .CE(1'b1), .D(DA_DDR[6]), .R(1'b0), .S(1'b0));
+ IDDR2 #(.DDR_ALIGNMENT("NONE")) IDDR2_07 (.Q0(DB[0]), .Q1(DB[1]),
.C0(CLK_ADC), .C1(~CLK_ADC), .CE(1'b1), .D(DB_DDR[0]), .R(1'b0), .S(1'b0));
+ IDDR2 #(.DDR_ALIGNMENT("NONE")) IDDR2_08 (.Q0(DB[2]), .Q1(DB[3]),
.C0(CLK_ADC), .C1(~CLK_ADC), .CE(1'b1), .D(DB_DDR[1]), .R(1'b0), .S(1'b0));
+ IDDR2 #(.DDR_ALIGNMENT("NONE")) IDDR2_09 (.Q0(DB[4]), .Q1(DB[5]),
.C0(CLK_ADC), .C1(~CLK_ADC), .CE(1'b1), .D(DB_DDR[2]), .R(1'b0), .S(1'b0));
+ IDDR2 #(.DDR_ALIGNMENT("NONE")) IDDR2_10 (.Q0(DB[6]), .Q1(DB[7]),
.C0(CLK_ADC), .C1(~CLK_ADC), .CE(1'b1), .D(DB_DDR[3]), .R(1'b0), .S(1'b0));
+ IDDR2 #(.DDR_ALIGNMENT("NONE")) IDDR2_11 (.Q0(DB[8]), .Q1(DB[9]),
.C0(CLK_ADC), .C1(~CLK_ADC), .CE(1'b1), .D(DB_DDR[4]), .R(1'b0), .S(1'b0));
+ IDDR2 #(.DDR_ALIGNMENT("NONE")) IDDR2_12 (.Q0(DB[10]), .Q1(DB[11]),
.C0(CLK_ADC), .C1(~CLK_ADC), .CE(1'b1), .D(DB_DDR[5]), .R(1'b0), .S(1'b0));
+ IDDR2 #(.DDR_ALIGNMENT("NONE")) IDDR2_13 (.Q0(DB[12]), .Q1(DB[13]),
.C0(CLK_ADC), .C1(~CLK_ADC), .CE(1'b1), .D(DB_DDR[6]), .R(1'b0), .S(1'b0));
+
+ assign cpld_init_b = 0;
// FPGA-specific pins connections
- wire aux_clk = PHY_CLK;
-
wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+ wire clk90, clk180, clk270;
+ // reset the watchdog continuously
+ wire config_success;
+
IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
- wire exp_pps_in;
- IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
- defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+ wire exp_time_in;
+ IBUFDS exp_time_in_pin
(.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n));
+ defparam exp_time_in_pin.IOSTANDARD = "LVDS_25";
- wire exp_pps_out;
- OBUFDS exp_pps_out_pin
(.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
- defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+ wire exp_time_out;
+ OBUFDS exp_time_out_pin
(.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out));
+ defparam exp_time_out_pin.IOSTANDARD = "LVDS_25";
reg [5:0] clock_ready_d;
- always @(posedge aux_clk)
+ always @(posedge clk_fpga)
clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
-
wire dcm_rst = ~&clock_ready_d & |clock_ready_d;
- wire clk_muxed = clock_ready ? clk_fpga : aux_clk;
-
+
wire adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
assign adc_oen_a = ~adc_oe_a;
assign adc_oen_b = ~adc_oe_b;
assign adc_pdn_a = ~adc_on_a;
assign adc_pdn_b = ~adc_on_b;
+ reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
+ reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1,
adc_ovf_b_reg2;
+
+ always @(posedge dsp_clk)
+ begin
+ adc_a_reg1 <= adc_a;
+ adc_b_reg1 <= adc_b;
+ adc_ovf_a_reg1 <= adc_ovf_a;
+ adc_ovf_b_reg1 <= adc_ovf_b;
+ end
+
+ always @(posedge dsp_clk)
+ begin
+ adc_a_reg2 <= adc_a_reg1;
+ adc_b_reg2 <= adc_b_reg1;
+ adc_ovf_a_reg2 <= adc_ovf_a_reg1;
+ adc_ovf_b_reg2 <= adc_ovf_b_reg1;
+ end // always @ (posedge dsp_clk)
+
// Handle Clocks
DCM DCM_INST (.CLKFB(dsp_clk),
- .CLKIN(clk_muxed),
+ .CLKIN(clk_fpga),
.DSSEN(0),
.PSCLK(0),
.PSEN(0),
@@ -178,9 +257,9 @@
.CLK0(dcm_out),
.CLK2X(),
.CLK2X180(),
- .CLK90(),
- .CLK180(),
- .CLK270(),
+ .CLK90(clk90),
+ .CLK180(clk180),
+ .CLK270(clk270),
.LOCKED(LOCKED_OUT),
.PSDONE(),
.STATUS());
@@ -207,23 +286,30 @@
IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
// LEDs are active low outputs
- wire [4:0] leds_int;
- assign leds = ~leds_int; // drive low to turn on leds
+ wire [5:0] leds_int;
+ assign {leds,ETH_LED} = 6'b011111 ^ leds_int; // all except eth are
active-low
// SPI
- wire miso, mosi, sclk_int;
- assign {sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
- assign {sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
- assign {sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
- assign {sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
- assign {sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
- assign {sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
- assign {sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+ wire miso, mosi, sclk;
+ wire [9:0] sen;
+ assign {flash_cs,
SEN_ADC,SEN_TX_DB,SEN_TX_ADC,SEN_TX_DAC,SEN_RX_DB,SEN_RX_ADC,SEN_RX_DAC,SEN_DAC,SEN_CLK}
= sen;
+ assign {flash_clk, flash_mosi} = ~flash_cs ? {sclk, mosi} :
2'b00;
+ assign {SCLK_CLK, MOSI_CLK} = ~SEN_CLK ? {sclk, mosi} : 2'b00;
+ assign {SCLK_ADC, MOSI_ADC} = ~SEN_ADC ? {sclk, mosi} : 2'b00;
+ assign {SCLK_DAC, MOSI_DAC} = ~SEN_DAC ? {sclk, mosi} : 2'b00;
+ assign {SCLK_RX_DB, MOSI_RX_DB} = ~SEN_RX_DB ? {sclk, mosi} : 2'b00;
+ assign {SCLK_TX_DB, MOSI_TX_DB} = ~SEN_TX_DB ? {sclk, mosi} : 2'b00;
+ assign {SCLK_RX_ADC, MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk, mosi} : 2'b00;
+ assign {SCLK_TX_ADC, MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk, mosi} : 2'b00;
+ assign {SCLK_RX_DAC, MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk, mosi} : 2'b00;
+ assign {SCLK_TX_DAC, MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk, mosi} : 2'b00;
- assign miso = (~sen_clk & sdo) | (~sen_dac & sdo) |
- (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
- (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+ assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC &
MISO_DAC) |
+ (~SEN_RX_ADC & MISO_RX_ADC) |
(~SEN_TX_ADC & MISO_TX_ADC) |
+ (~SEN_RX_DB & MISO_RX_DB) | (~SEN_TX_DB
& MISO_TX_DB) |
+ (~flash_cs & flash_miso) ;
+ // GMII
wire GMII_TX_EN_unreg, GMII_TX_ER_unreg;
wire [7:0] GMII_TXD_unreg;
wire GMII_GTX_CLK_int;
@@ -268,7 +354,11 @@
ser_rklsb_int <= ser_rklsb;
ser_rkmsb_int <= ser_rkmsb;
end
-
+
+ wire [15:0] dac_a_int, dac_b_int;
+ always @(negedge dsp_clk) TXA <= dac_a_int;
+ always @(negedge dsp_clk) TXB <= dac_b_int;
+
/*
OFDDRRSE OFDDRRSE_serdes_inst
(.Q(ser_tx_clk), // Data output (connect directly to top-level port)
@@ -281,16 +371,19 @@
.S(0) // Synchronous preset input
);
*/
- u2_core u2_core(.dsp_clk (dsp_clk),
+ u2_core #(.RAM_SIZE(32768))
+ u2_core(.dsp_clk (dsp_clk),
.wb_clk (wb_clk),
.clock_ready (clock_ready),
.clk_to_mac (clk_to_mac),
- .pps_in (pps_in),
+ .pps_in (PPS_IN),
.leds (leds_int),
.debug (debug[31:0]),
.debug_clk (debug_clk[1:0]),
- .exp_pps_in (exp_pps_in),
- .exp_pps_out (exp_pps_out),
+ .exp_pps_in (exp_time_in),
+ .exp_pps_out (exp_time_out),
+ //.exp_user_in (exp_user_in),
+ //.exp_user_out (exp_user_out),
.GMII_COL (GMII_COL),
.GMII_CRS (GMII_CRS),
.GMII_TXD (GMII_TXD_unreg[7:0]),
@@ -306,7 +399,6 @@
.MDC (MDC),
.PHY_INTn (PHY_INTn),
.PHY_RESETn (PHY_RESETn),
- .PHY_CLK (PHY_CLK),
.ser_enable (ser_enable),
.ser_prbsen (ser_prbsen),
.ser_loopen (ser_loopen),
@@ -319,22 +411,18 @@
.ser_r (ser_r_int[15:0]),
.ser_rklsb (ser_rklsb_int),
.ser_rkmsb (ser_rkmsb_int),
- .cpld_start (cpld_start),
- .cpld_mode (cpld_mode),
- .cpld_done (cpld_done),
- .cpld_din (cpld_din),
- .cpld_clk (cpld_clk),
- .cpld_detached (cpld_detached),
- .adc_a (adc_a[13:0]),
- .adc_ovf_a (adc_ovf_a),
+ .por (~POR),
+ .config_success (config_success),
+ .adc_a (adc_a_reg2),
+ .adc_ovf_a (adc_ovf_a_reg2),
.adc_on_a (adc_on_a),
.adc_oe_a (adc_oe_a),
- .adc_b (adc_b[13:0]),
- .adc_ovf_b (adc_ovf_b),
+ .adc_b (adc_b_reg2),
+ .adc_ovf_b (adc_ovf_b_reg2),
.adc_on_b (adc_on_b),
.adc_oe_b (adc_oe_b),
- .dac_a (dac_a[15:0]),
- .dac_b (dac_b[15:0]),
+ .dac_a (dac_a_int),
+ .dac_b (dac_b_int),
.scl_pad_i (scl_pad_i),
.scl_pad_o (scl_pad_o),
.scl_pad_oen_o (scl_pad_oen_o),
@@ -345,17 +433,10 @@
.clk_sel (clk_sel[1:0]),
.clk_func (clk_func),
.clk_status (clk_status),
- .sclk (sclk_int),
+ .sclk (sclk),
.mosi (mosi),
.miso (miso),
- .sen_clk (sen_clk),
- .sen_dac (sen_dac),
- .sen_tx_db (sen_tx_db),
- .sen_tx_adc (sen_tx_adc),
- .sen_tx_dac (sen_tx_dac),
- .sen_rx_db (sen_rx_db),
- .sen_rx_adc (sen_rx_adc),
- .sen_rx_dac (sen_rx_dac),
+// .sen (sen),
.io_tx (io_tx[15:0]),
.io_rx (io_rx[15:0]),
.RAM_D (RAM_D),
@@ -367,11 +448,10 @@
.RAM_OEn (RAM_OEn),
.RAM_LDn (RAM_LDn),
.uart_tx_o (uart_tx_o),
- //.uart_rx_i (uart_rx_i),
- .uart_rx_i (),
+ .uart_rx_i (uart_rx_i),
.uart_baud_o (),
.sim_mode (1'b0),
.clock_divider (2)
);
-endmodule // u2plus
+endmodule // u2_rev2
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- [Commit-gnuradio] r11624 - gnuradio/trunk/usrp2/fpga/top/u2plus,
matt <=