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[Commit-gnuradio] r10830 - in gnuradio/branches/releases/3.2: . gnuradio
|
From: |
jcorgan |
|
Subject: |
[Commit-gnuradio] r10830 - in gnuradio/branches/releases/3.2: . gnuradio-core/src/python/gnuradio/gr gr-wxgui/src/python/plotter grc/data/platforms/python/blocks usrp2/firmware/lib usrp2/fpga usrp2/fpga/control_lib usrp2/fpga/control_lib/newfifo usrp2/fpga/eth usrp2/fpga/eth/rtl/verilog usrp2/fpga/simple_gemac usrp2/fpga/simple_gemac/miim usrp2/fpga/top/u2_core |
|
Date: |
Tue, 14 Apr 2009 13:41:41 -0600 (MDT) |
Author: jcorgan
Date: 2009-04-14 13:41:41 -0600 (Tue, 14 Apr 2009)
New Revision: 10830
Added:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_int.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_int_tb.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_pool.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_pool_tb.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo18_to_ll8.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo19_to_fifo36.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo19_to_ll8.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo36_to_fifo18.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo36_to_fifo19.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo36_to_ll8.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_2clock.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_2clock_casc.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_cascade.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_long.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_new_tb.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_new_tb.vcd
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_short.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_spec.txt
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_tb.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/ll8_to_fifo19.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/ll8_to_fifo36.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/reset_sync.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/address_filter.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/crc.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/delay_line.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/eth_tasks.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/flow_ctrl_rx.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/flow_ctrl_tx.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/ll8_shortfifo.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/ll8_to_txmac.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_clockgen.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_miim.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_outputcontrol.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_shiftreg.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/rxmac_to_ll8.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_rx.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_tb.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_tx.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_wb.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/test_packet.mem
Removed:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_int.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_int_tb.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_pool.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_pool_tb.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo18_to_ll8.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo19_to_fifo36.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo19_to_ll8.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo36_to_fifo18.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo36_to_fifo19.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo36_to_ll8.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_2clock.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_2clock_casc.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_cascade.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_long.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_new_tb.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_new_tb.vcd
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_short.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_spec.txt
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_tb.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/ll8_to_fifo19.v
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/ll8_to_fifo36.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/crc.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/flow_ctrl_rx.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/flow_ctrl_tx.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_clockgen.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_miim.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_outputcontrol.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_shiftreg.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_rx.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_tb.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_tx.v
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/test_packet.mem
Modified:
gnuradio/branches/releases/3.2/
gnuradio/branches/releases/3.2/gnuradio-core/src/python/gnuradio/gr/pubsub.py
gnuradio/branches/releases/3.2/gr-wxgui/src/python/plotter/grid_plotter_base.py
gnuradio/branches/releases/3.2/grc/data/platforms/python/blocks/gr_add_xx.xml
gnuradio/branches/releases/3.2/grc/data/platforms/python/blocks/gr_multiply_xx.xml
gnuradio/branches/releases/3.2/usrp2/firmware/lib/eth_mac.c
gnuradio/branches/releases/3.2/usrp2/firmware/lib/eth_mac_regs.h
gnuradio/branches/releases/3.2/usrp2/fpga/eth/mac_rxfifo_int.v
gnuradio/branches/releases/3.2/usrp2/fpga/eth/rtl/verilog/MAC_top.v
gnuradio/branches/releases/3.2/usrp2/fpga/eth/rtl/verilog/Reg_int.v
gnuradio/branches/releases/3.2/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v
gnuradio/branches/releases/3.2/usrp2/fpga/top/u2_core/u2_core.v
Log:
Applied changesets r10706:10710, r10714:10721, r10724:10733, r10738:10744,
r10745:10751, r10758:10762 to release 3.2 branch.
Property changes on: gnuradio/branches/releases/3.2
___________________________________________________________________
Modified: svn:mergeinfo
- /gnuradio/branches/developers/eb/t348:10638-10648
/gnuradio/branches/developers/eb/t378:10683-10688
/gnuradio/branches/developers/jblum/gui_guts:10464-10658
/gnuradio/branches/developers/jblum/vlen:10667-10677
/gnuradio/branches/developers/michaelld/am_swig_4:10555-10595
/gnuradio/branches/developers/michaelld/two_mods:10540-10546
/gnuradio/trunk:10356-10359,10481-10482,10497-10499,10506-10507,10511,10514,10521,10523-10524,10529,10531,10535,10537-10538,10550-10551,10556,10558-10560,10562-10563,10565,10574-10576,10578-10579,10581-10582,10585,10587,10596-10600,10623-10624,10629,10632-10634,10645-10646,10649-10650,10653-10655,10660-10661,10671,10673,10678,10681,10686,10689,10691,10701-10702,10734-10736,10745
+ /gnuradio/branches/developers/eb/t348:10638-10648
/gnuradio/branches/developers/eb/t378:10683-10688
/gnuradio/branches/developers/jblum/gui_guts:10464-10658
/gnuradio/branches/developers/jblum/vlen:10667-10677
/gnuradio/branches/developers/michaelld/am_swig_4:10555-10595
/gnuradio/branches/developers/michaelld/two_mods:10540-10546
/gnuradio/trunk:10356-10359,10481-10482,10497-10499,10506-10507,10511,10514,10521,10523-10524,10529,10531,10535,10537-10538,10550-10551,10556,10558-10560,10562-10563,10565,10574-10576,10578-10579,10581-10582,10585,10587,10596-10600,10623-10624,10629,10632-10634,10645-10646,10649-10650,10653-10655,10660-10661,10671,10673,10678,10681,10686,10689,10691,10701-10702,10707-10710,10715-10721,10725,10728-10736,10739-10751,10759-10762
Property changes on:
gnuradio/branches/releases/3.2/gnuradio-core/src/python/gnuradio/gr/pubsub.py
___________________________________________________________________
Modified: svn:mergeinfo
-
/gnuradio/branches/developers/eb/t348/gnuradio-core/src/python/gnuradio/gr/pubsub.py:10638-10648
/gnuradio/branches/developers/eb/t378/gnuradio-core/src/python/gnuradio/gr/pubsub.py:10683-10688
/gnuradio/branches/developers/jblum/vlen/gnuradio-core/src/python/gnuradio/gr/pubsub.py:10667-10677
/gnuradio/trunk/gnuradio-core/src/python/gnuradio/gr/pubsub.py:10653-10655,10660-10661,10671,10673,10678,10681,10686,10689,10691,10701-10702,10734-10736,10745
+
/gnuradio/branches/developers/eb/t348/gnuradio-core/src/python/gnuradio/gr/pubsub.py:10638-10648
/gnuradio/branches/developers/eb/t378/gnuradio-core/src/python/gnuradio/gr/pubsub.py:10683-10688
/gnuradio/branches/developers/jblum/vlen/gnuradio-core/src/python/gnuradio/gr/pubsub.py:10667-10677
/gnuradio/trunk/gnuradio-core/src/python/gnuradio/gr/pubsub.py:10653-10655,10660-10661,10671,10673,10678,10681,10686,10689,10691,10701-10702,10707-10710,10715-10721,10725,10728-10736,10739-10751,10759-10762
Property changes on:
gnuradio/branches/releases/3.2/gr-wxgui/src/python/plotter/grid_plotter_base.py
___________________________________________________________________
Modified: svn:mergeinfo
-
/gnuradio/branches/developers/eb/t378/gr-wxgui/src/python/plotter/grid_plotter_base.py:10683-10688
/gnuradio/branches/developers/jblum/vlen/gr-wxgui/src/python/plotter/grid_plotter_base.py:10667-10677
/gnuradio/trunk/gr-wxgui/src/python/plotter/grid_plotter_base.py:10673,10678,10681,10686,10689,10691,10701-10702,10734-10736,10745
+
/gnuradio/branches/developers/eb/t378/gr-wxgui/src/python/plotter/grid_plotter_base.py:10683-10688
/gnuradio/branches/developers/jblum/vlen/gr-wxgui/src/python/plotter/grid_plotter_base.py:10667-10677
/gnuradio/trunk/gr-wxgui/src/python/plotter/grid_plotter_base.py:10673,10678,10681,10686,10689,10691,10701-10702,10707-10710,10715-10721,10725,10728-10736,10739-10751,10759-10762
Property changes on:
gnuradio/branches/releases/3.2/grc/data/platforms/python/blocks/gr_add_xx.xml
___________________________________________________________________
Modified: svn:mergeinfo
-
/gnuradio/branches/developers/eb/t348/grc/data/platforms/python/blocks/gr_add_vxx.xml:10638-10648
/gnuradio/branches/developers/eb/t378/grc/data/platforms/python/blocks/gr_add_xx.xml:10683-10688
/gnuradio/branches/developers/jblum/gui_guts/grc/data/platforms/python/blocks/gr_add_vxx.xml:10464-10658
/gnuradio/branches/developers/michaelld/am_swig_4/grc/data/platforms/python/blocks/gr_add_vxx.xml:10555-10595
/gnuradio/branches/developers/michaelld/two_mods/grc/data/platforms/python/blocks/gr_add_vxx.xml:10540-10546
/gnuradio/trunk/grc/data/platforms/python/blocks/gr_add_xx.xml:10681,10686,10689,10691,10701-10702,10734-10736,10745
+
/gnuradio/branches/developers/eb/t348/grc/data/platforms/python/blocks/gr_add_vxx.xml:10638-10648
/gnuradio/branches/developers/eb/t378/grc/data/platforms/python/blocks/gr_add_xx.xml:10683-10688
/gnuradio/branches/developers/jblum/gui_guts/grc/data/platforms/python/blocks/gr_add_vxx.xml:10464-10658
/gnuradio/branches/developers/michaelld/am_swig_4/grc/data/platforms/python/blocks/gr_add_vxx.xml:10555-10595
/gnuradio/branches/developers/michaelld/two_mods/grc/data/platforms/python/blocks/gr_add_vxx.xml:10540-10546
/gnuradio/trunk/grc/data/platforms/python/blocks/gr_add_xx.xml:10681,10686,10689,10691,10701-10702,10707-10710,10715-10721,10725,10728-10736,10739-10751,10759-10762
Property changes on:
gnuradio/branches/releases/3.2/grc/data/platforms/python/blocks/gr_multiply_xx.xml
___________________________________________________________________
Modified: svn:mergeinfo
-
/gnuradio/branches/developers/eb/t348/grc/data/platforms/python/blocks/gr_multiply_vxx.xml:10638-10648
/gnuradio/branches/developers/eb/t378/grc/data/platforms/python/blocks/gr_multiply_xx.xml:10683-10688
/gnuradio/branches/developers/jblum/gui_guts/grc/data/platforms/python/blocks/gr_multiply_vxx.xml:10464-10658
/gnuradio/branches/developers/michaelld/am_swig_4/grc/data/platforms/python/blocks/gr_multiply_vxx.xml:10555-10595
/gnuradio/branches/developers/michaelld/two_mods/grc/data/platforms/python/blocks/gr_multiply_vxx.xml:10540-10546
/gnuradio/trunk/grc/data/platforms/python/blocks/gr_multiply_xx.xml:10681,10686,10689,10691,10701-10702,10734-10736,10745
+
/gnuradio/branches/developers/eb/t348/grc/data/platforms/python/blocks/gr_multiply_vxx.xml:10638-10648
/gnuradio/branches/developers/eb/t378/grc/data/platforms/python/blocks/gr_multiply_xx.xml:10683-10688
/gnuradio/branches/developers/jblum/gui_guts/grc/data/platforms/python/blocks/gr_multiply_vxx.xml:10464-10658
/gnuradio/branches/developers/michaelld/am_swig_4/grc/data/platforms/python/blocks/gr_multiply_vxx.xml:10555-10595
/gnuradio/branches/developers/michaelld/two_mods/grc/data/platforms/python/blocks/gr_multiply_vxx.xml:10540-10546
/gnuradio/trunk/grc/data/platforms/python/blocks/gr_multiply_xx.xml:10681,10686,10689,10691,10701-10702,10707-10710,10715-10721,10725,10728-10736,10739-10751,10759-10762
Modified: gnuradio/branches/releases/3.2/usrp2/firmware/lib/eth_mac.c
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/firmware/lib/eth_mac.c 2009-04-14
19:31:57 UTC (rev 10829)
+++ gnuradio/branches/releases/3.2/usrp2/firmware/lib/eth_mac.c 2009-04-14
19:41:41 UTC (rev 10830)
@@ -69,6 +69,8 @@
eth_mac->fc_lwmark = 600; // there are currently 2047 lines in
the fifo
eth_mac->fc_hwmark = 1200;
+ eth_mac->fc_padtime = 1700; // how long before flow control runs
out do we
+ // request a re-pause. Units of 8ns
(bytes)
//eth_mac->tx_pause_en = 0; // pay attn to pause frames sent to us
//eth_mac->pause_quanta_set = 38; // a bit more than 1 max frame 16kb/512
+ fudge
Modified: gnuradio/branches/releases/3.2/usrp2/firmware/lib/eth_mac_regs.h
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/firmware/lib/eth_mac_regs.h
2009-04-14 19:31:57 UTC (rev 10829)
+++ gnuradio/branches/releases/3.2/usrp2/firmware/lib/eth_mac_regs.h
2009-04-14 19:41:41 UTC (rev 10830)
@@ -81,6 +81,7 @@
volatile int miitx_data;
volatile int miirx_data;
volatile int miistatus;
+ volatile int fc_padtime;
} eth_mac_regs_t;
// miicommand register
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_int.v
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/buffer_int.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_int.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_int.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,168 @@
+
+// FIFO Interface to the 2K buffer RAMs
+// Read port is read-acknowledge
+// FIXME do we want to be able to interleave reads and writes?
+
+module buffer_int
+ #(parameter BUF_NUM = 0,
+ parameter BUF_SIZE = 9)
+ (// Control Interface
+ input clk,
+ input rst,
+ input [31:0] ctrl_word,
+ input go,
+ output done,
+ output error,
+ output idle,
+ output [1:0] flag,
+
+ // Buffer Interface
+ output en_o,
+ output we_o,
+ output reg [BUF_SIZE-1:0] addr_o,
+ output [31:0] dat_to_buf,
+ input [31:0] dat_from_buf,
+
+ // Write FIFO Interface
+ input [31:0] wr_data_i,
+ input [3:0] wr_flags_i,
+ input wr_ready_i,
+ output wr_ready_o,
+
+ // Read FIFO Interface
+ output [31:0] rd_data_o,
+ output [3:0] rd_flags_o,
+ output rd_ready_o,
+ input rd_ready_i
+ );
+
+ reg [31:0] ctrl_reg;
+ reg go_reg;
+
+ always @(posedge clk)
+ go_reg <= go;
+
+ always @(posedge clk)
+ if(rst)
+ ctrl_reg <= 0;
+ else
+ if(go & (ctrl_word[31:28] == BUF_NUM))
+ ctrl_reg <= ctrl_word;
+
+ wire [BUF_SIZE-1:0] firstline = ctrl_reg[BUF_SIZE-1:0];
+ wire [BUF_SIZE-1:0] lastline = ctrl_reg[2*BUF_SIZE-1:BUF_SIZE];
+
+ wire read = ctrl_reg[22];
+ wire write = ctrl_reg[23];
+ wire clear = ctrl_reg[24];
+ //wire [2:0] port = ctrl_reg[27:25]; // Ignored in this block
+ //wire [3:0] buff_num = ctrl_reg[31:28]; // Ignored here ?
+
+ localparam IDLE = 3'd0;
+ localparam PRE_READ = 3'd1;
+ localparam READING = 3'd2;
+ localparam WRITING = 3'd3;
+ localparam ERROR = 3'd4;
+ localparam DONE = 3'd5;
+
+ reg [2:0] state;
+ reg rd_sop, rd_eop;
+ wire wr_sop, wr_eop, wr_error;
+ reg [1:0] rd_occ;
+ wire [1:0] wr_occ;
+
+ always @(posedge clk)
+ if(rst)
+ begin
+ state <= IDLE;
+ rd_sop <= 0;
+ rd_eop <= 0;
+ rd_occ <= 0;
+ end
+ else
+ if(clear)
+ begin
+ state <= IDLE;
+ rd_sop <= 0;
+ rd_eop <= 0;
+ rd_occ <= 0;
+ end
+ else
+ case(state)
+ IDLE :
+ if(go_reg & read)
+ begin
+ addr_o <= firstline;
+ state <= PRE_READ;
+ end
+ else if(go_reg & write)
+ begin
+ addr_o <= firstline;
+ state <= WRITING;
+ end
+
+ PRE_READ :
+ begin
+ state <= READING;
+ addr_o <= addr_o + 1;
+ rd_occ <= 2'b00;
+ rd_sop <= 1;
+ rd_eop <= 0;
+ end
+
+ READING :
+ if(rd_ready_i)
+ begin
+ rd_sop <= 0;
+ addr_o <= addr_o + 1;
+ if(addr_o == lastline)
+ begin
+ rd_eop <= 1;
+ // FIXME assign occ here
+ rd_occ <= 0;
+ end
+ else
+ rd_eop <= 0;
+ if(rd_eop)
+ state <= DONE;
+ end
+
+ WRITING :
+ begin
+ if(wr_ready_i)
+ begin
+ addr_o <= addr_o + 1;
+ if(wr_error)
+ begin
+ state <= ERROR;
+ // Save OCC flags here
+ end
+ else if((addr_o == lastline)||wr_eop)
+ state <= DONE;
+ end // if (wr_ready_i)
+ end // case: WRITING
+
+ endcase // case(state)
+
+ assign dat_to_buf = wr_data_i;
+ assign rd_data_o = dat_from_buf;
+
+ assign rd_flags_o = { rd_occ[1:0], rd_eop, rd_sop };
+ assign rd_ready_o = (state == READING);
+
+ assign wr_sop = wr_flags_i[0];
+ assign wr_eop = wr_flags_i[1];
+ assign wr_occ = wr_flags_i[3:2];
+ assign wr_error = wr_sop & wr_eop;
+ assign wr_ready_o = (state == WRITING);
+
+ assign we_o = (state == WRITING);
+ //assign we_o = (state == WRITING) && wr_ready_i; // always write to
avoid timing issue
+
+ assign en_o = ~((state==READING)& ~rd_ready_i); // FIXME potential
critical path
+
+ assign done = (state == DONE);
+ assign error = (state == ERROR);
+ assign idle = (state == IDLE);
+
+endmodule // buffer_int
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_int_tb.v
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/buffer_int_tb.v)
===================================================================
---
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_int_tb.v
(rev 0)
+++
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_int_tb.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,418 @@
+
+module buffer_int_tb ();
+
+ reg clk = 0;
+ reg rst = 1;
+
+ initial #100 rst = 0;
+ always #5 clk = ~clk;
+
+ wire en, we;
+ wire [8:0] addr;
+ wire [31:0] fifo2buf, buf2fifo;
+
+ wire [31:0] rd_data_o;
+ wire [3:0] rd_flags_o;
+ wire rd_sop_o, rd_eop_o;
+ reg rd_error_i = 0, rd_read_i = 0;
+
+ reg [31:0] wr_data_i = 0;
+ wire [3:0] wr_flags_i;
+ reg wr_eop_i = 0, wr_sop_i = 0;
+ reg wr_write_i = 0;
+ wire wr_ready_o, wr_full_o;
+
+ reg clear = 0, write = 0, read = 0;
+ reg [8:0] firstline = 0, lastline = 0;
+ wire [3:0] step = 1;
+ wire [31:0] ctrl_word =
{4'b0,3'b0,clear,write,read,step,lastline,firstline};
+ reg go = 0;
+ wire done, error;
+
+ assign wr_flags_i = {2'b00, wr_eop_i, wr_sop_i};
+ assign rd_sop_o = rd_flags_o[0];
+ assign rd_eop_o = rd_flags_o[1];
+
+ buffer_int buffer_int
+ (.clk(clk),.rst(rst),
+ .ctrl_word(ctrl_word),.go(go),
+ .done(done),.error(error),
+
+ // Buffer Interface
+ .en_o(en),.we_o(we),.addr_o(addr),
+ .dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo),
+
+ // Write FIFO Interface
+ .wr_data_i(wr_data_i), .wr_flags_i(wr_flags_i), .wr_write_i(wr_write_i),
.wr_ready_o(wr_ready_o),
+
+ // Read FIFO Interface
+ .rd_data_o(rd_data_o), .rd_flags_o(rd_flags_o), .rd_ready_o(rd_ready_o),
.rd_read_i(rd_read_i)
+ );
+
+ reg ram_en = 0, ram_we = 0;
+ reg [8:0] ram_addr = 0;
+ reg [31:0] ram_data = 0;
+
+ ram_2port #(.DWIDTH(32),.AWIDTH(9)) ram_2port
+ (.clka(clk), .ena(ram_en), .wea(ram_we), .addra(ram_addr),
.dia(ram_data), .doa(),
+ .clkb(clk), .enb(en), .web(we), .addrb(addr), .dib(fifo2buf),
.dob(buf2fifo) );
+
+ initial
+ begin
+ @(negedge rst);
+ @(posedge clk);
+ FillRAM;
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing full read, no wait states.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(6,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing full read, 2 wait states.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(6,2);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing partial read, 0 wait states, then nothing after
last.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(3,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing partial read, 0 wait states, then done at same time
as last.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(2,0);
+ ReadALine;
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(5,10);
+ $display("Testing partial read, 3 wait states, then error at same time
as last.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(2,3);
+ rd_error_i <= 1;
+ ReadALine;
+ rd_error_i <= 0;
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(500,511);
+ $display("Testing full read, to the end of the buffer.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(12,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(0,511);
+ $display("Testing full read, start to end of the buffer.");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(512,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(505,3);
+ $display("Testing full read, wraparound");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(11,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(10,15);
+ $display("Testing Full Write, no wait states");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(6,0,72);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(18,23);
+ $display("Testing Full Write, 1 wait states");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(6,1,101);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(27,40);
+ $display("Testing Partial Write, 0 wait states");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(6,0,201);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(45,200);
+ $display("Testing Partial Write, 0 wait states, then done and write
simultaneously");
+ while(!wr_ready_o)
+ @(posedge clk);
+ wr_sop_i <= 1; wr_eop_i <= 0;
+ WriteLines(6,0,301);
+ wr_sop_i <= 0; wr_eop_i <= 1;
+ WriteALine(400);
+ wr_sop_i <= 0; wr_eop_i <= 0;
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(55,200);
+ $display("Testing Partial Write, 0 wait states, then error");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(6,0,501);
+ wr_sop_i <= 1; wr_eop_i <= 1;
+ WriteALine(400);
+ @(posedge clk);
+ repeat (10)
+ @(posedge clk);
+ wr_sop_i <= 0; wr_eop_i <= 0;
+
+ ResetBuffer;
+ SetBufferRead(0,82);
+ $display("Testing read after all the writes");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(83,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(508,4);
+ $display("Testing wraparound write");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(9,0,601);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(506,10);
+ $display("Reading wraparound write");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(17,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferWrite(0,511);
+ $display("Testing Whole Buffer write");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(512,0,1000);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(0,511);
+ $display("Reading Whole Buffer write");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(512,0);
+ repeat (10)
+ @(posedge clk);
+
+ /*
+ ResetBuffer;
+ SetBufferWrite(5,10);
+ $display("Testing Write Too Many");
+ while(!wr_ready_o)
+ @(posedge clk);
+ WriteLines(12,0,2000);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(0,15);
+ $display("Reading back Write Too Many");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(16,0);
+ repeat (10)
+ @(posedge clk);
+ */
+ ResetBuffer;
+ SetBufferWrite(15,20);
+ $display("Testing Write One Less Than Full");
+ while(!wr_ready_o)
+ @(posedge clk);
+ wr_sop_i <= 1; wr_eop_i <= 0;
+ WriteALine(400);
+ wr_sop_i <= 0; wr_eop_i <= 0;
+ WriteLines(3,0,2000);
+ wr_sop_i <= 0; wr_eop_i <= 1;
+ WriteALine(400);
+ wr_sop_i <= 0; wr_eop_i <= 0;
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ SetBufferRead(13,22);
+ $display("Reading back Write One Less Than Full");
+ while(!rd_sop_o)
+ @(posedge clk);
+ ReadLines(10,0);
+ repeat (10)
+ @(posedge clk);
+
+ ResetBuffer;
+ repeat(100)
+ @(posedge clk);
+ $finish;
+ end
+
+ always @(posedge clk)
+ if(rd_read_i == 1'd1)
+ $display("READ Buffer %d, rd_sop_o %d, rd_eop_o %d", rd_data_o,
rd_sop_o, rd_eop_o);
+
+ always @(posedge clk)
+ if(wr_write_i == 1'd1)
+ $display("WRITE Buffer %d, wr_ready_o %d, wr_full_o %d", wr_data_i,
wr_ready_o, wr_full_o);
+
+ initial begin
+ $dumpfile("buffer_int_tb.lxt");
+ $dumpvars(0,buffer_int_tb);
+ end
+
+ task FillRAM;
+ begin
+ ram_addr <= 0;
+ ram_data <= 0;
+ @(posedge clk);
+ ram_en <= 1;
+ ram_we <= 1;
+ @(posedge clk);
+ repeat (511)
+ begin
+ ram_addr <= ram_addr + 1;
+ ram_data <= ram_data + 1;
+ ram_en <= 1;
+ ram_we <= 1;
+ @(posedge clk);
+ end
+ ram_en <= 0;
+ ram_we <= 0;
+ @(posedge clk);
+ $display("Filled the RAM");
+ end
+ endtask // FillRAM
+
+ task ResetBuffer;
+ begin
+ clear <= 1; read <= 0; write <= 0;
+ go <= 1;
+ @(posedge clk);
+ go <= 0;
+ @(posedge clk);
+ $display("Buffer Reset");
+ end
+ endtask // ClearBuffer
+
+ task SetBufferWrite;
+ input [8:0] start;
+ input [8:0] stop;
+ begin
+ clear <= 0; read <= 0; write <= 1;
+ firstline <= start;
+ lastline <= stop;
+ go <= 1;
+ @(posedge clk);
+ go <= 0;
+ @(posedge clk);
+ $display("Buffer Set for Write");
+ end
+ endtask // SetBufferWrite
+
+ task SetBufferRead;
+ input [8:0] start;
+ input [8:0] stop;
+ begin
+ clear <= 0; read <= 1; write <= 0;
+ firstline <= start;
+ lastline <= stop;
+ go <= 1;
+ @(posedge clk);
+ go <= 0;
+ @(posedge clk);
+ $display("Buffer Set for Read");
+ end
+ endtask // SetBufferRead
+
+ task ReadALine;
+ begin
+ while(~rd_ready_o)
+ @(posedge clk);
+ #1 rd_read_i <= 1;
+ @(posedge clk);
+ rd_read_i <= 0;
+ end
+ endtask // ReadALine
+
+ task ReadLines;
+ input [9:0] lines;
+ input [7:0] wait_states;
+ begin
+ $display("Read Lines: Number %d, Wait States %d",lines,wait_states);
+ repeat (lines)
+ begin
+ ReadALine;
+ repeat (wait_states)
+ @(posedge clk);
+ end
+ end
+ endtask // ReadLines
+
+ task WriteALine;
+ input [31:0] value;
+ begin
+ while(~wr_ready_o)
+ @(posedge clk);
+ #1 wr_write_i <= 1;
+ wr_data_i <= value;
+ @(posedge clk);
+ wr_write_i <= 0;
+ end
+ endtask // WriteALine
+
+ task WriteLines;
+ input [9:0] lines;
+ input [7:0] wait_states;
+ input [31:0] value;
+ begin
+ $display("Write Lines: Number %d, Wait States %d",lines,wait_states);
+ repeat(lines)
+ begin
+ value <= value + 1;
+ WriteALine(value);
+ repeat(wait_states)
+ @(posedge clk);
+ end
+ end
+ endtask // WriteLines
+
+endmodule // buffer_int_tb
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_pool.v
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/buffer_pool.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_pool.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_pool.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,283 @@
+
+// Buffer pool. Contains 8 buffers, each 2K (512 by 32). Each buffer
+// is a dual-ported RAM. Port A on each of them is indirectly connected
+// to the wishbone bus by a bridge. Port B may be connected any one of the
+// 8 (4 rd, 4 wr) FIFO-like streaming interaces, or disconnected. The
wishbone bus
+// provides access to all 8 buffers, and also controls the connections
+// between the ports and the buffers, allocating them as needed.
+
+// wb_adr is 16 bits --
+// bits 13:11 select which buffer
+// bits 10:2 select line in buffer
+// bits 1:0 are unused (32-bit access only)
+
+// BUF_SIZE is in address lines (i.e. log2 of number of lines).
+// For S3 it should be 9 (512 words, 2KB)
+// For V5 it should be at least 10 (1024 words, 4KB) or 11 (2048 words, 8KB)
+
+module buffer_pool
+ #(parameter BUF_SIZE = 9,
+ parameter SET_ADDR = 64)
+ (input wb_clk_i,
+ input wb_rst_i,
+ input wb_we_i,
+ input wb_stb_i,
+ input [15:0] wb_adr_i,
+ input [31:0] wb_dat_i,
+ output [31:0] wb_dat_o,
+ output reg wb_ack_o,
+ output wb_err_o,
+ output wb_rty_o,
+
+ input stream_clk,
+ input stream_rst,
+
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+ output [31:0] status,
+ output sys_int_o,
+
+ output [31:0] s0, output [31:0] s1, output [31:0] s2, output [31:0] s3,
+ output [31:0] s4, output [31:0] s5, output [31:0] s6, output [31:0] s7,
+
+ // Write Interfaces
+ input [31:0] wr0_data_i, input [3:0] wr0_flags_i, input wr0_ready_i,
output wr0_ready_o,
+ input [31:0] wr1_data_i, input [3:0] wr1_flags_i, input wr1_ready_i,
output wr1_ready_o,
+ input [31:0] wr2_data_i, input [3:0] wr2_flags_i, input wr2_ready_i,
output wr2_ready_o,
+ input [31:0] wr3_data_i, input [3:0] wr3_flags_i, input wr3_ready_i,
output wr3_ready_o,
+
+ // Read Interfaces
+ output [31:0] rd0_data_o, output [3:0] rd0_flags_o, output rd0_ready_o,
input rd0_ready_i,
+ output [31:0] rd1_data_o, output [3:0] rd1_flags_o, output rd1_ready_o,
input rd1_ready_i,
+ output [31:0] rd2_data_o, output [3:0] rd2_flags_o, output rd2_ready_o,
input rd2_ready_i,
+ output [31:0] rd3_data_o, output [3:0] rd3_flags_o, output rd3_ready_o,
input rd3_ready_i
+ );
+
+ wire [7:0] sel_a;
+
+ wire [BUF_SIZE-1:0] buf_addra = wb_adr_i[BUF_SIZE+1:2]; //
ignore address 1:0, 32-bit access only
+ wire [2:0] which_buf = wb_adr_i[BUF_SIZE+4:BUF_SIZE+2]; //
address 15:14 selects the buffer pool
+
+ decoder_3_8 dec(.sel(which_buf),.res(sel_a));
+
+ genvar i;
+
+ wire go;
+
+ reg [2:0] port[0:7];
+ reg [3:0] read_src[0:3];
+ reg [3:0] write_src[0:3];
+
+ wire [7:0] done;
+ wire [7:0] error;
+ wire [7:0] idle;
+
+ wire [31:0] buf_doa[0:7];
+
+ wire [7:0] buf_enb;
+ wire [7:0] buf_web;
+ wire [BUF_SIZE-1:0] buf_addrb[0:7];
+ wire [31:0] buf_dib[0:7];
+ wire [31:0] buf_dob[0:7];
+
+ wire [31:0] wr_data_i[0:7];
+ wire [3:0] wr_flags_i[0:7];
+ wire [7:0] wr_ready_i;
+ wire [7:0] wr_ready_o;
+
+ wire [31:0] rd_data_o[0:7];
+ wire [3:0] rd_flags_o[0:7];
+ wire [7:0] rd_ready_o;
+ wire [7:0] rd_ready_i;
+
+ assign status = {8'd0,idle[7:0],error[7:0],done[7:0]};
+
+ assign s0 = buf_addrb[0];
+ assign s1 = buf_addrb[1];
+ assign s2 = buf_addrb[2];
+ assign s3 = buf_addrb[3];
+ assign s4 = buf_addrb[4];
+ assign s5 = buf_addrb[5];
+ assign s6 = buf_addrb[6];
+ assign s7 = buf_addrb[7];
+
+ wire [31:0] fifo_ctrl;
+ setting_reg #(.my_addr(SET_ADDR))
+
sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),
+ .out(fifo_ctrl),.changed(go));
+
+ integer k;
+ always @(posedge stream_clk)
+ if(stream_rst)
+ for(k=0;k<8;k=k+1)
+ port[k] <= 4; // disabled
+ else
+ for(k=0;k<8;k=k+1)
+ if(go & (fifo_ctrl[31:28]==k))
+ port[k] <= fifo_ctrl[27:25];
+
+ always @(posedge stream_clk)
+ if(stream_rst)
+ for(k=0;k<4;k=k+1)
+ read_src[k] <= 8; // disabled
+ else
+ for(k=0;k<4;k=k+1)
+ if(go & fifo_ctrl[22] & (fifo_ctrl[27:25]==k))
+ read_src[k] <= fifo_ctrl[31:28];
+
+ always @(posedge stream_clk)
+ if(stream_rst)
+ for(k=0;k<4;k=k+1)
+ write_src[k] <= 8; // disabled
+ else
+ for(k=0;k<4;k=k+1)
+ if(go & fifo_ctrl[23] & (fifo_ctrl[27:25]==k))
+ write_src[k] <= fifo_ctrl[31:28];
+
+ generate
+ for(i=0;i<8;i=i+1)
+ begin : gen_buffer
+ RAMB16_S36_S36 dpram
+
(.DOA(buf_doa[i]),.ADDRA(buf_addra),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0),
+ .ENA(wb_stb_i & sel_a[i]),.SSRA(0),.WEA(wb_we_i),
+
.DOB(buf_dob[i]),.ADDRB(buf_addrb[i]),.CLKB(stream_clk),.DIB(buf_dib[i]),.DIPB(4'h0),
+ .ENB(buf_enb[i]),.SSRB(0),.WEB(buf_web[i]) );
+
+/*
+ ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer
+ (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i),
+ .addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]),
+ .clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]),
+ .addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i]));
+
+ */
+
+ buffer_int #(.BUF_NUM(i),.BUF_SIZE(BUF_SIZE)) buffer_int
+ (.clk(stream_clk),.rst(stream_rst),
+ .ctrl_word(fifo_ctrl),.go(go & (fifo_ctrl[31:28]==i)),
+ .done(done[i]),.error(error[i]),.idle(idle[i]),
+ .en_o(buf_enb[i]),
+ .we_o(buf_web[i]),
+ .addr_o(buf_addrb[i]),
+ .dat_to_buf(buf_dib[i]),
+ .dat_from_buf(buf_dob[i]),
+ .wr_data_i(wr_data_i[i]),
+ .wr_flags_i(wr_flags_i[i]),
+ .wr_ready_i(wr_ready_i[i]),
+ .wr_ready_o(wr_ready_o[i]),
+ .rd_data_o(rd_data_o[i]),
+ .rd_flags_o(rd_flags_o[i]),
+ .rd_ready_o(rd_ready_o[i]),
+ .rd_ready_i(rd_ready_i[i]) );
+ mux4 #(.WIDTH(37))
+ mux4_wr (.en(~port[i][2]),.sel(port[i][1:0]),
+ .i0({wr0_data_i,wr0_flags_i,wr0_ready_i}),
+ .i1({wr1_data_i,wr1_flags_i,wr1_ready_i}),
+ .i2({wr2_data_i,wr2_flags_i,wr2_ready_i}),
+ .i3({wr3_data_i,wr3_flags_i,wr3_ready_i}),
+ .o({wr_data_i[i],wr_flags_i[i],wr_ready_i[i]}) );
+ mux4 #(.WIDTH(1))
+ mux4_rd (.en(~port[i][2]),.sel(port[i][1:0]),
+
.i0(rd0_ready_i),.i1(rd1_ready_i),.i2(rd2_ready_i),.i3(rd3_ready_i),
+ .o(rd_ready_i[i]));
+ end // block: gen_buffer
+ endgenerate
+
+ //----------------------------------------------------------------------
+ // Wishbone Outputs
+
+ // Use the following lines if ram output and mux can be made fast enough
+
+ assign wb_err_o = 1'b0; // Unused for now
+ assign wb_rty_o = 1'b0; // Unused for now
+
+ always @(posedge wb_clk_i)
+ wb_ack_o <= wb_stb_i & ~wb_ack_o;
+ assign wb_dat_o = buf_doa[which_buf];
+
+ // Use this if we can't make the RAM+MUX fast enough
+ // reg [31:0] wb_dat_o_reg;
+ // reg stb_d1;
+
+ // always @(posedge wb_clk_i)
+ // begin
+ // wb_dat_o_reg <= buf_doa[which_buf];
+ // stb_d1 <= wb_stb_i;
+ // wb_ack_o <= (stb_d1 & ~wb_ack_o) | (wb_we_i & wb_stb_i);
+ // end
+ //assign wb_dat_o = wb_dat_o_reg;
+
+ mux8 #(.WIDTH(1))
+ mux8_wr0(.en(~write_src[0][3]),.sel(write_src[0][2:0]),
+ .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]),
.i3(wr_ready_o[3]),
+ .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]),
.i7(wr_ready_o[7]),
+ .o(wr0_ready_o));
+
+ mux8 #(.WIDTH(1))
+ mux8_wr1(.en(~write_src[1][3]),.sel(write_src[1][2:0]),
+ .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]),
.i3(wr_ready_o[3]),
+ .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]),
.i7(wr_ready_o[7]),
+ .o(wr1_ready_o));
+
+ mux8 #(.WIDTH(1))
+ mux8_wr2(.en(~write_src[2][3]),.sel(write_src[2][2:0]),
+ .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]),
.i3(wr_ready_o[3]),
+ .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]),
.i7(wr_ready_o[7]),
+ .o(wr2_ready_o));
+
+ mux8 #(.WIDTH(1))
+ mux8_wr3(.en(~write_src[3][3]),.sel(write_src[3][2:0]),
+ .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]),
.i3(wr_ready_o[3]),
+ .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]),
.i7(wr_ready_o[7]),
+ .o(wr3_ready_o));
+
+ mux8 #(.WIDTH(37))
+ mux8_rd0(.en(~read_src[0][3]),.sel(read_src[0][2:0]),
+ .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}),
+ .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}),
+ .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}),
+ .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}),
+ .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}),
+ .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}),
+ .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}),
+ .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}),
+ .o({rd0_data_o,rd0_flags_o,rd0_ready_o}));
+
+ mux8 #(.WIDTH(37))
+ mux8_rd1(.en(~read_src[1][3]),.sel(read_src[1][2:0]),
+ .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}),
+ .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}),
+ .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}),
+ .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}),
+ .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}),
+ .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}),
+ .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}),
+ .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}),
+ .o({rd1_data_o,rd1_flags_o,rd1_ready_o}));
+
+ mux8 #(.WIDTH(37))
+ mux8_rd2(.en(~read_src[2][3]),.sel(read_src[2][2:0]),
+ .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}),
+ .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}),
+ .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}),
+ .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}),
+ .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}),
+ .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}),
+ .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}),
+ .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}),
+ .o({rd2_data_o,rd2_flags_o,rd2_ready_o}));
+
+ mux8 #(.WIDTH(37))
+ mux8_rd3(.en(~read_src[3][3]),.sel(read_src[3][2:0]),
+ .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}),
+ .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}),
+ .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}),
+ .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}),
+ .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}),
+ .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}),
+ .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}),
+ .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}),
+ .o({rd3_data_o,rd3_flags_o,rd3_ready_o}));
+
+ assign sys_int_o = (|error) | (|done);
+
+endmodule // buffer_pool
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_pool_tb.v
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/buffer_pool_tb.v)
===================================================================
---
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_pool_tb.v
(rev 0)
+++
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/buffer_pool_tb.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,58 @@
+
+module buffer_pool_tb();
+
+ wire wb_clk_i;
+ wire wb_rst_i;
+ wire wb_we_i;
+ wire wb_stb_i;
+ wire [15:0] wb_adr_i;
+ wire [31:0] wb_dat_i;
+ wire [31:0] wb_dat_o;
+ wire wb_ack_o;
+ wire wb_err_o;
+ wire wb_rty_o;
+
+ wire stream_clk, stream_rst;
+
+ wire set_stb;
+ wire [7:0] set_addr;
+ wire [31:0] set_data;
+
+ wire [31:0] wr0_data, wr1_data, wr2_data, wr3_data;
+ wire [31:0] rd0_data, rd1_data, rd2_data, rd3_data;
+ wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags;
+ wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags;
+ wire wr0_ready, wr1_ready, wr2_ready, wr3_ready;
+ wire rd0_ready, rd1_ready, rd2_ready, rd3_ready;
+ wire wr0_write, wr1_write, wr2_write, wr3_write;
+ wire rd0_read, rd1_read, rd2_read, rd3_read;
+
+ buffer_pool dut
+ (.wb_clk_i(wb_clk_i),
+ .wb_rst_i(wb_rst_i),
+ .wb_we_i(wb_we_i),
+ .wb_stb_i(wb_stb_i),
+ .wb_adr_i(wb_adr_i),
+ .wb_dat_i(wb_dat_i),
+ .wb_dat_o(wb_dat_o),
+ .wb_ack_o(wb_ack_o),
+ .wb_err_o(wb_err_o),
+ .wb_rty_o(wb_rty_o),
+
+ .stream_clk(stream_clk),
+ .stream_rst(stream_rst),
+
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+
+ .wr0_data_i(wr0_data), .wr0_write_i(wr0_write), .wr0_flags_i(wr0_flags),
.wr0_ready_o(wr0_ready),
+ .wr1_data_i(wr1_data), .wr1_write_i(wr1_write), .wr1_flags_i(wr1_flags),
.wr1_ready_o(wr1_ready),
+ .wr2_data_i(wr2_data), .wr2_write_i(wr2_write), .wr2_flags_i(wr2_flags),
.wr2_ready_o(wr2_ready),
+ .wr3_data_i(wr3_data), .wr3_write_i(wr3_write), .wr3_flags_i(wr3_flags),
.wr3_ready_o(wr3_ready),
+
+ .rd0_data_o(rd0_data), .rd0_read_i(rd0_read), .rd0_flags_o(rd0_flags),
.rd0_ready_o(rd0_ready),
+ .rd1_data_o(rd1_data), .rd1_read_i(rd1_read), .rd1_flags_o(rd1_flags),
.rd1_ready_o(rd1_ready),
+ .rd2_data_o(rd2_data), .rd2_read_i(rd2_read), .rd2_flags_o(rd2_flags),
.rd2_ready_o(rd2_ready),
+ .rd3_data_o(rd3_data), .rd3_read_i(rd3_read), .rd3_flags_o(rd3_flags),
.rd3_ready_o(rd3_ready)
+ );
+
+endmodule // buffer_pool_tb
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo18_to_ll8.v
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/fifo18_to_ll8.v)
===================================================================
---
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo18_to_ll8.v
(rev 0)
+++
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo18_to_ll8.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,58 @@
+
+module fifo18_to_ll8
+ (input clk, input reset, input clear,
+ input [35:0] f18_data,
+ input f18_src_rdy_i,
+ output f18_dst_rdy_o,
+
+ output reg [7:0] ll_data,
+ output ll_sof_n,
+ output ll_eof_n,
+ output ll_src_rdy_n,
+ input ll_dst_rdy_n);
+
+ wire ll_sof, ll_eof, ll_src_rdy;
+ assign ll_sof_n = ~ll_sof;
+ assign ll_eof_n = ~ll_eof;
+ assign ll_src_rdy_n = ~ll_src_rdy;
+ wire ll_dst_rdy = ~ll_dst_rdy_n;
+
+ wire f18_sof = f18_data[32];
+ wire f18_eof = f18_data[33];
+ wire f18_occ = f18_data[35:34];
+ wire advance, end_early;
+ reg [1:0] state;
+ assign debug = {29'b0,state};
+
+ always @(posedge clk)
+ if(reset)
+ state <= 0;
+ else
+ if(advance)
+ if(ll_eof)
+ state <= 0;
+ else
+ state <= state + 1;
+
+ always @*
+ case(state)
+ 0 : ll_data = f18_data[31:24];
+ 1 : ll_data = f18_data[23:16];
+ 2 : ll_data = f18_data[15:8];
+ 3 : ll_data = f18_data[7:0];
+ default : ll_data = f18_data[31:24];
+ endcase // case (state)
+
+ assign ll_sof = (state==0) & f18_sof;
+ assign ll_eof = f18_eof & (((state==0)&(f18_occ==1)) |
+ ((state==1)&(f18_occ==2)) |
+ ((state==2)&(f18_occ==3)) |
+ (state==3));
+
+ assign ll_src_rdy = f18_src_rdy_i;
+
+ assign advance = ll_src_rdy & ll_dst_rdy;
+ assign f18_dst_rdy_o = advance & ((state==3)|ll_eof);
+ assign debug = state;
+
+endmodule // ll8_to_fifo36
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo19_to_fifo36.v
(from rev 10710,
gnuradio/trunk/usrp2/fpga/control_lib/newfifo/fifo19_to_fifo36.v)
===================================================================
---
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo19_to_fifo36.v
(rev 0)
+++
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo19_to_fifo36.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,71 @@
+
+module fifo19_to_fifo36
+ (input clk, input reset, input clear,
+ input [18:0] f19_datain,
+ input f19_src_rdy_i,
+ output f19_dst_rdy_o,
+
+ output [35:0] f36_dataout,
+ output f36_src_rdy_o,
+ input f36_dst_rdy_i
+ );
+
+ reg f36_sof, f36_eof, f36_occ;
+
+ reg [1:0] state;
+ reg [15:0] dat0, dat1;
+
+ wire f19_sof = f19_datain[16];
+ wire f19_eof = f19_datain[17];
+ wire f19_occ = f19_datain[18];
+
+ wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
+
+ always @(posedge clk)
+ if(f19_src_rdy_i & ((state==0)|xfer_out))
+ f36_sof <= f19_sof;
+
+ always @(posedge clk)
+ if(f19_src_rdy_i & ((state != 2)|xfer_out))
+ f36_eof <= f19_eof;
+
+ always @(posedge clk) // FIXME check this
+ if(f19_eof)
+ f36_occ <= {state[0],f19_occ};
+ else
+ f36_occ <= 0;
+
+ always @(posedge clk)
+ if(reset)
+ state <= 0;
+ else
+ if(f19_src_rdy_i)
+ case(state)
+ 0 :
+ if(f19_eof)
+ state <= 2;
+ else
+ state <= 1;
+ 1 :
+ state <= 2;
+ 2 :
+ if(xfer_out)
+ state <= 1;
+ endcase // case(state)
+ else
+ if(xfer_out)
+ state <= 0;
+
+ always @(posedge clk)
+ if(f19_src_rdy_i & (state==1))
+ dat1 <= f19_datain;
+
+ always @(posedge clk)
+ if(f19_src_rdy_i & ((state==0) | xfer_out))
+ dat0 <= f19_datain;
+
+ assign f19_dst_rdy_o = xfer_out | (state != 2);
+ assign f36_dataout = {f36_occ,f36_eof,f36_sof,dat0,dat1};
+ assign f36_src_rdy_o = (state == 2);
+
+endmodule // fifo19_to_fifo36
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo19_to_ll8.v
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/fifo19_to_ll8.v)
===================================================================
---
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo19_to_ll8.v
(rev 0)
+++
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo19_to_ll8.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,53 @@
+
+module fifo19_to_ll8
+ (input clk, input reset, input clear,
+ input [18:0] f19_data,
+ input f19_src_rdy_i,
+ output f19_dst_rdy_o,
+
+ output reg [7:0] ll_data,
+ output ll_sof_n,
+ output ll_eof_n,
+ output ll_src_rdy_n,
+ input ll_dst_rdy_n);
+
+ wire ll_sof, ll_eof, ll_src_rdy;
+ assign ll_sof_n = ~ll_sof;
+ assign ll_eof_n = ~ll_eof;
+ assign ll_src_rdy_n = ~ll_src_rdy;
+ wire ll_dst_rdy = ~ll_dst_rdy_n;
+
+ wire f19_sof = f19_data[16];
+ wire f19_eof = f19_data[17];
+ wire f19_occ = f19_data[18];
+
+ wire advance, end_early;
+ reg state;
+
+ always @(posedge clk)
+ if(reset)
+ state <= 0;
+ else
+ if(advance)
+ if(ll_eof)
+ state <= 0;
+ else
+ state <= state + 1;
+
+ always @*
+ case(state)
+ 0 : ll_data = f19_data[15:8];
+ 1 : ll_data = f19_data[7:0];
+ default : ll_data = f19_data[15:8];
+ endcase // case (state)
+
+ assign ll_sof = (state==0) & f19_sof;
+ assign ll_eof = f19_eof & ((f19_occ==1)|(state==1));
+
+ assign ll_src_rdy = f19_src_rdy_i;
+
+ assign advance = ll_src_rdy & ll_dst_rdy;
+ assign f19_dst_rdy_o = advance & ((state==1)|ll_eof);
+
+endmodule // fifo19_to_ll8
+
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo36_to_fifo18.v
(from rev 10710,
gnuradio/trunk/usrp2/fpga/control_lib/newfifo/fifo36_to_fifo18.v)
===================================================================
---
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo36_to_fifo18.v
(rev 0)
+++
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo36_to_fifo18.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,40 @@
+
+module fifo36_to_fifo18
+ (input clk, input reset, input clear,
+ input [35:0] f36_datain,
+ input f36_src_rdy_i,
+ output f36_dst_rdy_o,
+
+ output [17:0] f18_dataout,
+ output f18_src_rdy_o,
+ input f18_dst_rdy_i );
+
+ wire f36_sof = f36_datain[32];
+ wire f36_eof = f36_datain[33];
+ wire f36_occ = f36_datain[35:34];
+
+ reg phase;
+
+ wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2));
+
+ assign f18_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
+ assign f18_dataout[16] = phase ? 0 : f36_sof;
+ assign f18_dataout[17] = phase ? f36_eof : half_line;
+
+ assign f18_src_rdy_o = f36_src_rdy_i;
+ assign f36_dst_rdy_o = (phase | half_line) & f18_dst_rdy_i;
+
+ wire f18_xfer = f18_src_rdy_o & f18_dst_rdy_i;
+ wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o;
+
+ always @(posedge clk)
+ if(reset)
+ phase <= 0;
+ else if(f36_xfer)
+ phase <= 0;
+ else if(f18_xfer)
+ phase <= 1;
+
+
+endmodule // fifo36_to_fifo18
+
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo36_to_fifo19.v
(from rev 10710,
gnuradio/trunk/usrp2/fpga/control_lib/newfifo/fifo36_to_fifo19.v)
===================================================================
---
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo36_to_fifo19.v
(rev 0)
+++
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo36_to_fifo19.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,41 @@
+
+module fifo36_to_fifo19
+ (input clk, input reset, input clear,
+ input [35:0] f36_datain,
+ input f36_src_rdy_i,
+ output f36_dst_rdy_o,
+
+ output [18:0] f19_dataout,
+ output f19_src_rdy_o,
+ input f19_dst_rdy_i );
+
+ wire f36_sof = f36_datain[32];
+ wire f36_eof = f36_datain[33];
+ wire f36_occ = f36_datain[35:34];
+
+ reg phase;
+
+ wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2));
+
+ assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
+ assign f19_dataout[16] = phase ? 0 : f36_sof;
+ assign f19_dataout[17] = phase ? f36_eof : half_line;
+ assign f19_dataout[18] = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3));
+
+ assign f19_src_rdy_o = f36_src_rdy_i;
+ assign f36_dst_rdy_o = (phase | half_line) & f19_dst_rdy_i;
+
+ wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i;
+ wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o;
+
+ always @(posedge clk)
+ if(reset)
+ phase <= 0;
+ else if(f36_xfer)
+ phase <= 0;
+ else if(f19_xfer)
+ phase <= 1;
+
+
+endmodule // fifo36_to_fifo19
+
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo36_to_ll8.v
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/fifo36_to_ll8.v)
===================================================================
---
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo36_to_ll8.v
(rev 0)
+++
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo36_to_ll8.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,60 @@
+
+module fifo36_to_ll8
+ (input clk, reset,
+ input [35:0] f36_data,
+ input f36_src_rdy_i,
+ output f36_dst_rdy_o,
+
+ output reg [7:0] ll_data,
+ output ll_sof_n,
+ output ll_eof_n,
+ output ll_src_rdy_n,
+ input ll_dst_rdy_n,
+
+ output [31:0] debug);
+
+ wire ll_sof, ll_eof, ll_src_rdy;
+ assign ll_sof_n = ~ll_sof;
+ assign ll_eof_n = ~ll_eof;
+ assign ll_src_rdy_n = ~ll_src_rdy;
+ wire ll_dst_rdy = ~ll_dst_rdy_n;
+
+ wire f36_sof = f36_data[32];
+ wire f36_eof = f36_data[33];
+ wire f36_occ = f36_data[35:34];
+ wire advance, end_early;
+ reg [1:0] state;
+ assign debug = {29'b0,state};
+
+ always @(posedge clk)
+ if(reset)
+ state <= 0;
+ else
+ if(advance)
+ if(ll_eof)
+ state <= 0;
+ else
+ state <= state + 1;
+
+ always @*
+ case(state)
+ 0 : ll_data = f36_data[31:24];
+ 1 : ll_data = f36_data[23:16];
+ 2 : ll_data = f36_data[15:8];
+ 3 : ll_data = f36_data[7:0];
+ default : ll_data = f36_data[31:24];
+ endcase // case (state)
+
+ assign ll_sof = (state==0) & f36_sof;
+ assign ll_eof = f36_eof & (((state==0)&(f36_occ==1)) |
+ ((state==1)&(f36_occ==2)) |
+ ((state==2)&(f36_occ==3)) |
+ (state==3));
+
+ assign ll_src_rdy = f36_src_rdy_i;
+
+ assign advance = ll_src_rdy & ll_dst_rdy;
+ assign f36_dst_rdy_o = advance & ((state==3)|ll_eof);
+ assign debug = state;
+
+endmodule // ll8_to_fifo36
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_2clock.v
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/fifo_2clock.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_2clock.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_2clock.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,66 @@
+
+module fifo_2clock
+ #(parameter DWIDTH=32, AWIDTH=9)
+ (input wclk, input [DWIDTH-1:0] datain, input write, output full, output
reg [AWIDTH-1:0] level_wclk,
+ input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output
reg [AWIDTH-1:0] level_rclk,
+ input arst);
+
+ reg [AWIDTH-1:0] wr_addr, rd_addr;
+ wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk;
+ wire [AWIDTH-1:0] next_rd_addr;
+ wire enb_read;
+
+ // Write side management
+ wire [AWIDTH-1:0] next_wr_addr = wr_addr + 1;
+ always @(posedge wclk or posedge arst)
+ if(arst)
+ wr_addr <= 0;
+ else if(write)
+ wr_addr <= next_wr_addr;
+ assign full = (next_wr_addr == rd_addr_wclk);
+
+ // RAM for data storage. Data out is registered, complicating the
+ // read side logic
+ ram_2port #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) mac_rx_ff_ram
+ (.clka(wclk),.ena(1'b1),.wea(write),.addra(wr_addr),.dia(datain),.doa(),
+
.clkb(rclk),.enb(enb_read),.web(1'b0),.addrb(next_rd_addr),.dib(0),.dob(dataout)
);
+
+ // Read side management
+ reg data_valid;
+ assign empty = ~data_valid;
+ assign next_rd_addr = rd_addr + data_valid;
+ assign enb_read = read | ~data_valid;
+
+ always @(posedge rclk or posedge arst)
+ if(arst)
+ rd_addr <= 0;
+ else if(read)
+ rd_addr <= rd_addr + 1;
+
+ always @(posedge rclk or posedge arst)
+ if(arst)
+ data_valid <= 0;
+ else
+ if(read & (next_rd_addr == wr_addr_rclk))
+ data_valid <= 0;
+ else if(next_rd_addr != wr_addr_rclk)
+ data_valid <= 1;
+
+ // Send pointers across clock domains via gray code
+ gray_send #(.WIDTH(AWIDTH)) send_wr_addr
+ (.clk_in(wclk),.addr_in(wr_addr),
+ .clk_out(rclk),.addr_out(wr_addr_rclk) );
+
+ gray_send #(.WIDTH(AWIDTH)) send_rd_addr
+ (.clk_in(rclk),.addr_in(rd_addr),
+ .clk_out(wclk),.addr_out(rd_addr_wclk) );
+
+ // Generate fullness info, these are approximate and may be delayed
+ // and are only for higher-level flow control.
+ // Only full and empty are guaranteed exact.
+ always @(posedge wclk)
+ level_wclk <= wr_addr - rd_addr_wclk;
+ always @(posedge rclk)
+ level_rclk <= wr_addr_rclk - rd_addr;
+
+endmodule // fifo_2clock
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_2clock_casc.v
(from rev 10710,
gnuradio/trunk/usrp2/fpga/control_lib/newfifo/fifo_2clock_casc.v)
===================================================================
---
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_2clock_casc.v
(rev 0)
+++
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_2clock_casc.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,31 @@
+
+module fifo_2clock_casc
+ #(parameter DWIDTH=32, AWIDTH=9)
+ (input wclk, input [DWIDTH-1:0] datain, input write, output full, output
[AWIDTH-1:0] level_wclk,
+ input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output
[AWIDTH-1:0] level_rclk,
+ input arst);
+
+ wire full_int, empty_int, full_int2, empty_int2, transfer, transfer2;
+ wire [DWIDTH-1:0] data_int, data_int2;
+
+ shortfifo #(.WIDTH(DWIDTH)) shortfifo
+ (.clk(wclk), .rst(arst), .clear(0),
+ .datain(datain), .write(write), .full(full),
+ .dataout(data_int), .read(transfer), .empty(empty_int) );
+
+ assign transfer = ~full_int & ~empty_int;
+
+ fifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
+ (.wclk(wclk), .datain(data_int), .write(transfer), .full(full_int),
.level_wclk(level_wclk),
+ .rclk(rclk), .dataout(data_int2), .read(transfer2), .empty(empty_int2),
.level_rclk(level_rclk),
+ .arst(arst) );
+
+ assign transfer2 = ~full_int2 & ~empty_int2;
+
+ shortfifo #(.WIDTH(DWIDTH)) shortfifo2
+ (.clk(rclk), .rst(arst), .clear(0),
+ .datain(data_int2), .write(transfer2), .full(full_int2),
+ .dataout(dataout), .read(read), .empty(empty) );
+
+endmodule // fifo_2clock_casc
+
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_cascade.v
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/fifo_cascade.v)
===================================================================
---
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_cascade.v
(rev 0)
+++
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_cascade.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,52 @@
+
+
+// This FIFO exists to provide an intermediate point for the data on its
+// long trek from one RAM (in the buffer pool) to another (in the longfifo)
+// The shortfifo is more flexible in its placement since it is based on
+// distributed RAM
+
+// This one has the shortfifo on both the in and out sides.
+module fifo_cascade
+ #(parameter WIDTH=32, SIZE=9)
+ (input clk, input reset, input clear,
+ input [WIDTH-1:0] datain,
+ input src_rdy_i,
+ output dst_rdy_o,
+ output [WIDTH-1:0] dataout,
+ output src_rdy_o,
+ input dst_rdy_i,
+ output [15:0] space,
+ output [15:0] occupied);
+
+ wire [WIDTH-1:0] data_int, data_int2;
+ wire src_rdy_1, dst_rdy_1, src_rdy_2, dst_rdy_2;
+
+ wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied;
+ wire [15:0] l_space, l_occupied;
+
+ fifo_short #(.WIDTH(WIDTH)) head_fifo
+ (.clk(clk),.reset(reset),.clear(clear),
+ .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+ .dataout(data_int), .src_rdy_o(src_rdy_1), .dst_rdy_i(dst_rdy_1),
+ .space(s1_space),.occupied(s1_occupied) );
+
+ fifo_long #(.WIDTH(WIDTH),.SIZE(SIZE)) middle_fifo
+ (.clk(clk),.reset(reset),.clear(clear),
+ .datain(data_int), .src_rdy_i(src_rdy_1), .dst_rdy_o(dst_rdy_1),
+ .dataout(data_int2), .src_rdy_o(src_rdy_2), .dst_rdy_i(dst_rdy_2),
+ .space(l_space),.occupied(l_occupied) );
+
+ fifo_short #(.WIDTH(WIDTH)) tail_fifo
+ (.clk(clk),.reset(reset),.clear(clear),
+ .datain(data_int2), .src_rdy_i(src_rdy_2), .dst_rdy_o(dst_rdy_2),
+ .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
+ .space(s2_space),.occupied(s2_occupied) );
+
+ assign space = {11'b0,s1_space} + {11'b0,s2_space} + l_space;
+ assign occupied = {11'b0,s1_occupied} + {11'b0,s2_occupied} +
l_occupied;
+
+endmodule // cascadefifo2
+
+
+
+
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_long.v (from
rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/fifo_long.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_long.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_long.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,148 @@
+
+// FIFO intended to be interchangeable with shortfifo, but
+// based on block ram instead of SRL16's
+// only one clock domain
+
+// Port A is write port, Port B is read port
+
+module fifo_long
+ #(parameter WIDTH=32, SIZE=9)
+ (input clk, input reset, input clear,
+ input [WIDTH-1:0] datain,
+ input src_rdy_i,
+ output dst_rdy_o,
+ output [WIDTH-1:0] dataout,
+ output src_rdy_o,
+ input dst_rdy_i,
+
+ output reg [15:0] space,
+ output reg [15:0] occupied);
+
+ wire write = src_rdy_i & dst_rdy_o;
+ wire read = dst_rdy_i & src_rdy_o;
+ wire full, empty;
+
+ assign dst_rdy_o = ~full;
+ assign src_rdy_o = ~empty;
+
+ // Read side states
+ localparam EMPTY = 0;
+ localparam PRE_READ = 1;
+ localparam READING = 2;
+
+ reg [SIZE-1:0] wr_addr, rd_addr;
+ reg [1:0] read_state;
+
+ reg empty_reg, full_reg;
+ always @(posedge clk)
+ if(reset)
+ wr_addr <= 0;
+ else if(clear)
+ wr_addr <= 0;
+ else if(write)
+ wr_addr <= wr_addr + 1;
+
+ ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
+ ram (.clka(clk),
+ .ena(1'b1),
+ .wea(write),
+ .addra(wr_addr),
+ .dia(datain),
+ .doa(),
+
+ .clkb(clk),
+ .enb((read_state==PRE_READ)|read),
+ .web(0),
+ .addrb(rd_addr),
+ .dib(0),
+ .dob(dataout));
+
+ always @(posedge clk)
+ if(reset)
+ begin
+ read_state <= EMPTY;
+ rd_addr <= 0;
+ empty_reg <= 1;
+ end
+ else
+ if(clear)
+ begin
+ read_state <= EMPTY;
+ rd_addr <= 0;
+ empty_reg <= 1;
+ end
+ else
+ case(read_state)
+ EMPTY :
+ if(write)
+ begin
+ //rd_addr <= wr_addr;
+ read_state <= PRE_READ;
+ end
+ PRE_READ :
+ begin
+ read_state <= READING;
+ empty_reg <= 0;
+ rd_addr <= rd_addr + 1;
+ end
+
+ READING :
+ if(read)
+ if(rd_addr == wr_addr)
+ begin
+ empty_reg <= 1;
+ if(write)
+ read_state <= PRE_READ;
+ else
+ read_state <= EMPTY;
+ end
+ else
+ rd_addr <= rd_addr + 1;
+ endcase // case(read_state)
+
+ wire [SIZE-1:0] dont_write_past_me = rd_addr - 3;
+ wire becoming_full = wr_addr == dont_write_past_me;
+
+ always @(posedge clk)
+ if(reset)
+ full_reg <= 0;
+ else if(clear)
+ full_reg <= 0;
+ else if(read & ~write)
+ full_reg <= 0;
+ //else if(write & ~read & (wr_addr == (rd_addr-3)))
+ else if(write & ~read & becoming_full)
+ full_reg <= 1;
+
+ //assign empty = (read_state != READING);
+ assign empty = empty_reg;
+
+ // assign full = ((rd_addr - 1) == wr_addr);
+ assign full = full_reg;
+
+ //////////////////////////////////////////////
+ // space and occupied are for diagnostics only
+ // not guaranteed exact
+
+ localparam NUMLINES = (1<<SIZE)-2;
+ always @(posedge clk)
+ if(reset)
+ space <= NUMLINES;
+ else if(clear)
+ space <= NUMLINES;
+ else if(read & ~write)
+ space <= space + 1;
+ else if(write & ~read)
+ space <= space - 1;
+
+ always @(posedge clk)
+ if(reset)
+ occupied <= 0;
+ else if(clear)
+ occupied <= 0;
+ else if(read & ~write)
+ occupied <= occupied - 1;
+ else if(write & ~read)
+ occupied <= occupied + 1;
+
+endmodule // fifo_long
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_new_tb.v
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/fifo_new_tb.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_new_tb.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_new_tb.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,158 @@
+module fifo_new_tb();
+
+ reg clk = 0;
+ reg rst = 1;
+ reg clear = 0;
+ initial #1000 rst = 0;
+ always #50 clk = ~clk;
+
+ reg [31:0] f36_data = 0;
+ reg [1:0] f36_occ = 0;
+ reg f36_sof = 0, f36_eof = 0;
+
+ wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
+ reg src_rdy_f36i = 0;
+ wire dst_rdy_f36i;
+
+ wire [35:0] f36_out, f36_out2;
+ wire src_rdy_f36o;
+ reg dst_rdy_f36o = 0;
+
+ //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+ //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+
+ wire i1_sr, i1_dr;
+ wire i2_sr, i2_dr;
+ wire i3_sr, i3_dr;
+ reg i4_dr = 0;
+ wire i4_sr;
+
+ wire [35:0] i1, i4;
+ wire [18:0] i2, i3;
+
+ wire [7:0] ll_data;
+ wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
+
+ fifo_short #(.WIDTH(36)) fifo_short1
+ (.clk(clk),.reset(rst),.clear(clear),
+ .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
+ .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
+
+ fifo36_to_fifo19 fifo36_to_fifo19
+ (.clk(clk),.reset(rst),.clear(clear),
+ .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
+ .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) );
+
+ fifo19_to_ll8 fifo19_to_ll8
+ (.clk(clk),.reset(rst),.clear(clear),
+ .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr),
+ .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+ .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n));
+
+ ll8_to_fifo19 ll8_to_fifo19
+ (.clk(clk),.reset(rst),.clear(clear),
+ .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+ .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n),
+ .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) );
+
+ fifo19_to_fifo36 fifo19_to_fifo36
+ (.clk(clk),.reset(rst),.clear(clear),
+ .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
+ .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
+
+ task ReadFromFIFO36;
+ begin
+ $display("Read from FIFO36");
+ #1 i4_dr <= 1;
+ while(1)
+ begin
+ while(~i4_sr)
+ @(posedge clk);
+ $display("Read: %h",i4);
+ @(posedge clk);
+ end
+ end
+ endtask // ReadFromFIFO36
+
+ reg [15:0] count;
+ task PutPacketInFIFO36;
+ input [31:0] data_start;
+ input [31:0] data_len;
+ begin
+ count <= 4;
+ src_rdy_f36i <= 1;
+ f36_data <= data_start;
+ f36_sof <= 1;
+ f36_eof <= 0;
+ f36_occ <= 0;
+
+ $display("Put Packet in FIFO36");
+ while(~dst_rdy_f36i)
+ @(posedge clk);
+ @(posedge clk);
+ $display("PPI_FIFO36: Entered First Line");
+ f36_sof <= 0;
+ while(count+4 < data_len)
+ begin
+ f36_data <= f36_data + 32'h01010101;
+ count <= count + 4;
+ while(~dst_rdy_f36i)
+ @(posedge clk);
+ @(posedge clk);
+ $display("PPI_FIFO36: Entered New Line");
+ end
+ f36_data <= f36_data + 32'h01010101;
+ f36_eof <= 1;
+ if(count + 4 == data_len)
+ f36_occ <= 0;
+ else if(count + 3 == data_len)
+ f36_occ <= 3;
+ else if(count + 2 == data_len)
+ f36_occ <= 2;
+ else
+ f36_occ <= 1;
+ while(~dst_rdy_f36i)
+ @(posedge clk);
+ @(posedge clk);
+ f36_occ <= 0;
+ f36_eof <= 0;
+ f36_data <= 0;
+ src_rdy_f36i <= 0;
+ $display("PPI_FIFO36: Entered Last Line");
+ end
+ endtask // PutPacketInFIFO36
+
+ initial $dumpfile("fifo_new_tb.vcd");
+ initial $dumpvars(0,fifo_new_tb);
+
+ initial
+ begin
+ @(negedge rst);
+ //#10000;
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ ReadFromFIFO36;
+ end
+
+ initial
+ begin
+ @(negedge rst);
+ @(posedge clk);
+ @(posedge clk);
+ PutPacketInFIFO36(32'hA0B0C0D0,12);
+ @(posedge clk);
+ @(posedge clk);
+ #10000;
+ @(posedge clk);
+ PutPacketInFIFO36(32'hE0F0A0B0,36);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ end
+
+ initial #20000 $finish;
+endmodule // longfifo_tb
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_new_tb.vcd
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/fifo_new_tb.vcd)
===================================================================
---
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_new_tb.vcd
(rev 0)
+++
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_new_tb.vcd
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,5506 @@
+$date
+ Thu Mar 19 17:21:11 2009
+$end
+$version
+ Icarus Verilog
+$end
+$timescale
+ 1ps
+$end
+$scope module fifo_new_tb $end
+$var wire 1 ! dst_rdy_f36i $end
+$var wire 36 " f36_in [35:0] $end
+$var wire 36 # i1 [35:0] $end
+$var wire 1 $ i1_dr $end
+$var wire 1 % i1_sr $end
+$var wire 19 & i2 [18:0] $end
+$var wire 1 ' i2_dr $end
+$var wire 1 ( i2_sr $end
+$var wire 19 ) i3 [18:0] $end
+$var wire 1 * i3_dr $end
+$var wire 1 + i3_sr $end
+$var wire 36 , i4 [35:0] $end
+$var wire 1 - i4_sr $end
+$var wire 8 . ll_data [7:0] $end
+$var wire 1 / ll_dst_rdy_n $end
+$var wire 1 0 ll_eof_n $end
+$var wire 1 1 ll_sof_n $end
+$var wire 1 2 ll_src_rdy_n $end
+$var reg 1 3 clear $end
+$var reg 1 4 clk $end
+$var reg 16 5 count [15:0] $end
+$var reg 1 6 dst_rdy_f36o $end
+$var reg 32 7 f36_data [31:0] $end
+$var reg 1 8 f36_eof $end
+$var reg 2 9 f36_occ [1:0] $end
+$var reg 1 : f36_sof $end
+$var reg 1 ; i4_dr $end
+$var reg 1 < rst $end
+$var reg 1 = src_rdy_f36i $end
+$scope module fifo_short1 $end
+$var wire 1 > clear $end
+$var wire 1 ? clk $end
+$var wire 36 @ datain [35:0] $end
+$var wire 36 A dataout [35:0] $end
+$var wire 1 $ dst_rdy_i $end
+$var wire 1 ! dst_rdy_o $end
+$var wire 1 B read $end
+$var wire 1 C reset $end
+$var wire 1 D src_rdy_i $end
+$var wire 1 % src_rdy_o $end
+$var wire 1 E write $end
+$var reg 4 F a [3:0] $end
+$var reg 1 G empty $end
+$var reg 1 H full $end
+$var reg 5 I occupied [4:0] $end
+$var reg 5 J space [4:0] $end
+$scope begin gen_srl16[0] $end
+$scope module srl16e $end
+$var wire 1 K A0 $end
+$var wire 1 L A1 $end
+$var wire 1 M A2 $end
+$var wire 1 N A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 O D $end
+$var wire 1 P Q $end
+$var reg 16 Q data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[1] $end
+$scope module srl16e $end
+$var wire 1 R A0 $end
+$var wire 1 S A1 $end
+$var wire 1 T A2 $end
+$var wire 1 U A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 V D $end
+$var wire 1 W Q $end
+$var reg 16 X data [15:0] $end
+$upscope $end
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+$scope begin gen_srl16[2] $end
+$scope module srl16e $end
+$var wire 1 Y A0 $end
+$var wire 1 Z A1 $end
+$var wire 1 [ A2 $end
+$var wire 1 \ A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 ] D $end
+$var wire 1 ^ Q $end
+$var reg 16 _ data [15:0] $end
+$upscope $end
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+$scope begin gen_srl16[3] $end
+$scope module srl16e $end
+$var wire 1 ` A0 $end
+$var wire 1 a A1 $end
+$var wire 1 b A2 $end
+$var wire 1 c A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 d D $end
+$var wire 1 e Q $end
+$var reg 16 f data [15:0] $end
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+$scope begin gen_srl16[4] $end
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+$var wire 1 g A0 $end
+$var wire 1 h A1 $end
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+$var wire 1 j A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 k D $end
+$var wire 1 l Q $end
+$var reg 16 m data [15:0] $end
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+$scope begin gen_srl16[5] $end
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+$var wire 1 n A0 $end
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+$var wire 1 q A3 $end
+$var wire 1 E CE $end
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+$var wire 1 r D $end
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+$var wire 1 x A3 $end
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+$var wire 1 !" A3 $end
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+$var wire 1 "" D $end
+$var wire 1 #" Q $end
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+$var wire 1 (" A3 $end
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+$var wire 1 )" D $end
+$var wire 1 *" Q $end
+$var reg 16 +" data [15:0] $end
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+$var wire 1 6" A3 $end
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+$var wire 1 =" A3 $end
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+$var wire 1 D" A3 $end
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+$var wire 1 H" A0 $end
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+$var wire 1 K" A3 $end
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+$var wire 1 ? CLK $end
+$var wire 1 L" D $end
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+$var wire 1 Q" A2 $end
+$var wire 1 R" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 S" D $end
+$var wire 1 T" Q $end
+$var reg 16 U" data [15:0] $end
+$upscope $end
+$upscope $end
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+$var wire 1 V" A0 $end
+$var wire 1 W" A1 $end
+$var wire 1 X" A2 $end
+$var wire 1 Y" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 Z" D $end
+$var wire 1 [" Q $end
+$var reg 16 \" data [15:0] $end
+$upscope $end
+$upscope $end
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+$scope module srl16e $end
+$var wire 1 ]" A0 $end
+$var wire 1 ^" A1 $end
+$var wire 1 _" A2 $end
+$var wire 1 `" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 a" D $end
+$var wire 1 b" Q $end
+$var reg 16 c" data [15:0] $end
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+$var wire 1 d" A0 $end
+$var wire 1 e" A1 $end
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+$var wire 1 g" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 h" D $end
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+$var reg 16 j" data [15:0] $end
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+$var wire 1 m" A2 $end
+$var wire 1 n" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 o" D $end
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+$var wire 1 t" A2 $end
+$var wire 1 u" A3 $end
+$var wire 1 E CE $end
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+$var wire 1 z" A1 $end
+$var wire 1 {" A2 $end
+$var wire 1 |" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 }" D $end
+$var wire 1 ~" Q $end
+$var reg 16 !# data [15:0] $end
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+$var wire 1 ## A1 $end
+$var wire 1 $# A2 $end
+$var wire 1 %# A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 &# D $end
+$var wire 1 '# Q $end
+$var reg 16 (# data [15:0] $end
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+$var wire 1 *# A1 $end
+$var wire 1 +# A2 $end
+$var wire 1 ,# A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 -# D $end
+$var wire 1 .# Q $end
+$var reg 16 /# data [15:0] $end
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+$var wire 1 0# A0 $end
+$var wire 1 1# A1 $end
+$var wire 1 2# A2 $end
+$var wire 1 3# A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 4# D $end
+$var wire 1 5# Q $end
+$var reg 16 6# data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[24] $end
+$scope module srl16e $end
+$var wire 1 7# A0 $end
+$var wire 1 8# A1 $end
+$var wire 1 9# A2 $end
+$var wire 1 :# A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 ;# D $end
+$var wire 1 <# Q $end
+$var reg 16 =# data [15:0] $end
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+$var wire 1 ># A0 $end
+$var wire 1 ?# A1 $end
+$var wire 1 @# A2 $end
+$var wire 1 A# A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 B# D $end
+$var wire 1 C# Q $end
+$var reg 16 D# data [15:0] $end
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+$var wire 1 G# A2 $end
+$var wire 1 H# A3 $end
+$var wire 1 E CE $end
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+$var wire 1 E CE $end
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+$var wire 1 }# A0 $end
+$var wire 1 ~# A1 $end
+$var wire 1 !$ A2 $end
+$var wire 1 "$ A3 $end
+$var wire 1 E CE $end
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+$var wire 1 '$ A1 $end
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+$var wire 1 )$ A3 $end
+$var wire 1 E CE $end
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+$var wire 1 *$ D $end
+$var wire 1 +$ Q $end
+$var reg 16 ,$ data [15:0] $end
+$upscope $end
+$upscope $end
+$upscope $end
+$scope module fifo36_to_fifo19 $end
+$var wire 1 > clear $end
+$var wire 1 ? clk $end
+$var wire 19 -$ f19_dataout [18:0] $end
+$var wire 1 ' f19_dst_rdy_i $end
+$var wire 1 ( f19_src_rdy_o $end
+$var wire 1 .$ f19_xfer $end
+$var wire 36 /$ f36_datain [35:0] $end
+$var wire 1 $ f36_dst_rdy_o $end
+$var wire 1 0$ f36_eof $end
+$var wire 1 1$ f36_occ $end
+$var wire 1 2$ f36_sof $end
+$var wire 1 % f36_src_rdy_i $end
+$var wire 1 3$ f36_xfer $end
+$var wire 1 4$ half_line $end
+$var wire 1 C reset $end
+$var reg 1 5$ phase $end
+$upscope $end
+$scope module fifo19_to_ll8 $end
+$var wire 1 6$ advance $end
+$var wire 1 > clear $end
+$var wire 1 ? clk $end
+$var wire 19 7$ f19_data [18:0] $end
+$var wire 1 ' f19_dst_rdy_o $end
+$var wire 1 8$ f19_eof $end
+$var wire 1 9$ f19_occ $end
+$var wire 1 :$ f19_sof $end
+$var wire 1 ( f19_src_rdy_i $end
+$var wire 1 ;$ ll_dst_rdy $end
+$var wire 1 / ll_dst_rdy_n $end
+$var wire 1 <$ ll_eof $end
+$var wire 1 0 ll_eof_n $end
+$var wire 1 =$ ll_sof $end
+$var wire 1 1 ll_sof_n $end
+$var wire 1 >$ ll_src_rdy $end
+$var wire 1 2 ll_src_rdy_n $end
+$var wire 1 C reset $end
+$var reg 8 ?$ ll_data [7:0] $end
+$var reg 1 @$ state $end
+$upscope $end
+$scope module ll8_to_fifo19 $end
+$var wire 1 > clear $end
+$var wire 1 ? clk $end
+$var wire 19 A$ f19_data [18:0] $end
+$var wire 1 * f19_dst_rdy_i $end
+$var wire 1 + f19_src_rdy_o $end
+$var wire 8 B$ ll_data [7:0] $end
+$var wire 1 C$ ll_dst_rdy $end
+$var wire 1 / ll_dst_rdy_n $end
+$var wire 1 D$ ll_eof $end
+$var wire 1 0 ll_eof_n $end
+$var wire 1 E$ ll_sof $end
+$var wire 1 1 ll_sof_n $end
+$var wire 1 F$ ll_src_rdy $end
+$var wire 1 2 ll_src_rdy_n $end
+$var wire 1 C reset $end
+$var wire 1 G$ xfer_out $end
+$var reg 8 H$ dat0 [7:0] $end
+$var reg 8 I$ dat1 [7:0] $end
+$var reg 1 J$ f19_eof $end
+$var reg 1 K$ f19_occ $end
+$var reg 1 L$ f19_sof $end
+$var reg 2 M$ state [1:0] $end
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+$var wire 1 > clear $end
+$var wire 1 ? clk $end
+$var wire 19 N$ f19_datain [18:0] $end
+$var wire 1 * f19_dst_rdy_o $end
+$var wire 1 O$ f19_eof $end
+$var wire 1 P$ f19_occ $end
+$var wire 1 Q$ f19_sof $end
+$var wire 1 + f19_src_rdy_i $end
+$var wire 36 R$ f36_dataout [35:0] $end
+$var wire 1 S$ f36_dst_rdy_i $end
+$var wire 1 - f36_src_rdy_o $end
+$var wire 1 C reset $end
+$var wire 1 T$ xfer_out $end
+$var reg 16 U$ dat0 [15:0] $end
+$var reg 16 V$ dat1 [15:0] $end
+$var reg 1 W$ f36_eof $end
+$var reg 1 X$ f36_occ $end
+$var reg 1 Y$ f36_sof $end
+$var reg 2 Z$ state [1:0] $end
+$upscope $end
+$scope task PutPacketInFIFO36 $end
+$var reg 32 [$ data_len [31:0] $end
+$var reg 32 \$ data_start [31:0] $end
+$upscope $end
+$scope task ReadFromFIFO36 $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
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Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_short.v
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/fifo_short.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_short.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_short.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,95 @@
+
+module fifo_short
+ #(parameter WIDTH=32)
+ (input clk, input reset, input clear,
+ input [WIDTH-1:0] datain,
+ input src_rdy_i,
+ output dst_rdy_o,
+ output [WIDTH-1:0] dataout,
+ output src_rdy_o,
+ input dst_rdy_i,
+
+ output reg [4:0] space,
+ output reg [4:0] occupied);
+
+ reg full, empty;
+ wire write = src_rdy_i & dst_rdy_o;
+ wire read = dst_rdy_i & src_rdy_o;
+
+ assign dst_rdy_o = ~full;
+ assign src_rdy_o = ~empty;
+
+ reg [3:0] a;
+ genvar i;
+
+ generate
+ for (i=0;i<WIDTH;i=i+1)
+ begin : gen_srl16
+ SRL16E
+ srl16e(.Q(dataout[i]),
+ .A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),
+ .CE(write),.CLK(clk),.D(datain[i]));
+ end
+ endgenerate
+
+ always @(posedge clk)
+ if(reset)
+ begin
+ a <= 0;
+ empty <= 1;
+ full <= 0;
+ end
+ else if(clear)
+ begin
+ a <= 0;
+ empty <= 1;
+ full<= 0;
+ end
+ else if(read & ~write)
+ begin
+ full <= 0;
+ if(a==0)
+ empty <= 1;
+ else
+ a <= a - 1;
+ end
+ else if(write & ~read)
+ begin
+ empty <= 0;
+ if(~empty)
+ a <= a + 1;
+ if(a == 14)
+ full <= 1;
+ end
+
+ // NOTE will fail if you write into a full fifo or read from an empty one
+
+ //////////////////////////////////////////////////////////////
+ // space and occupied are used for diagnostics, not
+ // guaranteed correct
+
+ //assign space = full ? 0 : empty ? 16 : 15-a;
+ //assign occupied = empty ? 0 : full ? 16 : a+1;
+
+ always @(posedge clk)
+ if(reset)
+ space <= 16;
+ else if(clear)
+ space <= 16;
+ else if(read & ~write)
+ space <= space + 1;
+ else if(write & ~read)
+ space <= space - 1;
+
+ always @(posedge clk)
+ if(reset)
+ occupied <= 0;
+ else if(clear)
+ occupied <= 0;
+ else if(read & ~write)
+ occupied <= occupied - 1;
+ else if(write & ~read)
+ occupied <= occupied + 1;
+
+endmodule // fifo_short
+
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_spec.txt
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/fifo_spec.txt)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_spec.txt
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_spec.txt
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,36 @@
+
+
+FIFO and Buffer Interface Spec
+
+Buffer Interface Data Wires -- matches fifo36
+ DATA[31:0]
+ FLAGS[3:0]
+ Bit 0 SOP
+ Bit 1 EOP
+ If SOP=1 && EOP=1, OCC contains error flags
+ Bits 3:2 OCC[1:0] --> 00 = all 4 bytes
+ 01 = 1 byte
+ 10 = 2 bytes
+ 11 = 3 bytes
+
+fifo36 --> {OCC[1:0],EOP,SOP,DATA[31:0]}
+ OCC same as buffer interface
+
+fifo19 --> {OCC,EOP,SOP,DATA[15:0]}
+ Doesn't fit well into BRAM, dist RAM ok
+ OCC = 1 means last word is half full
+ = 0 means last word is full
+
+fifo18 --> {EOP,SOP,DATA[15:0]}
+ No half-word capability? Should we drop sop instead?
+
+Control Wires - Data into FIFO
+ SRC_RDY_i Upstream has data for me
+ DST_RDY_o I have space
+ Transfer occurs if SRC_RDI_i && DST_RDY_o
+
+Control Wires - Data out of FIFO
+ SRC_RDY_o I have data for downstream
+ DST_RDY_i Downstream has space
+ Transfer occurs if SRC_RDI_o && DST_RDY_i
+
Copied: gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_tb.v
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/fifo_tb.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_tb.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/fifo_tb.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,155 @@
+module fifo_tb();
+
+ reg clk, rst;
+ wire short_full, short_empty, long_full, long_empty;
+ wire casc_full, casc_empty, casc2_full, casc2_empty;
+ reg read, write;
+
+ wire [7:0] short_do, long_do;
+ wire [7:0] casc_do, casc2_do;
+ reg [7:0] di;
+
+ reg clear = 0;
+
+ shortfifo #(.WIDTH(8)) shortfifo
+ (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear),
+ .read(read),.write(write),.full(short_full),.empty(short_empty));
+
+ longfifo #(.WIDTH(8), .SIZE(4)) longfifo
+ (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear),
+ .read(read),.write(write),.full(long_full),.empty(long_empty));
+
+ cascadefifo #(.WIDTH(8), .SIZE(4)) cascadefifo
+ (.clk(clk),.rst(rst),.datain(di),.dataout(casc_do),.clear(clear),
+ .read(read),.write(write),.full(casc_full),.empty(casc_empty));
+
+ cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2
+ (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear),
+ .read(read),.write(write),.full(casc2_full),.empty(casc2_empty));
+
+ initial rst = 1;
+ initial #1000 rst = 0;
+ initial clk = 0;
+ always #50 clk = ~clk;
+
+ initial di = 8'hAE;
+ initial read = 0;
+ initial write = 0;
+
+ always @(posedge clk)
+ if(write)
+ di <= di + 1;
+
+ always @(posedge clk)
+ begin
+ if(short_full != long_full)
+ $display("Error: FULL mismatch");
+ if(short_empty != long_empty)
+ $display("Note: EMPTY mismatch, usually not a problem (longfifo has 2
cycle latency)");
+ if(read & (short_do != long_do))
+ $display("Error: DATA mismatch");
+ end
+
+ initial $dumpfile("fifo_tb.vcd");
+ initial $dumpvars(0,fifo_tb);
+
+ initial
+ begin
+ @(negedge rst);
+ @(posedge clk);
+ repeat (10)
+ @(posedge clk);
+ write <= 1;
+ @(posedge clk);
+ write <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ read <= 1;
+ @(posedge clk);
+ read <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+
+ repeat(10)
+ begin
+ write <= 1;
+ @(posedge clk);
+ write <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ read <= 1;
+ @(posedge clk);
+ read <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ end // repeat (10)
+
+ write <= 1;
+ repeat (4)
+ @(posedge clk);
+ write <= 0;
+ @(posedge clk);
+ read <= 1;
+ repeat (4)
+ @(posedge clk);
+ read <= 0;
+ @(posedge clk);
+
+
+ write <= 1;
+ repeat (4)
+ @(posedge clk);
+ write <= 0;
+ @(posedge clk);
+ repeat (4)
+ begin
+ read <= 1;
+ @(posedge clk);
+ read <= 0;
+ @(posedge clk);
+ end
+
+ write <= 1;
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ @(posedge clk);
+ read <= 1;
+ repeat (5)
+ @(posedge clk);
+ write <= 0;
+ @(posedge clk);
+ @(posedge clk);
+ read <= 0;
+ @(posedge clk);
+
+ write <= 1;
+ repeat (16)
+ @(posedge clk);
+ write <= 0;
+ @(posedge clk);
+
+ read <= 1;
+ repeat (16)
+ @(posedge clk);
+ read <= 0;
+ @(posedge clk);
+
+ repeat (10)
+ @(posedge clk);
+ $finish;
+ end
+endmodule // longfifo_tb
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/ll8_to_fifo19.v
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/ll8_to_fifo19.v)
===================================================================
---
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/ll8_to_fifo19.v
(rev 0)
+++
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/ll8_to_fifo19.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,77 @@
+
+module ll8_to_fifo19
+ (input clk, input reset, input clear,
+ input [7:0] ll_data,
+ input ll_sof_n,
+ input ll_eof_n,
+ input ll_src_rdy_n,
+ output ll_dst_rdy_n,
+
+ output [18:0] f19_data,
+ output f19_src_rdy_o,
+ input f19_dst_rdy_i );
+
+ // Why anybody would use active low in an FPGA is beyond me...
+ wire ll_sof = ~ll_sof_n;
+ wire ll_eof = ~ll_eof_n;
+ wire ll_src_rdy = ~ll_src_rdy_n;
+ wire ll_dst_rdy;
+ assign ll_dst_rdy_n = ~ll_dst_rdy;
+
+ wire xfer_out = f19_src_rdy_o & f19_dst_rdy_i;
+ // wire xfer_in = ll_src_rdy & ll_dst_rdy; Not needed
+
+ reg f19_sof, f19_eof, f19_occ;
+
+ reg [1:0] state;
+ reg [7:0] dat0, dat1;
+
+ always @(posedge clk)
+ if(ll_src_rdy & ((state==0)|xfer_out))
+ f19_sof <= ll_sof;
+
+ always @(posedge clk)
+ if(ll_src_rdy & ((state != 2)|xfer_out))
+ f19_eof <= ll_eof;
+
+ always @(posedge clk)
+ if(ll_eof)
+ f19_occ <= ~state[0];
+ else
+ f19_occ <= 0;
+
+ always @(posedge clk)
+ if(reset)
+ state <= 0;
+ else
+ if(ll_src_rdy)
+ case(state)
+ 0 :
+ if(ll_eof)
+ state <= 2;
+ else
+ state <= 1;
+ 1 :
+ state <= 2;
+ 2 :
+ if(xfer_out)
+ state <= 1;
+ endcase // case(state)
+ else
+ if(xfer_out)
+ state <= 0;
+
+ always @(posedge clk)
+ if(ll_src_rdy & (state==1))
+ dat1 <= ll_data;
+
+ always @(posedge clk)
+ if(ll_src_rdy & ((state==0) | xfer_out))
+ dat0 <= ll_data;
+
+ assign ll_dst_rdy = xfer_out | (state != 2);
+ assign f19_data = {f19_occ,f19_eof,f19_sof,dat0,dat1};
+ assign f19_src_rdy_o = (state == 2);
+
+endmodule // ll8_to_fifo19
+
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/ll8_to_fifo36.v
(from rev 10710, gnuradio/trunk/usrp2/fpga/control_lib/newfifo/ll8_to_fifo36.v)
===================================================================
---
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/ll8_to_fifo36.v
(rev 0)
+++
gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/newfifo/ll8_to_fifo36.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,94 @@
+
+module ll8_to_fifo36
+ (input clk, reset,
+ input [7:0] ll_data,
+ input ll_sof_n,
+ input ll_eof_n,
+ input ll_src_rdy_n,
+ output ll_dst_rdy_n,
+
+ output [35:0] f36_data,
+ output f36_src_rdy_o,
+ input f36_dst_rdy_i );
+
+ wire f36_full = ~f36_dst_rdy_i;
+ wire f36_write = f36_src_rdy_o & f36_dst_rdy_i;
+
+ // Why anybody would use active low in an FPGA is beyond me...
+ wire ll_sof = ~ll_sof_n;
+ wire ll_eof = ~ll_eof_n;
+ wire ll_src_rdy = ~ll_src_rdy_n;
+ wire ll_dst_rdy;
+ assign ll_dst_rdy_n = ~ll_dst_rdy;
+
+ reg f36_sof, f36_eof;
+ reg [1:0] f36_occ;
+
+
+ reg [2:0] state;
+ reg [7:0] dat0, dat1, dat2, dat3;
+
+ always @(posedge clk)
+ if(ll_src_rdy & ((state==0)|f36_write))
+ f36_sof <= ll_sof;
+
+ always @(posedge clk)
+ if(ll_src_rdy & ((state !=4)|f36_write))
+ f36_eof <= ll_eof;
+
+ always @(posedge clk)
+ if(ll_eof)
+ f36_occ <= state[1:0];
+ else
+ f36_occ <= 0;
+
+ always @(posedge clk)
+ if(reset)
+ state <= 0;
+ else
+ if(ll_src_rdy)
+ case(state)
+ 0 :
+ if(ll_eof)
+ state <= 4;
+ else
+ state <= 1;
+ 1 :
+ if(ll_eof)
+ state <= 4;
+ else
+ state <= 2;
+ 2 :
+ if(ll_eof)
+ state <= 4;
+ else
+ state <= 3;
+ 3 : state <= 4;
+ 4 : if(~f36_full)
+ state <= 1;
+ endcase // case(state)
+ else
+ if(f36_write)
+ state <= 0;
+
+ always @(posedge clk)
+ if(ll_src_rdy & (state==3))
+ dat3 <= ll_data;
+
+ always @(posedge clk)
+ if(ll_src_rdy & (state==2))
+ dat2 <= ll_data;
+
+ always @(posedge clk)
+ if(ll_src_rdy & (state==1))
+ dat1 <= ll_data;
+
+ always @(posedge clk)
+ if(ll_src_rdy & ((state==0) | f36_write))
+ dat0 <= ll_data;
+
+ assign ll_dst_rdy = ~f36_full | (state != 4);
+ assign f36_data = {f36_occ,f36_eof,f36_sof,dat0,dat1,dat2,dat3};
// FIXME endianess
+ assign f36_src_rdy_o = (state == 4);
+
+endmodule // ll8_to_fifo36
Copied: gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/reset_sync.v
(from rev 10762, gnuradio/trunk/usrp2/fpga/control_lib/reset_sync.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/reset_sync.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/control_lib/reset_sync.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,16 @@
+
+
+module reset_sync
+ (input clk,
+ input reset_in,
+ output reg reset_out);
+
+ reg reset_int;
+
+ always @(posedge clk or posedge reset_in)
+ if(reset_in)
+ {reset_out,reset_int} <= 2'b11;
+ else
+ {reset_out,reset_int} <= {reset_int,1'b0};
+
+endmodule // reset_sync
Modified: gnuradio/branches/releases/3.2/usrp2/fpga/eth/mac_rxfifo_int.v
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/eth/mac_rxfifo_int.v
2009-04-14 19:31:57 UTC (rev 10829)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/eth/mac_rxfifo_int.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -32,13 +32,24 @@
// Write side of short FIFO
assign write = ~full & ~Rx_mac_empty;
assign Rx_mac_rd = write;
+
+`define LONGFIFO 0
+`ifdef LONGFIFO
+ cascadefifo2 #(.WIDTH(35),.SIZE(10)) mac_rx_longfifo
+ (.clk(clk),.rst(rst),.clear(0),
+
.datain({Rx_mac_sop,Rx_mac_eop,Rx_mac_err,Rx_mac_data}),.write(write),.full(full),
+ .dataout({sop_o,eop_o,error_o,wr_dat_o}),.read(read),.empty(empty),
+ .space(), .occupied(fifo_occupied) );
+`else
shortfifo #(.WIDTH(35)) mac_rx_sfifo
(.clk(clk),.rst(rst),.clear(0),
.datain({Rx_mac_sop,Rx_mac_eop,Rx_mac_err,Rx_mac_data}),.write(write),.full(full),
.dataout({sop_o,eop_o,error_o,wr_dat_o}),.read(read),.empty(empty),
.space(), .occupied(fifo_occupied[4:0]) );
assign fifo_occupied[15:5] = 0;
+`endif
+
assign fifo_full = full;
assign fifo_empty = empty;
Modified: gnuradio/branches/releases/3.2/usrp2/fpga/eth/rtl/verilog/MAC_top.v
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/eth/rtl/verilog/MAC_top.v
2009-04-14 19:31:57 UTC (rev 10829)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/eth/rtl/verilog/MAC_top.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -137,7 +137,7 @@
wire [15:0] rx_fifo_space;
wire pause_apply, pause_quanta_sub;
wire xon_gen, xoff_gen, xon_gen_complete, xoff_gen_complete;
- wire [15:0] fc_hwmark, fc_lwmark;
+ wire [15:0] fc_hwmark, fc_lwmark, fc_padtime;
//PHY interface
wire [7:0] MTxD;
@@ -332,6 +332,7 @@
.pause_quanta_set ( pause_quanta_set ),
.fc_hwmark (fc_hwmark),
.fc_lwmark (fc_lwmark),
+ .fc_padtime (fc_padtime),
// From RX side
.rx_clk(MAC_rx_clk_div),
.rx_fifo_space (rx_fifo_space), // Decide if we need to send a PAUSE
@@ -342,7 +343,7 @@
.xoff_gen_complete (xoff_gen_complete),
.xon_gen_complete(xon_gen_complete)
);
-
+
RMON U_RMON(
.Clk ( CLK_I ),
.Reset ( RST_I ),
@@ -478,6 +479,7 @@
.tx_pause_en ( tx_pause_en ),
.fc_hwmark ( fc_hwmark ),
.fc_lwmark ( fc_lwmark ),
+ .fc_padtime ( fc_padtime ),
// RMON host interface
.CPU_rd_addr ( CPU_rd_addr ),
@@ -507,7 +509,7 @@
.UpdateMIIRX_DATAReg ( UpdateMIIRX_DATAReg )
);
- assign debug0 = {xon_gen, xoff_gen, Tx_en, Rx_dv};
+ assign debug0 = {xon_gen, xoff_gen, xon_gen_complete,
xoff_gen_complete, debug_rx[3:0]};
//assign debug0 = {{debug_rx[3:0], xon_gen, xon_gen_complete, xoff_gen,
xoff_gen_complete},
//
{1'b0,Rx_mac_err,Rx_mac_empty,Rx_mac_rd,Rx_mac_sop,Rx_mac_eop,Rx_mac_BE[1:0]},
// {rx_fifo_space}};
Modified: gnuradio/branches/releases/3.2/usrp2/fpga/eth/rtl/verilog/Reg_int.v
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/eth/rtl/verilog/Reg_int.v
2009-04-14 19:31:57 UTC (rev 10829)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/eth/rtl/verilog/Reg_int.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -43,6 +43,7 @@
output tx_pause_en,
output [15:0] fc_hwmark,
output [15:0] fc_lwmark,
+ output [15:0] fc_padtime,
// RMON host interface
output [5:0] CPU_rd_addr,
@@ -141,6 +142,9 @@
RegCPUData #( 13 ) U_0_037( MIIADDRESS , 7'd037, 13'h0000,
RST_I, CLK_I, Wr, ADR_I, DAT_I[12:0] );
RegCPUData #( 16 ) U_0_038( MIITX_DATA , 7'd038, 16'h0000,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
+ // New FC register
+ RegCPUData #( 16 ) U_0_041( fc_padtime , 7'd041, 1'h0,
RST_I, CLK_I, Wr, ADR_I, DAT_I[15:0] );
+
// Asserted in first clock of 2-cycle access, negated otherwise
wire Access = ~ACK_O & STB_I & CYC_I;
@@ -231,6 +235,7 @@
7'd38: DAT_O <= MIITX_DATA;
7'd39: DAT_O <= MIIRX_DATA;
7'd40: DAT_O <= MIISTATUS;
+ 7'd41: DAT_O <= fc_padtime;
endcase
end
Modified:
gnuradio/branches/releases/3.2/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v
2009-04-14 19:31:57 UTC (rev 10829)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/eth/rtl/verilog/flow_ctrl_rx.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -8,6 +8,7 @@
input [15:0] pause_quanta_set,
input [15:0] fc_hwmark,
input [15:0] fc_lwmark,
+ input [15:0] fc_padtime,
// From MAC_rx_ctrl
input rx_clk,
input [15:0] rx_fifo_space,
@@ -70,13 +71,13 @@
else if (xon_int | xon_int_d1)
xon_gen <=1;
- wire [15:0] pq_reduced = pause_quanta_set - 2;
+ wire [21:0] pq_reduced = {pause_quanta_set,6'd0} - {6'd0,fc_padtime};
always @(posedge tx_clk or posedge rst)
if(rst)
countdown <= 0;
else if(xoff_gen)
- countdown <= {pq_reduced,6'd0};
+ countdown <= pq_reduced;
else if(xon_gen)
countdown <= 0;
else if(countdown != 0)
Property changes on: gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac
___________________________________________________________________
Added: svn:ignore
+ a.out
*~
*.vcd
Copied: gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/address_filter.v
(from rev 10725, gnuradio/trunk/usrp2/fpga/simple_gemac/address_filter.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/address_filter.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/address_filter.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,35 @@
+
+
+module address_filter
+ (input clk,
+ input reset,
+ input go,
+ input [7:0] data,
+ input [47:0] address,
+ output match,
+ output done);
+
+ reg [2:0] af_state;
+
+ always @(posedge clk)
+ if(reset)
+ af_state <= 0;
+ else
+ if(go)
+ af_state <= (data == address[47:40]) ? 1 : 7;
+ else
+ case(af_state)
+ 1 : af_state <= (data == address[39:32]) ? 2 : 7;
+ 2 : af_state <= (data == address[31:24]) ? 3 : 7;
+ 3 : af_state <= (data == address[23:16]) ? 4 : 7;
+ 4 : af_state <= (data == address[15:8]) ? 5 : 7;
+ 5 : af_state <= (data == address[7:0]) ? 6 : 7;
+ 6, 7 : af_state <= 0;
+ endcase // case (af_state)
+
+ assign match = (af_state==6);
+ assign done = (af_state==6)|(af_state==7);
+
+endmodule // address_filter
+
+
Copied: gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/crc.v (from rev
10721, gnuradio/trunk/usrp2/fpga/simple_gemac/crc.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/crc.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/crc.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,66 @@
+
+module crc
+ (input clk,
+ input reset,
+ input clear,
+ input [7:0] data,
+ input calc,
+ output [31:0] crc_out,
+ output match);
+
+ function[31:0] NextCRC;
+ input[7:0] D;
+ input[31:0] C;
+ reg[31:0] NewCRC;
+ begin
+ NewCRC[0] = C[24]^C[30]^D[1]^D[7];
+ NewCRC[1] = C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
+ NewCRC[2] = C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
+ NewCRC[3] = C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
+ NewCRC[4] = C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
+ NewCRC[5] =
C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
+ NewCRC[6] =
C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
+ NewCRC[7] = C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
+ NewCRC[8] = C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
+ NewCRC[9] = C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
+ NewCRC[10] = C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
+ NewCRC[11] = C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
+ NewCRC[12] =
C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
+ NewCRC[13] =
C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
+ NewCRC[14] =
C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
+ NewCRC[15] = C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
+ NewCRC[16] = C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
+ NewCRC[17] = C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
+ NewCRC[18] = C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
+ NewCRC[19] = C[11]^C[31]^D[0]^C[27]^D[4];
+ NewCRC[20] = C[12]^C[28]^D[3];
+ NewCRC[21] = C[13]^C[29]^D[2];
+ NewCRC[22] = C[14]^C[24]^D[7];
+ NewCRC[23] = C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
+ NewCRC[24] = C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
+ NewCRC[25] = C[17]^C[27]^D[4]^C[26]^D[5];
+ NewCRC[26] = C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
+ NewCRC[27] = C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
+ NewCRC[28] = C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
+ NewCRC[29] = C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
+ NewCRC[30] = C[22]^C[31]^D[0]^C[28]^D[3];
+ NewCRC[31] = C[23]^C[29]^D[2];
+ NextCRC = NewCRC;
+ end
+ endfunction
+
+ reg [31:0] crc_reg;
+ always @ (posedge clk)
+ if (reset | clear)
+ crc_reg <= 32'hffffffff;
+ else if (calc)
+ crc_reg <= NextCRC(data,crc_reg);
+
+ assign crc_out =
~{crc_reg[24],crc_reg[25],crc_reg[26],crc_reg[27],crc_reg[28],crc_reg[29],crc_reg[30],crc_reg[31],
+
crc_reg[16],crc_reg[17],crc_reg[18],crc_reg[19],crc_reg[20],crc_reg[21],crc_reg[22],crc_reg[23],
+
crc_reg[8],crc_reg[9],crc_reg[10],crc_reg[11],crc_reg[12],crc_reg[13],crc_reg[14],crc_reg[15],
+
crc_reg[0],crc_reg[1],crc_reg[2],crc_reg[3],crc_reg[4],crc_reg[5],crc_reg[6],crc_reg[7]
};
+
+ assign match = (crc_reg == 32'hc704_dd7b);
+
+endmodule // crc
Copied: gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/delay_line.v
(from rev 10733, gnuradio/trunk/usrp2/fpga/simple_gemac/delay_line.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/delay_line.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/delay_line.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,21 @@
+
+
+module delay_line
+ #(parameter WIDTH=32)
+ (input clk,
+ input [3:0] delay,
+ input [WIDTH-1:0] din,
+ output [WIDTH-1:0] dout);
+
+ integer i;
+ generate
+ for (i=0;i<WIDTH;i=i+1)
+ begin : gen_delay
+ SRL16E
+ srl16e(.Q(dout[i]),
+ .A0(delay[0]),.A1(delay[1]),.A2(delay[2]),.A3(delay[3]),
+ .CE(1),.CLK(clk),.D(din[i]));
+ end
+ endgenerate
+
+endmodule // delay_line
Copied: gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/eth_tasks.v
(from rev 10744, gnuradio/trunk/usrp2/fpga/simple_gemac/eth_tasks.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/eth_tasks.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/eth_tasks.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,156 @@
+
+
+task SendFlowCtrl;
+ input [15:0] fc_len;
+ begin
+ $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
+ pause_time <= fc_len;
+ @(posedge clk);
+ pause_req <= 1;
+ @(posedge clk);
+ pause_req <= 0;
+ $display("Sent Flow Control");
+ end
+endtask // SendFlowCtrl
+
+task SendPacket2MAC;
+ input tx_clk;
+ input [7:0] data_start;
+ input [31:0] data_len;
+ output [7:0] tx_data;
+ output tx_valid;
+ output tx_error;
+ input tx_ack;
+ reg [15:0] count;
+ begin
+ $display("Sending Packet Len=%d, %d", data_len, $time);
+ count <= 1;
+ tx_data <= data_start;
+ tx_error <= 0;
+ tx_valid <= 1;
+ while(~tx_ack)
+ @(posedge tx_clk);
+ $display("Packet Accepted, %d", $time);
+ while(count < data_len)
+ begin
+ tx_data <= tx_data + 1;
+ count <= count + 1;
+ @(posedge clk);
+ end
+ tx_valid <= 0;
+ @(posedge tx_clk);
+ end
+endtask // SendPacket2MAC
+
+task SendPacket_to_ll8;
+ input [7:0] data_start;
+ input [15:0] data_len;
+// output [7:0] tx_data;
+// output tx_sof;
+// output tx_eof;
+// output tx_src_rdy;
+// input tx_dst_rdy;
+ reg [15:0] count;
+ begin
+ $display("Sending Packet Len=%d, %d", data_len, $time);
+ count <= 2;
+ tx_ll_data2 <= data_start;
+ tx_ll_src_rdy2 <= 1;
+ tx_ll_sof2 <= 1;
+ tx_ll_eof2 <= 0;
+ #1;
+ while(count < data_len)
+ begin
+ while(~tx_ll_dst_rdy2)
+ @(posedge clk);
+ @(posedge clk);
+ tx_ll_data2 = tx_ll_data2 + 1;
+ count = count + 1;
+ tx_ll_sof2 <= 0;
+ end
+ tx_ll_eof2 <= 1;
+ while(~tx_ll_dst_rdy2)
+ @(posedge clk);
+ @(posedge clk);
+ tx_ll_src_rdy2 <= 0;
+ end
+endtask // SendPacket_to_ll8
+
+
+task SendPacketFromFile;
+ input clk;
+ input [31:0] data_len;
+ output [7:0] tx_data;
+ output tx_valid;
+ output tx_error;
+ input tx_ack;
+ reg [15:0] count;
+ begin
+ $display("Sending Packet From File Len=%d, %d",data_len,$time);
+ $readmemh("test_packet.mem",pkt_rom );
+ count = 0;
+ tx_data = pkt_rom[count];
+ tx_error = 0;
+ tx_valid = 1;
+ while(~tx_ack)
+ @(posedge clk);
+ $display("Packet Accepted, %d",$time);
+ count = 1;
+ while(count < data_len)
+ begin
+ tx_data = pkt_rom[count];
+ count = count + 1;
+ @(posedge clk);
+ end
+ tx_valid <= 0;
+ @(posedge clk);
+ end
+endtask // SendPacketFromFile
+
+task Waiter;
+ input [31:0] wait_length;
+ begin
+ tx_ll_src_rdy2 <= 0;
+ repeat(wait_length)
+ @(posedge clk);
+ tx_ll_src_rdy2 <= 1;
+ end
+endtask // Waiter
+
+task SendPacketFromFile_ll8;
+ input [31:0] data_len;
+ input [31:0] wait_length;
+ input [31:0] wait_time;
+
+ integer count;
+ begin
+ $display("Sending Packet From File to LL8 Len=%d, %d",data_len,$time);
+ $readmemh("test_packet.mem",pkt_rom );
+
+ while(~tx_ll_dst_rdy2)
+ @(posedge clk);
+ tx_ll_data2 <= pkt_rom[0];
+ tx_ll_src_rdy2 <= 1;
+ tx_ll_sof2 <= 1;
+ tx_ll_eof2 <= 0;
+ @(posedge clk);
+
+ for(i=1;i<data_len-1;i=i+1)
+ begin
+ while(~tx_ll_dst_rdy2)
+ @(posedge clk);
+ tx_ll_data2 <= pkt_rom[i];
+ tx_ll_sof2 <= 0;
+ @(posedge clk);
+ if(i==wait_time)
+ Waiter(wait_length);
+ end
+
+ while(~tx_ll_dst_rdy2)
+ @(posedge clk);
+ tx_ll_eof2 <= 1;
+ tx_ll_data2 <= pkt_rom[data_len-1];
+ @(posedge clk);
+ tx_ll_src_rdy2 <= 0;
+ end
+endtask // SendPacketFromFile_ll8
Copied: gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/flow_ctrl_rx.v
(from rev 10721, gnuradio/trunk/usrp2/fpga/simple_gemac/flow_ctrl_rx.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/flow_ctrl_rx.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/flow_ctrl_rx.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,85 @@
+
+// RX side of flow control -- when we are running out of RX space, send a PAUSE
+
+module flow_ctrl_rx
+ (input rst,
+ //host processor
+ input pause_frame_send_en,
+ input [15:0] pause_quanta_set,
+ input [15:0] fc_hwmark,
+ input [15:0] fc_lwmark,
+ // From MAC_rx_ctrl
+ input rx_clk,
+ input [15:0] rx_fifo_space,
+ // MAC_tx_ctrl
+ input tx_clk,
+ output reg xoff_gen,
+ output reg xon_gen,
+ input xoff_gen_complete,
+ input xon_gen_complete
+ );
+
+ //
******************************************************************************
+ // Force our TX to send a PAUSE frame because our RX is nearly full
+ //
******************************************************************************
+
+ reg xon_int, xoff_int;
+ reg [21:0] countdown;
+
+ always @(posedge rx_clk or posedge rst)
+ if(rst)
+ begin
+ xon_int <= 0;
+ xoff_int <= 0;
+ end
+ else
+ begin
+ xon_int <= 0;
+ xoff_int <= 0;
+ if(pause_frame_send_en)
+ if(countdown == 0)
+ if(rx_fifo_space < fc_lwmark)
+ xoff_int <= 1;
+ else
+ ;
+ else
+ if(rx_fifo_space > fc_hwmark)
+ xon_int <= 1;
+ end // else: !if(rst)
+
+ reg xoff_int_d1, xon_int_d1;
+
+ always @(posedge rx_clk)
+ xon_int_d1 <= xon_int;
+ always @(posedge rx_clk)
+ xoff_int_d1 <= xoff_int;
+
+ always @ (posedge tx_clk or posedge rst)
+ if (rst)
+ xoff_gen <=0;
+ else if (xoff_gen_complete)
+ xoff_gen <=0;
+ else if (xoff_int | xoff_int_d1)
+ xoff_gen <=1;
+
+ always @ (posedge tx_clk or posedge rst)
+ if (rst)
+ xon_gen <=0;
+ else if (xon_gen_complete)
+ xon_gen <=0;
+ else if (xon_int | xon_int_d1)
+ xon_gen <=1;
+
+ wire [15:0] pq_reduced = pause_quanta_set - 2;
+
+ always @(posedge tx_clk or posedge rst)
+ if(rst)
+ countdown <= 0;
+ else if(xoff_gen)
+ countdown <= {pq_reduced,6'd0};
+ else if(xon_gen)
+ countdown <= 0;
+ else if(countdown != 0)
+ countdown <= countdown - 1;
+
+endmodule // flow_ctrl
Copied: gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/flow_ctrl_tx.v
(from rev 10721, gnuradio/trunk/usrp2/fpga/simple_gemac/flow_ctrl_tx.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/flow_ctrl_tx.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/flow_ctrl_tx.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,39 @@
+
+// TX side of flow control -- when other side sends PAUSE, we wait
+
+module flow_ctrl_tx
+ (input rst,
+ input tx_clk,
+ //host processor
+ input tx_pause_en,
+ // From MAC_rx_ctrl
+ input [15:0] pause_quanta,
+ input pause_quanta_val,
+ // MAC_tx_ctrl
+ output pause_apply,
+ input paused);
+
+ //
******************************************************************************
+ // Inhibit our TX from transmitting because they sent us a PAUSE frame
+ //
******************************************************************************
+
+ // Pauses are in units of 512 bit times, or 64 bytes/clock cycles, and can
be
+ // as big as 16 bits, so 22 bits are needed for the counter
+
+ reg [15+6:0] pause_quanta_counter;
+ reg pqval_d1, pqval_d2;
+
+ always @(posedge tx_clk) pqval_d1 <= pause_quanta_val;
+ always @(posedge tx_clk) pqval_d2 <= pqval_d1;
+
+ always @ (posedge tx_clk or posedge rst)
+ if (rst)
+ pause_quanta_counter <= 0;
+ else if (pqval_d1 & ~pqval_d2)
+ pause_quanta_counter <= {pause_quanta, 6'b0};
+ else if((pause_quanta_counter!=0) & paused)
+ pause_quanta_counter <= pause_quanta_counter - 1;
+
+ assign pause_apply = tx_pause_en & (pause_quanta_counter != 0);
+
+endmodule // flow_ctrl
Copied: gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/ll8_shortfifo.v
(from rev 10744, gnuradio/trunk/usrp2/fpga/simple_gemac/ll8_shortfifo.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/ll8_shortfifo.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/ll8_shortfifo.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,13 @@
+
+
+module ll8_shortfifo
+ (input clk, input reset, input clear,
+ input [7:0] datain, input sof_i, input eof_i, input error_i, input
src_rdy_i, output dst_rdy_o,
+ output [7:0] dataout, output sof_o, output eof_o, output error_o, output
src_rdy_o, input dst_rdy_i);
+
+ fifo_short #(.WIDTH(11)) fifo_short
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i),
.dst_rdy_o(dst_rdy_o),
+ .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o),
.dst_rdy_i(dst_rdy_i));
+
+endmodule // ll8_shortfifo
Copied: gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/ll8_to_txmac.v
(from rev 10744, gnuradio/trunk/usrp2/fpga/simple_gemac/ll8_to_txmac.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/ll8_to_txmac.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/ll8_to_txmac.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,43 @@
+
+module ll8_to_txmac
+ (input clk, input reset, input clear,
+ input [7:0] ll_data, input ll_sof, input ll_eof, input ll_src_rdy, output
ll_dst_rdy,
+ output [7:0] tx_data, output tx_valid, output tx_error, input tx_ack );
+
+ reg [2:0] xfer_state;
+
+ localparam XFER_IDLE = 0;
+ localparam XFER_ACTIVE = 1;
+ localparam XFER_WAIT1 = 2;
+ localparam XFER_UNDERRUN = 3;
+ localparam XFER_DROP = 4;
+
+ always @(posedge clk)
+ if(reset | clear)
+ xfer_state <= XFER_IDLE;
+ else
+ case(xfer_state)
+ XFER_IDLE :
+ if(tx_ack)
+ xfer_state <= XFER_ACTIVE;
+ XFER_ACTIVE :
+ if(~ll_src_rdy)
+ xfer_state <= XFER_UNDERRUN;
+ else if(ll_eof)
+ xfer_state <= XFER_WAIT1;
+ XFER_WAIT1 :
+ xfer_state <= XFER_IDLE;
+ XFER_UNDERRUN :
+ xfer_state <= XFER_DROP;
+ XFER_DROP :
+ if(ll_eof)
+ xfer_state <= XFER_IDLE;
+ endcase // case (xfer_state)
+
+ assign ll_dst_rdy = (xfer_state == XFER_ACTIVE) | tx_ack | (xfer_state
== XFER_DROP);
+ assign tx_valid = (ll_src_rdy & (xfer_state == XFER_IDLE))|(xfer_state
== XFER_ACTIVE);
+ assign tx_data = ll_data;
+ assign tx_error = (xfer_state == XFER_UNDERRUN);
+
+endmodule // ll8_to_txmac
+
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_clockgen.v
(from rev 10762, gnuradio/trunk/usrp2/fpga/simple_gemac/miim/eth_clockgen.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_clockgen.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_clockgen.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,141 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_clockgen.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/projects/ethmac/ ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (address@hidden) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: eth_clockgen.v,v $
+// Revision 1.2 2005/12/13 12:54:49 maverickist
+// first simulation passed
+//
+// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
+// no message
+//
+// Revision 1.2 2005/04/27 15:58:45 Administrator
+// no message
+//
+// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
+// no message
+//
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram
(For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the
end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3 2001/06/01 22:28:55 mohor
+// This files (MIIM) are fully working. They were thoroughly tested. The
testbench is not updated.
+//
+//
+
+module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
+
+//parameter Tp=1;
+
+input Clk; // Input clock (Host clock)
+input Reset; // Reset signal
+input [7:0] Divider; // Divider (input clock will be divided by the
Divider[7:0])
+
+output Mdc; // Output clock
+output MdcEn; // Enable signal is asserted for one Clk period
before Mdc rises.
+output MdcEn_n; // Enable signal is asserted for one Clk period
before Mdc falls.
+
+reg Mdc;
+reg [7:0] Counter;
+
+wire CountEq0;
+wire [7:0] CounterPreset;
+wire [7:0] TempDivider;
+
+
+assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If
smaller than 2
+assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1; // We are
counting half of period
+
+
+// Counter counts half period
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ Counter[7:0] <= 8'h1;
+ else
+ begin
+ if(CountEq0)
+ begin
+ Counter[7:0] <= CounterPreset[7:0];
+ end
+ else
+ Counter[7:0] <= Counter - 8'h1;
+ end
+end
+
+
+// Mdc is asserted every other half period
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ Mdc <= 1'b0;
+ else
+ begin
+ if(CountEq0)
+ Mdc <= ~Mdc;
+ end
+end
+
+
+assign CountEq0 = Counter == 8'h0;
+assign MdcEn = CountEq0 & ~Mdc;
+assign MdcEn_n = CountEq0 & Mdc;
+
+endmodule
+
+
Copied: gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_miim.v
(from rev 10762, gnuradio/trunk/usrp2/fpga/simple_gemac/miim/eth_miim.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_miim.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_miim.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,470 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_miim.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/projects/ethmac/ ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (address@hidden) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: eth_miim.v,v $
+// Revision 1.3 2006/01/19 14:07:53 maverickist
+// verification is complete.
+//
+// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
+// no message
+//
+// Revision 1.4 2005/08/16 12:07:57 Administrator
+// no message
+//
+// Revision 1.3 2005/05/19 07:04:29 Administrator
+// no message
+//
+// Revision 1.2 2005/04/27 15:58:46 Administrator
+// no message
+//
+// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
+// no message
+//
+// Revision 1.5 2003/05/16 10:08:27 mohor
+// Busy was set 2 cycles too late. Reported by Dennis Scott.
+//
+// Revision 1.4 2002/08/14 18:32:10 mohor
+// - Busy signal was not set on time when scan status operation was performed
+// and clock was divided with more than 2.
+// - Nvalid remains valid two more clocks (was previously cleared too soon).
+//
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram
(For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the
end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.2 2001/08/02 09:25:31 mohor
+// Unconnected signals are now connected.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3 2001/06/01 22:28:56 mohor
+// This files (MIIM) are fully working. They were thoroughly tested. The
testbench is not updated.
+//
+//
+
+module eth_miim
+(
+ Clk,
+ Reset,
+ Divider,
+ NoPre,
+ CtrlData,
+ Rgad,
+ Fiad,
+ WCtrlData,
+ RStat,
+ ScanStat,
+ Mdio,
+ Mdc,
+ Busy,
+ Prsd,
+ LinkFail,
+ Nvalid,
+ WCtrlDataStart,
+ RStatStart,
+ UpdateMIIRX_DATAReg
+);
+
+input Clk; // Host Clock
+input Reset; // General Reset
+input [7:0] Divider; // Divider for the host clock
+input [15:0] CtrlData; // Control Data (to be written to the PHY
reg.)
+input [4:0] Rgad; // Register Address (within the PHY)
+input [4:0] Fiad; // PHY Address
+input NoPre; // No Preamble (no 32-bit preamble)
+input WCtrlData; // Write Control Data operation
+input RStat; // Read Status operation
+input ScanStat; // Scan Status operation
+inout Mdio; // MII Management Data In
+
+output Mdc; // MII Management Data Clock
+
+output Busy; // Busy Signal
+output LinkFail; // Link Integrity Signal
+output Nvalid; // Invalid Status (qualifier for the valid
scan result)
+
+output [15:0] Prsd; // Read Status Data (data read from the PHY)
+
+output WCtrlDataStart; // This signals resets the WCTRLDATA bit in
the MIIM Command register
+output RStatStart; // This signal resets the RSTAT BIT in the
MIIM Command register
+output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read
data
+
+//parameter Tp = 1;
+
+
+reg Nvalid;
+reg EndBusy_d; // Pre-end Busy signal
+reg EndBusy; // End Busy signal (stops the operation in
progress)
+
+reg WCtrlData_q1; // Write Control Data operation delayed 1
Clk cycle
+reg WCtrlData_q2; // Write Control Data operation delayed 2
Clk cycles
+reg WCtrlData_q3; // Write Control Data operation delayed 3
Clk cycles
+reg WCtrlDataStart; // Start Write Control Data Command
(positive edge detected)
+reg WCtrlDataStart_q;
+reg WCtrlDataStart_q1; // Start Write Control Data Command delayed
1 Mdc cycle
+reg WCtrlDataStart_q2; // Start Write Control Data Command delayed
2 Mdc cycles
+
+reg RStat_q1; // Read Status operation delayed 1 Clk cycle
+reg RStat_q2; // Read Status operation delayed 2 Clk cycles
+reg RStat_q3; // Read Status operation delayed 3 Clk cycles
+reg RStatStart; // Start Read Status Command (positive edge
detected)
+reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc
cycle
+reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc
cycles
+
+reg ScanStat_q1; // Scan Status operation delayed 1 cycle
+reg ScanStat_q2; // Scan Status operation delayed 2 cycles
+reg SyncStatMdcEn; // Scan Status operation delayed at least
cycles and synchronized to MdcEn
+
+wire WriteDataOp; // Write Data Operation (positive edge
detected)
+wire ReadStatusOp; // Read Status Operation (positive edge
detected)
+wire ScanStatusOp; // Scan Status Operation (positive edge
detected)
+wire StartOp; // Start Operation (start of any of the
preceding operations)
+wire EndOp; // End of Operation
+
+reg InProgress; // Operation in progress
+reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle
+reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles
+reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles
+
+reg WriteOp; // Write Operation Latch (When asserted,
write operation is in progress)
+reg [6:0] BitCounter; // Bit Counter
+
+
+wire [3:0] ByteSelect; // Byte Select defines which byte (preamble,
data, operation, etc.) is loaded and shifted through the shift register.
+wire MdcEn; // MII Management Data Clock Enable signal
is asserted for one Clk period before Mdc rises.
+wire ShiftedBit; // This bit is output of the shift register
and is connected to the Mdo signal
+
+
+wire LatchByte1_d2;
+wire LatchByte0_d2;
+reg LatchByte1_d;
+reg LatchByte0_d;
+reg [1:0] LatchByte; // Latch Byte selects which part of Read
Status Data is updated from the shift register
+
+reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read
data
+
+wire Mdo; // MII Management Data Output
+wire MdoEn; // MII Management Data Output Enable
+wire Mdi;
+
+assign Mdi=Mdio;
+assign Mdio=MdoEn?Mdo:1'bz;
+
+
+
+// Generation of the EndBusy signal. It is used for ending the MII Management
operation.
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ EndBusy_d <= 1'b0;
+ EndBusy <= 1'b0;
+ end
+ else
+ begin
+ EndBusy_d <= ~InProgress_q2 & InProgress_q3;
+ EndBusy <= EndBusy_d;
+ end
+end
+
+
+// Update MII RX_DATA register
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ UpdateMIIRX_DATAReg <= 0;
+ else
+ if(EndBusy & ~WCtrlDataStart_q)
+ UpdateMIIRX_DATAReg <= 1;
+ else
+ UpdateMIIRX_DATAReg <= 0;
+end
+
+
+
+// Generation of the delayed signals used for positive edge triggering.
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ WCtrlData_q1 <= 1'b0;
+ WCtrlData_q2 <= 1'b0;
+ WCtrlData_q3 <= 1'b0;
+
+ RStat_q1 <= 1'b0;
+ RStat_q2 <= 1'b0;
+ RStat_q3 <= 1'b0;
+
+ ScanStat_q1 <= 1'b0;
+ ScanStat_q2 <= 1'b0;
+ SyncStatMdcEn <= 1'b0;
+ end
+ else
+ begin
+ WCtrlData_q1 <= WCtrlData;
+ WCtrlData_q2 <= WCtrlData_q1;
+ WCtrlData_q3 <= WCtrlData_q2;
+
+ RStat_q1 <= RStat;
+ RStat_q2 <= RStat_q1;
+ RStat_q3 <= RStat_q2;
+
+ ScanStat_q1 <= ScanStat;
+ ScanStat_q2 <= ScanStat_q1;
+ if(MdcEn)
+ SyncStatMdcEn <= ScanStat_q2;
+ end
+end
+
+
+// Generation of the Start Commands (Write Control Data or Read Status)
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ WCtrlDataStart <= 1'b0;
+ WCtrlDataStart_q <= 1'b0;
+ RStatStart <= 1'b0;
+ end
+ else
+ begin
+ if(EndBusy)
+ begin
+ WCtrlDataStart <= 1'b0;
+ RStatStart <= 1'b0;
+ end
+ else
+ begin
+ if(WCtrlData_q2 & ~WCtrlData_q3)
+ WCtrlDataStart <= 1'b1;
+ if(RStat_q2 & ~RStat_q3)
+ RStatStart <= 1'b1;
+ WCtrlDataStart_q <= WCtrlDataStart;
+ end
+ end
+end
+
+
+// Generation of the Nvalid signal (indicates when the status is invalid)
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ Nvalid <= 1'b0;
+ else
+ begin
+ if(~InProgress_q2 & InProgress_q3)
+ begin
+ Nvalid <= 1'b0;
+ end
+ else
+ begin
+ if(ScanStat_q2 & ~SyncStatMdcEn)
+ Nvalid <= 1'b1;
+ end
+ end
+end
+
+// Signals used for the generation of the Operation signals (positive edge)
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ WCtrlDataStart_q1 <= 1'b0;
+ WCtrlDataStart_q2 <= 1'b0;
+
+ RStatStart_q1 <= 1'b0;
+ RStatStart_q2 <= 1'b0;
+
+ InProgress_q1 <= 1'b0;
+ InProgress_q2 <= 1'b0;
+ InProgress_q3 <= 1'b0;
+
+ LatchByte0_d <= 1'b0;
+ LatchByte1_d <= 1'b0;
+
+ LatchByte <= 2'b00;
+ end
+ else
+ begin
+ if(MdcEn)
+ begin
+ WCtrlDataStart_q1 <= WCtrlDataStart;
+ WCtrlDataStart_q2 <= WCtrlDataStart_q1;
+
+ RStatStart_q1 <= RStatStart;
+ RStatStart_q2 <= RStatStart_q1;
+
+ LatchByte[0] <= LatchByte0_d;
+ LatchByte[1] <= LatchByte1_d;
+
+ LatchByte0_d <= LatchByte0_d2;
+ LatchByte1_d <= LatchByte1_d2;
+
+ InProgress_q1 <= InProgress;
+ InProgress_q2 <= InProgress_q1;
+ InProgress_q3 <= InProgress_q2;
+ end
+ end
+end
+
+
+// Generation of the Operation signals
+assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
+assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;
+assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 &
~InProgress_q2;
+assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp;
+
+// Busy
+reg Busy;
+always @ (posedge Clk or posedge Reset)
+ if (Reset)
+ Busy <=0;
+ else if(WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn
| EndBusy | InProgress | InProgress_q3 | Nvalid)
+ Busy <=1;
+ else
+ Busy <=0;
+
+//assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart |
SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
+
+
+// Generation of the InProgress signal (indicates when an operation is in
progress)
+// Generation of the WriteOp signal (indicates when a write is in progress)
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ InProgress <= 1'b0;
+ WriteOp <= 1'b0;
+ end
+ else
+ begin
+ if(MdcEn)
+ begin
+ if(StartOp)
+ begin
+ if(~InProgress)
+ WriteOp <= WriteDataOp;
+ InProgress <= 1'b1;
+ end
+ else
+ begin
+ if(EndOp)
+ begin
+ InProgress <= 1'b0;
+ WriteOp <= 1'b0;
+ end
+ end
+ end
+ end
+end
+
+
+
+// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ BitCounter[6:0] <= 7'h0;
+ else
+ begin
+ if(MdcEn)
+ begin
+ if(InProgress)
+ begin
+ if(NoPre & ( BitCounter == 7'h0 ))
+ BitCounter[6:0] <= 7'h21;
+ else
+ BitCounter[6:0] <= BitCounter[6:0] + 1'b1;
+ end
+ else
+ BitCounter[6:0] <= 7'h0;
+ end
+ end
+end
+
+
+// Operation ends when the Bit Counter reaches 63
+assign EndOp = BitCounter==63;
+
+assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre
& (BitCounter == 7'h20)));
+assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
+assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
+assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
+
+
+// Latch Byte selects which part of Read Status Data is updated from the shift
register
+assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
+assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
+
+wire MdcEn_n;
+
+// Connecting the Clock Generator Module
+eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]),
.MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
+ );
+
+// Connecting the Shift Register Module
+eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi),
.Fiad(Fiad), .Rgad(Rgad),
+ .CtrlData(CtrlData), .WriteOp(WriteOp),
.ByteSelect(ByteSelect), .LatchByte(LatchByte),
+ .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
+ );
+
+// Connecting the Output Control Module
+eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n),
.InProgress(InProgress),
+ .ShiftedBit(ShiftedBit), .BitCounter(BitCounter),
.WriteOp(WriteOp), .NoPre(NoPre),
+ .Mdo(Mdo), .MdoEn(MdoEn)
+ );
+
+endmodule
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_outputcontrol.v
(from rev 10762,
gnuradio/trunk/usrp2/fpga/simple_gemac/miim/eth_outputcontrol.v)
===================================================================
---
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_outputcontrol.v
(rev 0)
+++
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_outputcontrol.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,158 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_outputcontrol.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/projects/ethmac/ ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (address@hidden) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: eth_outputcontrol.v,v $
+// Revision 1.2 2005/12/13 12:54:49 maverickist
+// first simulation passed
+//
+// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
+// no message
+//
+// Revision 1.2 2005/04/27 15:58:46 Administrator
+// no message
+//
+// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
+// no message
+//
+// Revision 1.4 2002/07/09 20:11:59 mohor
+// Comment removed.
+//
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram
(For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the
end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3 2001/06/01 22:28:56 mohor
+// This files (MIIM) are fully working. They were thoroughly tested. The
testbench is not updated.
+//
+//
+
+module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter,
WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
+
+input Clk; // Host Clock
+input Reset; // General Reset
+input WriteOp; // Write Operation Latch (When asserted,
write operation is in progress)
+input NoPre; // No Preamble (no 32-bit preamble)
+input InProgress; // Operation in progress
+input ShiftedBit; // This bit is output of the shift register
and is connected to the Mdo signal
+input [6:0] BitCounter; // Bit Counter
+input MdcEn_n; // MII Management Data Clock Enable signal
is asserted for one Clk period before Mdc falls.
+
+output Mdo; // MII Management Data Output
+output MdoEn; // MII Management Data Output Enable
+
+wire SerialEn;
+
+reg MdoEn_2d;
+reg MdoEn_d;
+reg MdoEn;
+
+reg Mdo_2d;
+reg Mdo_d;
+reg Mdo; // MII Management Data Output
+
+
+
+// Generation of the Serial Enable signal (enables the serialization of the
data)
+assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter ==
0 ) & NoPre ) )
+ | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) |
( ( BitCounter == 0 ) & NoPre ));
+
+
+// Generation of the MdoEn signal
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ MdoEn_2d <= 1'b0;
+ MdoEn_d <= 1'b0;
+ MdoEn <= 1'b0;
+ end
+ else
+ begin
+ if(MdcEn_n)
+ begin
+ MdoEn_2d <= SerialEn | InProgress & BitCounter<32;
+ MdoEn_d <= MdoEn_2d;
+ MdoEn <= MdoEn_d;
+ end
+ end
+end
+
+
+// Generation of the Mdo signal.
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ Mdo_2d <= 1'b0;
+ Mdo_d <= 1'b0;
+ Mdo <= 1'b0;
+ end
+ else
+ begin
+ if(MdcEn_n)
+ begin
+ Mdo_2d <= ~SerialEn & BitCounter<32;
+ Mdo_d <= ShiftedBit | Mdo_2d;
+ Mdo <= Mdo_d;
+ end
+ end
+end
+
+
+
+endmodule
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_shiftreg.v
(from rev 10762, gnuradio/trunk/usrp2/fpga/simple_gemac/miim/eth_shiftreg.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_shiftreg.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/miim/eth_shiftreg.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,159 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_shiftreg.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/projects/ethmac/ ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (address@hidden) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: eth_shiftreg.v,v $
+// Revision 1.2 2005/12/13 12:54:49 maverickist
+// first simulation passed
+//
+// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
+// no message
+//
+// Revision 1.2 2005/04/27 15:58:47 Administrator
+// no message
+//
+// Revision 1.1.1.1 2004/12/15 06:38:54 Administrator
+// no message
+//
+// Revision 1.5 2002/08/14 18:16:59 mohor
+// LinkFail signal was not latching appropriate bit.
+//
+// Revision 1.4 2002/03/02 21:06:01 mohor
+// LinkFail signal was not latching appropriate bit.
+//
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram
(For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the
end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3 2001/06/01 22:28:56 mohor
+// This files (MIIM) are fully working. They were thoroughly tested. The
testbench is not updated.
+//
+//
+
+module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp,
ByteSelect,
+ LatchByte, ShiftedBit, Prsd, LinkFail);
+
+
+input Clk; // Input clock (Host clock)
+input Reset; // Reset signal
+input MdcEn_n; // Enable signal is asserted for one Clk period
before Mdc falls.
+input Mdi; // MII input data
+input [4:0] Fiad; // PHY address
+input [4:0] Rgad; // Register address (within the selected PHY)
+input [15:0]CtrlData; // Control data (data to be written to the PHY)
+input WriteOp; // The current operation is a PHY register write
operation
+input [3:0] ByteSelect; // Byte select
+input [1:0] LatchByte; // Byte select for latching (read operation)
+
+output ShiftedBit; // Bit shifted out of the shift register
+output[15:0]Prsd; // Read Status Data (data read from the PHY)
+output LinkFail; // Link Integrity Signal
+
+reg [7:0] ShiftReg; // Shift register for shifting the data in and
out
+reg [15:0]Prsd;
+reg LinkFail;
+
+
+
+
+// ShiftReg[7:0] :: Shift Register Data
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ ShiftReg[7:0] <= 8'h0;
+ Prsd[15:0] <= 16'h0;
+ LinkFail <= 1'b0;
+ end
+ else
+ begin
+ if(MdcEn_n)
+ begin
+ if(|ByteSelect)
+ begin
+ case (ByteSelect[3:0])
+ 4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp,
Fiad[4:1]};
+ 4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
+ 4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
+ 4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
+ default : ShiftReg[7:0] <= 8'h0;
+ endcase
+ end
+ else
+ begin
+ ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
+ if(LatchByte[0])
+ begin
+ Prsd[7:0] <= {ShiftReg[6:0], Mdi};
+ if(Rgad == 5'h01)
+ LinkFail <= ~ShiftReg[1]; // this is bit [2], because it
is not shifted yet
+ end
+ else
+ begin
+ if(LatchByte[1])
+ Prsd[15:8] <= {ShiftReg[6:0], Mdi};
+ end
+ end
+ end
+ end
+end
+
+
+assign ShiftedBit = ShiftReg[7];
+
+
+endmodule
Copied: gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/rxmac_to_ll8.v
(from rev 10744, gnuradio/trunk/usrp2/fpga/simple_gemac/rxmac_to_ll8.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/rxmac_to_ll8.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/rxmac_to_ll8.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,54 @@
+
+module rxmac_to_ll8
+ (input clk, input reset, input clear,
+ input [7:0] rx_data, input rx_valid, input rx_error, input rx_ack,
+ output [7:0] ll_data, output ll_sof, output ll_eof, output ll_error, output
ll_src_rdy, input ll_dst_rdy );
+
+ reg [2:0] xfer_state;
+
+ assign ll_data = rx_data;
+ assign ll_src_rdy = ((rx_valid & (xfer_state != XFER_OVERRUN2) )
+ | (xfer_state == XFER_ERROR)
+ | (xfer_state == XFER_OVERRUN));
+ assign ll_sof =
((xfer_state==XFER_IDLE)|(xfer_state==XFER_ERROR)|(xfer_state==XFER_OVERRUN));
+ assign ll_eof = (rx_ack | (xfer_state==XFER_ERROR) |
(xfer_state==XFER_OVERRUN));
+ assign ll_error = (xfer_state ==
XFER_ERROR)|(xfer_state==XFER_OVERRUN);
+
+ localparam XFER_IDLE = 0;
+ localparam XFER_ACTIVE = 1;
+ localparam XFER_ERROR = 2;
+ localparam XFER_ERROR2 = 3;
+ localparam XFER_OVERRUN = 4;
+ localparam XFER_OVERRUN2 = 5;
+
+ always @(posedge clk)
+ if(reset | clear)
+ xfer_state <= XFER_IDLE;
+ else
+ case(xfer_state)
+ XFER_IDLE :
+ if(rx_valid)
+ xfer_state <= XFER_ACTIVE;
+ XFER_ACTIVE :
+ if(rx_error)
+ xfer_state <= XFER_ERROR;
+ else if(~rx_valid)
+ xfer_state <= XFER_IDLE;
+ else if(~ll_dst_rdy)
+ xfer_state <= XFER_OVERRUN;
+ XFER_ERROR :
+ if(ll_dst_rdy)
+ xfer_state <= XFER_ERROR2;
+ XFER_ERROR2 :
+ if(~rx_error)
+ xfer_state <= XFER_IDLE;
+ XFER_OVERRUN :
+ if(ll_dst_rdy)
+ xfer_state <= XFER_OVERRUN2;
+ XFER_OVERRUN2 :
+ if(~rx_valid)
+ xfer_state <= XFER_IDLE;
+ endcase // case (xfer_state)
+
+
+endmodule // rxmac_to_ll8
Copied: gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac.v
(from rev 10721, gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,60 @@
+
+module simple_gemac
+ (input clk125, input reset,
+ // GMII
+ output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0]
GMII_TXD,
+ input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
+
+ // Flow Control Interface
+ input pause_req, input [15:0] pause_time, input pause_en,
+
+ // Settings
+ input [47:0] ucast_addr, input [47:0] mcast_addr,
+ input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause,
input pass_all,
+
+ // RX Client Interface
+ output rx_clk, output [7:0] rx_data, output rx_valid, output rx_error,
output rx_ack,
+
+ // TX Client Interface
+ output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output
tx_ack
+ );
+
+ localparam SGE_IFG = 8'd12; // 12 should be the absolute
minimum
+
+ wire rst_rxclk, rst_txclk;
+ reset_sync reset_sync_tx
(.clk(tx_clk),.reset_in(reset),.reset_out(rst_txclk));
+ reset_sync reset_sync_rx
(.clk(rx_clk),.reset_in(reset),.reset_out(rst_rxclk));
+
+ wire [15:0] pause_quanta_rcvd;
+
+ simple_gemac_tx simple_gemac_tx
+ (.clk125(clk125),.reset(rst_txclk),
+ .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
+ .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+ .tx_clk(tx_clk), .tx_data(tx_data), .tx_valid(tx_valid),
.tx_error(tx_error), .tx_ack(tx_ack),
+ .ifg(SGE_IFG), .mac_addr(ucast_addr),
+ .pause_req(pause_req), .pause_time(pause_time), // We request flow
control
+ .pause_apply(pause_apply), .paused(paused) // We respect flow control
+ );
+
+ simple_gemac_rx simple_gemac_rx
+ (.reset(rst_rxclk),
+ .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
+ .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+ .rx_clk(rx_clk), .rx_data(rx_data), .rx_valid(rx_valid),
.rx_error(rx_error), .rx_ack(rx_ack),
+ .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
+ .pass_ucast(pass_ucast), .pass_mcast(pass_mcast),
.pass_bcast(pass_bcast),
+ .pass_pause(pass_pause), .pass_all(pass_all),
+ .pause_quanta_rcvd(pause_quanta_rcvd), .pause_rcvd(pause_rcvd)
+ );
+
+ flow_ctrl_tx flow_ctrl_tx
+ (.rst(rst_txclk), .tx_clk(tx_clk),
+ .tx_pause_en(pause_en),
+ .pause_quanta(pause_quanta_rcvd), // 16 bit value
+ .pause_quanta_val(pause_rcvd),
+ .pause_apply(pause_apply),
+ .paused(paused)
+ );
+
+endmodule // simple_gemac
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_rx.v (from
rev 10721, gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_rx.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_rx.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_rx.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,174 @@
+
+
+module simple_gemac_rx
+ (input clk125, input reset,
+ input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
+ output rx_clk, output [7:0] rx_data, output reg rx_valid, output rx_error,
output reg rx_ack,
+ input [47:0] ucast_addr, input [47:0] mcast_addr,
+ input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause,
input pass_all,
+ output reg [15:0] pause_quanta_rcvd, output pause_rcvd );
+
+ reg [7:0] rxd_d1;
+ reg rx_dv_d1, rx_er_d1;
+ assign rx_clk = GMII_RX_CLK;
+
+ always @(posedge rx_clk)
+ begin
+ rx_dv_d1 <= GMII_RX_DV;
+ rx_er_d1 <= GMII_RX_ER;
+ rxd_d1 <= GMII_RXD;
+ end
+
+ wire [7:0] rxd_del;
+ wire rx_dv_del, rx_er_del;
+ reg go_filt;
+
+ localparam DELAY = 6;
+ delay_line #(.WIDTH(10)) rx_delay
+ (.clk(rx_clk), .delay(DELAY),
.din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_dl,rxd_del}));
+
+ always @(posedge rx_clk)
+ if(reset)
+ rx_ack <= 0;
+ else
+ rx_ack <= (rx_state == RX_GOODFRAME);
+
+ wire is_ucast, is_bcast, is_mcast, is_pause;
+ wire keep_packet = (pass_ucast & is_ucast) | (pass_mcast & is_mcast) |
+ (pass_bcast & is_bcast) | (pass_pause & is_pause) | pass_all;
+
+ reg [7:0] rx_state;
+ assign rx_data = rxd_del;
+ assign rx_error = (rx_state == RX_ERROR);
+
+ always @(posedge rx_clk)
+ if(reset)
+ rx_valid <= 0;
+ else if(keep_packet)
+ rx_valid <= 1;
+ else if((rx_state == RX_IDLE)|(rx_state == RX_ERROR))
+ rx_valid <= 0;
+
+ address_filter af_ucast (.clk(rx_clk), .reset(reset), .go(go_filt),
.data(rxd_d1),
+ .address(ucast_addr), .match(is_ucast), .done());
+ address_filter af_mcast (.clk(rx_clk), .reset(reset), .go(go_filt),
.data(rxd_d1),
+ .address(mcast_addr), .match(is_mcast), .done());
+ address_filter af_bcast (.clk(rx_clk), .reset(reset), .go(go_filt),
.data(rxd_d1),
+ .address(48'hFFFF_FFFF_FFFF), .match(is_bcast),
.done());
+ address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt),
.data(rxd_d1),
+ .address(48'h0180_c200_0001), .match(is_pause),
.done());
+
+ localparam RX_IDLE = 0;
+ localparam RX_PREAMBLE = 1;
+ localparam RX_FRAME = 2;
+ localparam RX_GOODFRAME = 3;
+ localparam RX_DO_PAUSE = 4;
+ localparam RX_ERROR = 5;
+ localparam RX_DROP = 6;
+
+ localparam RX_PAUSE = 16;
+ localparam RX_PAUSE_CHK88 = RX_PAUSE + 5;
+ localparam RX_PAUSE_CHK08 = RX_PAUSE_CHK88 + 1;
+ localparam RX_PAUSE_CHK00 = RX_PAUSE_CHK08 + 1;
+ localparam RX_PAUSE_CHK01 = RX_PAUSE_CHK00 + 1;
+ localparam RX_PAUSE_STORE_MSB = RX_PAUSE_CHK01 + 1;
+ localparam RX_PAUSE_STORE_LSB = RX_PAUSE_STORE_MSB + 1;
+ localparam RX_PAUSE_WAIT_CRC = RX_PAUSE_STORE_LSB + 1;
+
+
+ always @(posedge rx_clk)
+ go_filt <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5);
+
+ reg [15:0] pkt_len_ctr;
+ always @(posedge rx_clk)
+ if(reset |(rx_state == RX_IDLE))
+ pkt_len_ctr <= 0;
+ else
+ pkt_len_ctr <= pkt_len_ctr + 1;
+
+ localparam MIN_PAUSE_LEN = 71; // 6
+ wire pkt_long_enough = (pkt_len_ctr >= MIN_PAUSE_LEN);
+ always @(posedge rx_clk)
+ if(reset)
+ rx_state <= RX_IDLE;
+ else
+ if(rx_er_d1) // | (~pkt_long_enough & ~rx_dv_d1) & (rx_state !=
RX_IDLE))
+ rx_state <= RX_ERROR;
+ else
+ case(rx_state)
+ RX_IDLE :
+ if(rx_dv_d1)
+ if(rxd_d1 == 8'h55)
+ rx_state <= RX_PREAMBLE;
+ else
+ rx_state <= RX_ERROR;
+ RX_PREAMBLE :
+ if(~rx_dv_d1)
+ rx_state <= RX_ERROR;
+ else if(rxd_d1 == 8'hD5)
+ rx_state <= RX_FRAME;
+ else if(rxd_d1 != 8'h55)
+ rx_state <= RX_ERROR;
+ RX_FRAME :
+ if(is_pause)
+ rx_state <= RX_PAUSE;
+ else if(~rx_dv_d1)
+ if(match_crc)
+ rx_state <= RX_GOODFRAME;
+ else
+ rx_state <= RX_ERROR;
+ RX_PAUSE_CHK88 :
+ if(rxd_d1 != 8'h88)
+ rx_state <= RX_DROP;
+ else
+ rx_state <= RX_PAUSE_CHK08;
+ RX_PAUSE_CHK08 :
+ if(rxd_d1 != 8'h08)
+ rx_state <= RX_DROP;
+ else
+ rx_state <= RX_PAUSE_CHK00;
+ RX_PAUSE_CHK00 :
+ if(rxd_d1 != 8'h00)
+ rx_state <= RX_DROP;
+ else
+ rx_state <= RX_PAUSE_CHK01;
+ RX_PAUSE_CHK01 :
+ if(rxd_d1 != 8'h01)
+ rx_state <= RX_DROP;
+ else
+ rx_state <= RX_PAUSE_STORE_MSB;
+ RX_PAUSE_WAIT_CRC :
+ if(pkt_long_enough)
+ if(match_crc)
+ rx_state <= RX_DO_PAUSE;
+ else
+ rx_state <= RX_DROP;
+ RX_DO_PAUSE :
+ rx_state <= RX_IDLE;
+ RX_GOODFRAME :
+ rx_state <= RX_IDLE;
+ RX_DROP, RX_ERROR :
+ if(~rx_dv_d1)
+ rx_state <= RX_IDLE;
+ default
+ rx_state <= rx_state + 1;
+ endcase // case (rx_state)
+
+ assign pause_rcvd = (rx_state == RX_DO_PAUSE);
+ wire match_crc;
+ wire clear_crc = rx_state == RX_IDLE;
+ wire calc_crc = (rx_state == RX_FRAME) | rx_state[7:4]==4'h1;
+ crc crc_check(.clk(rx_clk),.reset(reset),.clear(clear_crc),
+ .data(rxd_d1),.calc(calc_crc),.crc_out(),.match(match_crc));
+
+ always @(posedge rx_clk)
+ if(reset)
+ pause_quanta_rcvd <= 0;
+ else if(rx_state == RX_PAUSE_STORE_MSB)
+ pause_quanta_rcvd[15:8] <= rxd_d1;
+ else if(rx_state == RX_PAUSE_STORE_LSB)
+ pause_quanta_rcvd[7:0] <= rxd_d1;
+
+ assign rx_clk = GMII_RX_CLK;
+
+endmodule // simple_gemac_rx
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_tb.v (from
rev 10721, gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_tb.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_tb.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_tb.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,200 @@
+
+
+module simple_gemac_tb;
+`include "eth_tasks.v"
+
+ reg clk = 0;
+ reg reset = 1;
+
+ initial #1000 reset = 0;
+ always #50 clk = ~clk;
+
+ wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
+ wire [7:0] GMII_RXD, GMII_TXD;
+
+ wire rx_valid, rx_error, rx_ack;
+ wire tx_ack, tx_valid, tx_error;
+
+ wire [7:0] rx_data, tx_data;
+
+ reg [15:0] pause_time;
+ reg pause_req = 0;
+
+ wire GMII_RX_CLK = GMII_GTX_CLK;
+
+ reg [7:0] FORCE_DAT_ERR = 0;
+ reg FORCE_ERR = 0;
+
+ // Loopback
+ assign GMII_RX_DV = GMII_TX_EN;
+ assign GMII_RX_ER = GMII_TX_ER | FORCE_ERR;
+ assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR;
+
+ wire [47:0] ucast_addr = 48'hF1F2_F3F4_F5F6;
+ wire [47:0] mcast_addr = 0;
+ wire pass_ucast =1, pass_mcast=0, pass_bcast=1, pass_pause=0,
pass_all=0;
+
+ simple_gemac simple_gemac
+ (.clk125(clk), .reset(reset),
+ .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
+ .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+ .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
+ .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+ .pause_req(pause_req), .pause_time(pause_time), .pause_en(1),
+ .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
+ .pass_ucast(pass_ucast), .pass_mcast(pass_mcast),
.pass_bcast(pass_bcast),
+ .pass_pause(pass_pause), .pass_all(pass_all),
+ .rx_clk(rx_clk), .rx_data(rx_data),
+ .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+ .tx_clk(tx_clk), .tx_data(tx_data),
+ .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)
+ );
+
+ wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+ wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2;
+ reg rx_ll_dst_rdy2 = 1;
+ wire [7:0] rx_ll_data, rx_ll_data2;
+ wire rx_ll_error, rx_ll_error2;
+
+ rxmac_to_ll8 rx_adapt
+ (.clk(clk), .reset(reset), .clear(0),
+ .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error),
.rx_ack(rx_ack),
+ .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof),
.ll_error(rx_ll_error),
+ .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
+
+ ll8_shortfifo rx_sfifo
+ (.clk(clk), .reset(reset), .clear(0),
+ .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
+ .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy),
.dst_rdy_o(rx_ll_dst_rdy),
+ .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
+ .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2),
.dst_rdy_i(rx_ll_dst_rdy2));
+
+ wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
+ reg tx_ll_sof2=0, tx_ll_eof2=0;
+ reg tx_ll_src_rdy2 = 0;
+ wire tx_ll_dst_rdy2;
+ wire [7:0] tx_ll_data;
+ reg [7:0] tx_ll_data2 = 0;
+ wire tx_ll_error;
+ wire tx_ll_error2 = 0;
+
+ ll8_shortfifo tx_sfifo
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
+ .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2),
.dst_rdy_o(tx_ll_dst_rdy2),
+ .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
+ .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy),
.dst_rdy_i(tx_ll_dst_rdy));
+
+ ll8_to_txmac ll8_to_txmac
+ (.clk(clk), .reset(reset), .clear(clear),
+ .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
+ .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
+ .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error),
.tx_ack(tx_ack));
+
+ initial $dumpfile("simple_gemac_tb.vcd");
+ initial $dumpvars(0,simple_gemac_tb);
+
+ integer i;
+ reg [7:0] pkt_rom[0:65535];
+ reg [1023:0] ROMFile;
+
+ initial
+ for (i=0;i<65536;i=i+1)
+ pkt_rom[i] <= 8'h0;
+
+ initial
+ begin
+ @(negedge reset);
+ repeat (10)
+ @(posedge clk);
+ SendFlowCtrl(16'h0007); // Send flow control
+ @(posedge clk);
+ #30000;
+ @(posedge clk);
+ SendFlowCtrl(16'h0009); // Increas flow control before it expires
+ #10000;
+ @(posedge clk);
+ SendFlowCtrl(16'h0000); // Cancel flow control before it expires
+ @(posedge clk);
+
+ SendPacket_to_ll8(8'hAA,10); // This packet gets dropped by the
filters
+ repeat (10)
+ @(posedge clk);
+
+ SendPacketFromFile_ll8(60,0,0); // The rest are valid packets
+ repeat (10)
+ @(posedge clk);
+
+ SendPacketFromFile_ll8(61,0,0);
+ repeat (10)
+ @(posedge clk);
+ SendPacketFromFile_ll8(62,0,0);
+ repeat (10)
+ @(posedge clk);
+ SendPacketFromFile_ll8(63,0,0);
+ repeat (1)
+ @(posedge clk);
+ SendPacketFromFile_ll8(64,0,0);
+ repeat (10)
+ @(posedge clk);
+ SendPacketFromFile_ll8(59,0,0);
+ repeat (1)
+ @(posedge clk);
+ SendPacketFromFile_ll8(58,0,0);
+ repeat (1)
+ @(posedge clk);
+ SendPacketFromFile_ll8(100,0,0);
+ repeat (1)
+ @(posedge clk);
+ SendPacketFromFile_ll8(200,150,30); // waiting 14 empties the fifo, 15
underruns
+ repeat (1)
+ @(posedge clk);
+ SendPacketFromFile_ll8(100,0,30);
+ #10000 $finish;
+ end
+
+ // Force a CRC error
+ initial
+ begin
+ #90000;
+ @(posedge clk);
+ FORCE_DAT_ERR <= 8'h10;
+ @(posedge clk);
+ FORCE_DAT_ERR <= 8'h00;
+ end
+
+ // Force an RX_ER error (i.e. link loss)
+ initial
+ begin
+ #116000;
+ @(posedge clk);
+ FORCE_ERR <= 1;
+ @(posedge clk);
+ FORCE_ERR <= 0;
+ end
+
+ // Cause receive fifo to fill, causing an RX overrun
+ initial
+ begin
+ #126000;
+ @(posedge clk);
+ rx_ll_dst_rdy2 <= 0;
+ repeat (30) // Repeat of 14 fills the shortfifo, but works.
15 overflows
+ @(posedge clk);
+ rx_ll_dst_rdy2 <= 1;
+ end
+
+ // Tests: Send and recv flow control, send and receive good packets, RX CRC
err, RX_ER, RX overrun, TX underrun
+ // Still need to test: CRC errors on Pause Frames
+
+ always @(posedge clk)
+ if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
+ begin
+ if(rx_ll_sof2 & ~rx_ll_eof2)
+ $display("RX-PKT-START %d",$time);
+ $display("RX-PKT SOF %d EOF %d ERR%d DAT
%x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
+ if(rx_ll_eof2 & ~rx_ll_sof2)
+ $display("RX-PKT-END %d",$time);
+ end
+
+endmodule // simple_gemac_tb
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_tx.v (from
rev 10721, gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_tx.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_tx.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_tx.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,254 @@
+
+module simple_gemac_tx
+ (input clk125, input reset,
+ output GMII_GTX_CLK, output reg GMII_TX_EN, output reg GMII_TX_ER, output
reg [7:0] GMII_TXD,
+ output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output
tx_ack,
+ input [7:0] ifg, input [47:0] mac_addr,
+ input pause_req, input [15:0] pause_time,
+ input pause_apply, output reg paused
+ );
+
+ reg tx_en_pre, tx_er_pre;
+ reg [7:0] txd_pre;
+
+ assign GMII_GTX_CLK = clk125;
+ assign tx_clk = clk125;
+
+ reg [7:0] tx_state;
+ reg [7:0] ifg_ctr;
+ reg [15:0] frame_len_ctr;
+ reg [7:0] pause_ctr, pause_dat;
+
+ wire in_ifg = (ifg_ctr != 0);
+
+ wire [31:0] crc_out;
+
+ localparam MIN_FRAME_LEN = 64 + 8 - 4; // Min frame length includes
preamble but not CRC
+ localparam MAX_FRAME_LEN = 8192; // How big are the jumbo frames we
want to handle?
+ always @(posedge tx_clk)
+ if(reset |(tx_state == TX_IDLE))
+ frame_len_ctr <= 0;
+ else
+ frame_len_ctr <= frame_len_ctr + 1;
+
+ localparam TX_IDLE = 0;
+ localparam TX_PREAMBLE = 1;
+ localparam TX_SOF_DEL = TX_PREAMBLE + 7;
+ localparam TX_FIRSTBYTE = TX_SOF_DEL + 1;
+ localparam TX_IN_FRAME = TX_FIRSTBYTE + 1;
+ localparam TX_IN_FRAME_2 = TX_IN_FRAME + 1;
+ localparam TX_PAD = TX_IN_FRAME_2 + 1;
+ localparam TX_CRC_0 = 16;
+ localparam TX_CRC_1 = TX_CRC_0 + 1;
+ localparam TX_CRC_2 = TX_CRC_0 + 2;
+ localparam TX_CRC_3 = TX_CRC_0 + 3;
+ localparam TX_ERROR = 32;
+ localparam TX_PAUSE = 55;
+ localparam TX_PAUSE_SOF = TX_PAUSE + 7;
+ localparam TX_PAUSE_FIRST = TX_PAUSE_SOF + 1;
+ localparam TX_PAUSE_END = TX_PAUSE_SOF + 18;
+
+ reg send_pause;
+ reg [15:0] pause_time_held;
+
+ always @(posedge tx_clk)
+ if(reset)
+ send_pause <= 0;
+ else if(pause_req)
+ send_pause <= 1;
+ else if(tx_state == TX_PAUSE)
+ send_pause <= 0;
+
+ always @(posedge tx_clk)
+ if(pause_req)
+ pause_time_held <= pause_time;
+
+ always @(posedge tx_clk)
+ if(reset)
+ tx_state <= TX_IDLE;
+ else
+ case(tx_state)
+ TX_IDLE :
+ if(~in_ifg)
+ if(send_pause)
+ tx_state <= TX_PAUSE;
+ else if(tx_valid & ~pause_apply)
+ tx_state <= TX_PREAMBLE;
+ TX_FIRSTBYTE :
+ if(tx_error)
+ tx_state <= TX_ERROR; // underrun
+ else if(~tx_valid)
+ tx_state <= TX_PAD;
+ else
+ tx_state <= TX_IN_FRAME;
+ TX_IN_FRAME :
+ if(tx_error)
+ tx_state <= TX_ERROR; // underrun
+ else if(~tx_valid)
+ tx_state <= TX_PAD;
+ else if(frame_len_ctr == MIN_FRAME_LEN - 1)
+ tx_state <= TX_IN_FRAME_2;
+ TX_IN_FRAME_2 :
+ if(tx_error)
+ tx_state <= TX_ERROR; // underrun
+ else if(~tx_valid)
+ tx_state <= TX_CRC_0;
+ TX_PAD :
+ if(frame_len_ctr == MIN_FRAME_LEN)
+ tx_state <= TX_CRC_0;
+ TX_CRC_3 :
+ tx_state <= TX_IDLE;
+ TX_ERROR :
+ tx_state <= TX_IDLE;
+ TX_PAUSE_END :
+ tx_state <= TX_PAD;
+ default :
+ tx_state <= tx_state + 1;
+ endcase // case (tx_state)
+
+ always @(posedge tx_clk)
+ if(reset)
+ begin
+ tx_en_pre <= 0;
+ tx_er_pre <= 0;
+ txd_pre <= 0;
+ end
+ else
+ casex(tx_state)
+ TX_IDLE :
+ begin
+ tx_en_pre <= 0;
+ tx_er_pre <= 0;
+ txd_pre <= 0;
+ end
+ TX_PREAMBLE, TX_PAUSE :
+ begin
+ txd_pre <= 8'h55;
+ tx_en_pre <= 1;
+ end
+ TX_SOF_DEL, TX_PAUSE_SOF :
+ txd_pre <= 8'hD5;
+ TX_FIRSTBYTE, TX_IN_FRAME, TX_IN_FRAME_2 :
+ txd_pre <= tx_valid ? tx_data : 0;
+ TX_ERROR :
+ begin
+ tx_er_pre <= 1;
+ txd_pre <= 0;
+ end
+ TX_CRC_3 :
+ tx_en_pre <= 0;
+ TX_PAD :
+ txd_pre <= 0;
+ TX_PAUSE_FIRST, 8'b01xx_xxxx : // In Pause Frame
+ txd_pre <= pause_dat;
+ endcase // case (tx_state)
+
+ localparam SGE_FLOW_CTRL_ADDR = 48'h01_80_C2_00_00_01;
+ always @(posedge tx_clk)
+ case(tx_state)
+ TX_PAUSE_SOF :
+ pause_dat <= SGE_FLOW_CTRL_ADDR[47:40]; // Note everything must be
1 cycle early
+ TX_PAUSE_SOF + 1:
+ pause_dat <= SGE_FLOW_CTRL_ADDR[39:32];
+ TX_PAUSE_SOF + 2:
+ pause_dat <= SGE_FLOW_CTRL_ADDR[31:24];
+ TX_PAUSE_SOF + 3:
+ pause_dat <= SGE_FLOW_CTRL_ADDR[23:16];
+ TX_PAUSE_SOF + 4:
+ pause_dat <= SGE_FLOW_CTRL_ADDR[15:8];
+ TX_PAUSE_SOF + 5:
+ pause_dat <= SGE_FLOW_CTRL_ADDR[7:0];
+ TX_PAUSE_SOF + 6:
+ pause_dat <= mac_addr[47:40];
+ TX_PAUSE_SOF + 7:
+ pause_dat <= mac_addr[39:32];
+ TX_PAUSE_SOF + 8:
+ pause_dat <= mac_addr[31:24];
+ TX_PAUSE_SOF + 9:
+ pause_dat <= mac_addr[23:16];
+ TX_PAUSE_SOF + 10:
+ pause_dat <= mac_addr[15:8];
+ TX_PAUSE_SOF + 11:
+ pause_dat <= mac_addr[7:0];
+ TX_PAUSE_SOF + 12:
+ pause_dat <= 8'h88; // Type = 8808 = MAC ctrl frame
+ TX_PAUSE_SOF + 13:
+ pause_dat <= 8'h08;
+ TX_PAUSE_SOF + 14:
+ pause_dat <= 8'h00; // Opcode = 0001 = PAUSE
+ TX_PAUSE_SOF + 15:
+ pause_dat <= 8'h01;
+ TX_PAUSE_SOF + 16:
+ pause_dat <= pause_time_held[15:8];
+ TX_PAUSE_SOF + 17:
+ pause_dat <= pause_time_held[7:0];
+ endcase // case (tx_state)
+
+ wire start_ifg = (tx_state == TX_CRC_3);
+ always @(posedge tx_clk)
+ if(reset)
+ ifg_ctr <= 100;
+ else if(start_ifg)
+ ifg_ctr <= ifg;
+ else if(ifg_ctr != 0)
+ ifg_ctr <= ifg_ctr - 1;
+
+ wire clear_crc = (tx_state == TX_IDLE);
+
+ wire calc_crc =
+ (tx_state==TX_IN_FRAME) |
+ (tx_state==TX_IN_FRAME_2) |
+ (tx_state==TX_PAD) |
+ (tx_state[6]);
+
+ crc crc(.clk(tx_clk), .reset(reset), .clear(clear_crc),
+ .data(txd_pre), .calc(calc_crc), .crc_out(crc_out));
+
+ assign tx_ack = (tx_state == TX_FIRSTBYTE);
+
+ always @(posedge tx_clk)
+ begin
+ GMII_TX_EN <= tx_en_pre;
+ GMII_TX_ER <= tx_er_pre;
+ case(tx_state)
+ TX_CRC_0 :
+ GMII_TXD <= crc_out[31:24];
+ TX_CRC_1 :
+ GMII_TXD <= crc_out[23:16];
+ TX_CRC_2 :
+ GMII_TXD <= crc_out[15:8];
+ TX_CRC_3 :
+ GMII_TXD <= crc_out[7:0];
+ default :
+ GMII_TXD <= txd_pre;
+ endcase // case (tx_state)
+ end
+
+ // report that we are paused only when we get back to IDLE
+ always @(posedge tx_clk)
+ if(reset)
+ paused <= 0;
+ else if(~pause_apply)
+ paused <= 0;
+ else if(tx_state == TX_IDLE)
+ paused <= 1;
+
+endmodule // simple_gemac_tx
+
+// Testing code
+/*
+ reg [7:0] crc_ctr;
+ reg calc_crc_d1;
+ always @(posedge tx_clk)
+ calc_crc_d1 <= calc_crc;
+
+ always @(posedge tx_clk)
+ if(reset)
+ crc_ctr <= 0;
+ else if(calc_crc)
+ crc_ctr <= crc_ctr+1;
+ else if(calc_crc_d1)
+ $display("CRC COUNT = %d",crc_ctr);
+ else
+ crc_ctr <= 0;
+*/
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_wb.v (from
rev 10762, gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_wb.v)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_wb.v
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_wb.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,134 @@
+
+module wb_reg
+ #(parameter ADDR=0,
+ parameter DEFAULT=0)
+ (input clk, input rst,
+ input [5:0] adr, input wr_acc,
+ input [31:0] dat_i, output reg [31:0] dat_o);
+
+ always @(posedge clk)
+ if(rst)
+ dat_o <= DEFAULT;
+ else if(wr_acc & (adr == ADDR))
+ dat_o <= dat_i;
+
+endmodule // wb_reg
+
+
+
+module simple_gemac_wb
+ (input wb_clk, input wb_rst,
+ input wb_cyc, input wb_stb, input wb_ack, input wb_we,
+ input [7:0] wb_adr, input [31:0] wb_dat_i, output reg [31:0] wb_dat_o,
+
+ inout mdio, output mdc,
+ output [47:0] ucast_addr, output [47:0] mcast_addr,
+ output pass_ucast, output pass_mcast, output pass_bcast,
+ output pass_pause, output pass_all, output pause_en );
+
+ wire wr_acc = wb_cyc & wb_stb & wb_we;
+ wire rd_acc = wb_cyc & wb_stb & ~wb_we;
+
+ wire [5:0] misc_settings;
+ assign {pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_en}
= misc_settings;
+
+ wb_reg #(.ADDR(0),.DEFAULT(6'b111001))
+ wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]),
.dat_i(wb_dat_i), .dat_o(misc_settings) );
+ wb_reg #(.ADDR(1),.DEFAULT(0))
+ wb_reg_ucast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]),
.dat_i(wb_dat_i), .dat_o(ucast_addr[47:32]) );
+ wb_reg #(.ADDR(2),.DEFAULT(0))
+ wb_reg_ucast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]),
.dat_i(wb_dat_i), .dat_o(ucast_addr[31:0]) );
+ wb_reg #(.ADDR(3),.DEFAULT(0))
+ wb_reg_mcast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]),
.dat_i(wb_dat_i), .dat_o(mcast_addr[47:32]) );
+ wb_reg #(.ADDR(4),.DEFAULT(0))
+ wb_reg_mcast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]),
.dat_i(wb_dat_i), .dat_o(mcast_addr[31:0]) );
+
+ //MII to CPU
+ wire [7:0] Divider; // Divider for the host clock
+ wire [15:0] CtrlData; // Control Data (to be written to the PHY
reg.)
+ wire [4:0] Rgad; // Register Address (within the PHY)
+ wire [4:0] Fiad; // PHY Address
+ wire NoPre; // No Preamble (no 32-bit preamble)
+ wire WCtrlData; // Write Control Data operation
+ wire RStat; // Read Status operation
+ wire ScanStat; // Scan Status operation
+ wire Busy; // Busy Signal
+ wire LinkFail; // Link Integrity Signal
+ wire Nvalid; // Invalid Status (qualifier for the valid
scan result)
+ wire [15:0] Prsd; // Read Status Data (data read from the PHY)
+ wire WCtrlDataStart; // This signals resets the WCTRLDATA bit in
the MIIM Command register
+ wire RStatStart; // This signal resets the RSTAT BIT in the
MIIM Command register
+ wire UpdateMIIRX_DATAReg; // Updates MII RX_DATA register with read
data
+
+ // registers for controlling the MII interface
+ reg [2:0] MIICOMMAND;
+ wire [12:0] MIIADDRESS;
+ reg [15:0] MIIRX_DATA;
+ wire [2:0] MIISTATUS;
+
+ wb_reg #(.ADDR(5),.DEFAULT(0))
+ wb_reg_miimoder (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]),
.dat_i(wb_dat_i), .dat_o({NoPre,Divider}) );
+
+ wb_reg #(.ADDR(6),.DEFAULT(0))
+ wb_reg_miiaddr (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]),
.dat_i(wb_dat_i), .dat_o(MIIADDRESS) );
+
+ wb_reg #(.ADDR(7),.DEFAULT(0))
+ wb_reg_miidata (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]),
.dat_i(wb_dat_i), .dat_o(CtrlData) );
+
+ // MIICOMMAND register - needs special treatment because of auto-resetting
bits
+ always @ (posedge wb_clk)
+ if (wb_rst)
+ MIICOMMAND <= 0;
+ else
+ if (wr_acc & (wb_adr == 8'd8))
+ MIICOMMAND <= wb_dat_i;
+ else
+ begin
+ if ( WCtrlDataStart )
+ MIICOMMAND[2] <= 0;
+ if ( RStatStart )
+ MIICOMMAND[1] <= 0;
+ end
+
+ // MIIRX_DATA register
+ always @(posedge wb_clk)
+ if (wb_rst)
+ MIIRX_DATA <= 0;
+ else
+ if (UpdateMIIRX_DATAReg )
+ MIIRX_DATA <= Prsd;
+
+ // MIICOMMAND
+ assign WCtrlData = MIICOMMAND[2];
+ assign RStat = MIICOMMAND[1];
+ assign ScanStat = MIICOMMAND[0];
+ // MIIADDRESS
+ assign Rgad = MIIADDRESS[12:8];
+ assign Fiad = MIIADDRESS[4:0];
+ // MIISTATUS
+ assign MIISTATUS[2:0] = { Nvalid, Busy, LinkFail };
+
+ eth_miim eth_miim
+ (.Clk(wb_clk), .Reset(wb_rst),
+ .Divider(Divider), .NoPre(NoPre), .CtrlData(CtrlData), .Rgad(Rgad),
.Fiad(Fiad),
+ .WCtrlData(WCtrlData), .RStat(RStat), .ScanStat(ScanStat), .Mdio(mdio),
.Mdc(mdc),
+ .Busy(Busy), .Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(Nvalid),
+ .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart),
+ .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) );
+
+ always @(posedge wb_clk)
+ case(wb_adr)
+ 0 : wb_dat_o <= misc_settings;
+ 1 : wb_dat_o <= ucast_addr[47:32];
+ 2 : wb_dat_o <= ucast_addr[31:0];
+ 3 : wb_dat_o <= mcast_addr[47:32];
+ 4 : wb_dat_o <= mcast_addr[31:0];
+ 5 : wb_dat_o <= {NoPre,Divider};
+ 6 : wb_dat_o <= MIIADDRESS;
+ 7 : wb_dat_o <= CtrlData;
+ 8 : wb_dat_o <= MIICOMMAND;
+ 9 : wb_dat_o <= MIISTATUS;
+ 10: wb_dat_o <= MIIRX_DATA;
+ endcase // case (wb_adr)
+
+endmodule // simple_gemac_wb
Copied:
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
(from rev 10762, gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v)
===================================================================
---
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
(rev 0)
+++
gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,74 @@
+
+module simple_gemac_wrapper
+ (input clk125, input reset,
+ // GMII
+ output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0]
GMII_TXD,
+ input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
+
+ // Flow Control Interface
+ input pause_req, input [15:0] pause_time,
+
+ // RX Client Interface
+ output rx_clk, output [7:0] rx_ll_data, output rx_ll_sof, output rx_ll_eof,
+ output rx_ll_error, output rx_ll_src_rdy, input rx_ll_dst_rdy,
+
+ // TX Client Interface
+ output tx_clk, input [7:0] tx_ll_data, input tx_ll_sof, input tx_ll_eof,
+ input tx_ll_src_rdy, output tx_ll_dst_rdy,
+
+ // Wishbone Interface
+ input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack,
input wb_we,
+ input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o,
+
+ // MIIM
+ inout mdio, output mdc );
+
+ wire [7:0] rx_data, tx_data;
+ wire tx_clk, tx_valid, tx_error, tx_ack;
+ wire rx_clk, rx_valid, rx_error, rx_ack;
+
+ wire [47:0] ucast_addr, mcast_addr;
+ wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_en;
+
+ wire rst_rxclk, rst_txclk;
+ reset_sync reset_sync_tx
(.clk(tx_clk),.reset_in(reset),.reset_out(rst_txclk));
+ reset_sync reset_sync_rx
(.clk(rx_clk),.reset_in(reset),.reset_out(rst_rxclk));
+
+ simple_gemac simple_gemac
+ (.clk125(clk125), .reset(reset),
+ .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
+ .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+ .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
+ .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+ .pause_req(pause_req), .pause_time(pause_time), .pause_en(1),
+ .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
+ .pass_ucast(pass_ucast), .pass_mcast(pass_mcast),
.pass_bcast(pass_bcast),
+ .pass_pause(pass_pause), .pass_all(pass_all),
+ .rx_clk(rx_clk), .rx_data(rx_data),
+ .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+ .tx_clk(tx_clk), .tx_data(tx_data),
+ .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)
+ );
+
+ simple_gemac_wb simple_gemac_wb
+ (.wb_clk(wb_clk), .wb_rst(wb_rst),
+ .wb_cyc(wb_cyc), .wb_stb(wb_stb), .wb_ack(wb_ack), .wb_we(wb_we),
+ .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+ .mdio(mdio), .mdc(mdc),
+ .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
+ .pass_ucast(pass_ucast), .pass_mcast(pass_mcast),
.pass_bcast(pass_bcast),
+ .pass_pause(pass_pause), .pass_all(pass_all), .pause_en(pause_en) );
+
+ rxmac_to_ll8 rx_adapt
+ (.clk(rx_clk), .reset(rx_reset), .clear(0),
+ .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error),
.rx_ack(rx_ack),
+ .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof),
.ll_error(rx_ll_error),
+ .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
+
+ ll8_to_txmac ll8_to_txmac
+ (.clk(tx_clk), .reset(tx_reset), .clear(0),
+ .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
+ .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
+ .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error),
.tx_ack(tx_ack));
+
+endmodule // simple_gemac_wrapper
Copied: gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/test_packet.mem
(from rev 10721, gnuradio/trunk/usrp2/fpga/simple_gemac/test_packet.mem)
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/test_packet.mem
(rev 0)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/simple_gemac/test_packet.mem
2009-04-14 19:41:41 UTC (rev 10830)
@@ -0,0 +1,66 @@
+ff
+ff
+ff
+ff
+ff
+ff
+08
+00
+07
+5c
+2e
+e4
+08
+06
+00
+01
+08
+04
+06
+02
+00
+01
+08
+00
+07
+5c
+2e
+e4
+03
+64
+00
+00
+00
+00
+00
+00
+02
+64
+00
+3a
+f3
+5c
+4f
+12
+01
+10
+00
+01
+00
+00
+00
+00
+00
+00
+20
+41
+42
+41
+08
+00
+AA
+BB
+CC
+DD
+EE
+FF
Modified: gnuradio/branches/releases/3.2/usrp2/fpga/top/u2_core/u2_core.v
===================================================================
--- gnuradio/branches/releases/3.2/usrp2/fpga/top/u2_core/u2_core.v
2009-04-14 19:31:57 UTC (rev 10829)
+++ gnuradio/branches/releases/3.2/usrp2/fpga/top/u2_core/u2_core.v
2009-04-14 19:41:41 UTC (rev 10830)
@@ -695,14 +695,14 @@
{dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
always @(posedge dsp_clk)
- eth_mac_debug <= { { GMII_TX_EN, GMII_RX_DV, debug_txc[13:0]},
+ eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]},
{eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
assign debug_clk[0] = 0;
assign debug_clk[1] = dsp_clk;
- assign debug = 0;
- assign debug_gpio_0 = 0;
+ assign debug = host_to_dsp_fifo; // debug_mux ? host_to_dsp_fifo :
dsp_to_host_fifo;
+ assign debug_gpio_0 = eth_mac_debug;
assign debug_gpio_1 = 0;
endmodule // u2_core
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- [Commit-gnuradio] r10830 - in gnuradio/branches/releases/3.2: . gnuradio-core/src/python/gnuradio/gr gr-wxgui/src/python/plotter grc/data/platforms/python/blocks usrp2/firmware/lib usrp2/fpga usrp2/fpga/control_lib usrp2/fpga/control_lib/newfifo usrp2/fpga/eth usrp2/fpga/eth/rtl/verilog usrp2/fpga/simple_gemac usrp2/fpga/simple_gemac/miim usrp2/fpga/top/u2_core,
jcorgan <=