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[Commit-gnuradio] r10783 - in gnuradio/branches/developers/matt/new_eth/
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From: |
matt |
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Subject: |
[Commit-gnuradio] r10783 - in gnuradio/branches/developers/matt/new_eth/usrp2/fpga: control_lib control_lib/newfifo models sdr_lib serdes simple_gemac testbench top/u2_core top/u2_rev3 |
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Date: |
Mon, 6 Apr 2009 15:48:18 -0600 (MDT) |
Author: matt
Date: 2009-04-06 15:48:18 -0600 (Mon, 06 Apr 2009)
New Revision: 10783
Added:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/cascadefifo_2clock.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/ll8_shortfifo.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/newfifo_2clock.v
Removed:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/buffer_int.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/buffer_pool.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/fifo_2clock.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/fifo_2clock_casc.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/ll8_shortfifo.v
Modified:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/fifo36_to_ll8.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/models/adc_model.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/sdr_lib/rx_control.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/sdr_lib/tx_control.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/serdes/serdes.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/serdes/serdes_rx.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/serdes/serdes_tx.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/delay_line.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/rxmac_to_ll8.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/simple_gemac_rx.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/simple_gemac_tx.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/testbench/cmdfile
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/top/u2_core/u2_core.v
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/top/u2_rev3/Makefile
Log:
new ethernet mac, ready for testing
Added:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/cascadefifo_2clock.v
===================================================================
---
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/cascadefifo_2clock.v
(rev 0)
+++
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/cascadefifo_2clock.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -0,0 +1,27 @@
+
+module cascadefifo_2clock
+ #(parameter DWIDTH=32, AWIDTH=9)
+ (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o,
output [AWIDTH-1:0] level_wclk,
+ input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input
dst_rdy_i, output [AWIDTH-1:0] level_rclk,
+ input arst);
+
+ wire [DWIDTH-1:0] data_int1, data_int2;
+ wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
+
+ fifo_short #(.WIDTH(DWIDTH)) shortfifo
+ (.clk(wclk), .reset(arst), .clear(0),
+ .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+ .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1)
);
+
+ newfifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
+ (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1),
.dst_rdy_o(dst_rdy_int1), .level_wclk(level_wclk),
+ .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2),
.dst_rdy_i(dst_rdy_int2), .level_rclk(level_rclk),
+ .arst(arst) );
+
+ fifo_short #(.WIDTH(DWIDTH)) shortfifo2
+ (.clk(rclk), .reset(arst), .clear(0),
+ .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
+ .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i) );
+
+endmodule // fifo_2clock_casc
+
Modified:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/fifo36_to_ll8.v
===================================================================
---
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/fifo36_to_ll8.v
2009-04-06 20:38:57 UTC (rev 10782)
+++
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/fifo36_to_ll8.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -1,6 +1,6 @@
module fifo36_to_ll8
- (input clk, reset,
+ (input clk, input reset, input clear,
input [35:0] f36_data,
input f36_src_rdy_i,
output f36_dst_rdy_o,
Copied:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/ll8_shortfifo.v
(from rev 10782,
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/ll8_shortfifo.v)
===================================================================
---
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/ll8_shortfifo.v
(rev 0)
+++
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/ll8_shortfifo.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -0,0 +1,13 @@
+
+
+module ll8_shortfifo
+ (input clk, input reset, input clear,
+ input [7:0] datain, input sof_i, input eof_i, input error_i, input
src_rdy_i, output dst_rdy_o,
+ output [7:0] dataout, output sof_o, output eof_o, output error_o, output
src_rdy_o, input dst_rdy_i);
+
+ fifo_short #(.WIDTH(11)) fifo_short
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i),
.dst_rdy_o(dst_rdy_o),
+ .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o),
.dst_rdy_i(dst_rdy_i));
+
+endmodule // ll8_shortfifo
Property changes on:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/ll8_shortfifo.v
___________________________________________________________________
Added: svn:mergeinfo
+
/gnuradio/branches/developers/eb/t348/usrp2/fpga/simple_gemac/ll8_shortfifo.v:10638-10648
/gnuradio/branches/developers/eb/t378/usrp2/fpga/simple_gemac/ll8_shortfifo.v:10683-10688
/gnuradio/branches/developers/jblum/gui_guts/usrp2/fpga/simple_gemac/ll8_shortfifo.v:10464-10658
/gnuradio/branches/developers/jblum/vlen/usrp2/fpga/simple_gemac/ll8_shortfifo.v:10667-10677
/gnuradio/branches/developers/jcorgan/fw-optimize/usrp2/fpga/simple_gemac/ll8_shortfifo.v:10428-10429
/gnuradio/branches/developers/jcorgan/gpio2/usrp2/fpga/simple_gemac/ll8_shortfifo.v:10713-10765
/gnuradio/branches/developers/michaelld/am_swig_4/usrp2/fpga/simple_gemac/ll8_shortfifo.v:10555-10595
/gnuradio/branches/developers/michaelld/two_mods/usrp2/fpga/simple_gemac/ll8_shortfifo.v:10540-10546
Added:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/newfifo_2clock.v
===================================================================
---
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/newfifo_2clock.v
(rev 0)
+++
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/control_lib/newfifo/newfifo_2clock.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -0,0 +1,82 @@
+
+module newfifo_2clock
+ #(parameter DWIDTH=32, AWIDTH=9)
+ (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o,
output reg [AWIDTH-1:0] level_wclk,
+ input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i,
output reg [AWIDTH-1:0] level_rclk,
+ input arst);
+
+ wire full, empty, write, read;
+
+ assign dst_rdy_o = ~full;
+ assign src_rdy_o = ~empty;
+ assign write = src_rdy_i & dst_rdy_o;
+ assign read = src_rdy_o & dst_rdy_i;
+
+//`define USE_XLNX_FIFO 1
+`ifdef USE_XLNX_FIFO
+ fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
+ (.rst(rst),
+
.wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(fifo_occupied[8:0]),
+ .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count()
);
+`else
+ // ISE sucks, so the following doesn't work properly
+
+ reg [AWIDTH-1:0] wr_addr, rd_addr;
+ wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk;
+ wire [AWIDTH-1:0] next_rd_addr;
+ wire enb_read;
+
+ // Write side management
+ wire [AWIDTH-1:0] next_wr_addr = wr_addr + 1;
+ always @(posedge wclk or posedge arst)
+ if(arst)
+ wr_addr <= 0;
+ else if(write)
+ wr_addr <= next_wr_addr;
+ assign full = (next_wr_addr == rd_addr_wclk);
+
+ // RAM for data storage. Data out is registered, complicating the
+ // read side logic
+ ram_2port #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) mac_rx_ff_ram
+ (.clka(wclk),.ena(1'b1),.wea(write),.addra(wr_addr),.dia(datain),.doa(),
+
.clkb(rclk),.enb(enb_read),.web(1'b0),.addrb(next_rd_addr),.dib(0),.dob(dataout)
);
+
+ // Read side management
+ reg data_valid;
+ assign empty = ~data_valid;
+ assign next_rd_addr = rd_addr + data_valid;
+ assign enb_read = read | ~data_valid;
+
+ always @(posedge rclk or posedge arst)
+ if(arst)
+ rd_addr <= 0;
+ else if(read)
+ rd_addr <= rd_addr + 1;
+
+ always @(posedge rclk or posedge arst)
+ if(arst)
+ data_valid <= 0;
+ else
+ if(read & (next_rd_addr == wr_addr_rclk))
+ data_valid <= 0;
+ else if(next_rd_addr != wr_addr_rclk)
+ data_valid <= 1;
+
+ // Send pointers across clock domains via gray code
+ gray_send #(.WIDTH(AWIDTH)) send_wr_addr
+ (.clk_in(wclk),.addr_in(wr_addr),
+ .clk_out(rclk),.addr_out(wr_addr_rclk) );
+
+ gray_send #(.WIDTH(AWIDTH)) send_rd_addr
+ (.clk_in(rclk),.addr_in(rd_addr),
+ .clk_out(wclk),.addr_out(rd_addr_wclk) );
+
+ // Generate fullness info, these are approximate and may be delayed
+ // and are only for higher-level flow control.
+ // Only full and empty are guaranteed exact.
+ always @(posedge wclk)
+ level_wclk <= wr_addr - rd_addr_wclk;
+ always @(posedge rclk)
+ level_rclk <= wr_addr_rclk - rd_addr;
+`endif
+endmodule // fifo_2clock
Modified:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/models/adc_model.v
===================================================================
--- gnuradio/branches/developers/matt/new_eth/usrp2/fpga/models/adc_model.v
2009-04-06 20:38:57 UTC (rev 10782)
+++ gnuradio/branches/developers/matt/new_eth/usrp2/fpga/models/adc_model.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -22,10 +22,9 @@
assign adc_ovf_b = adc_oe_b ? 1'b0 : 1'bz;
real phase = 0;
- real sample_rate = 100000000;
- real freq = 330000/sample_rate; // 330 kHz
+ real freq = 330000/100000000;
- real scale = math.pow(2,13)-2;
+ real scale = 8190; // math.pow(2,13)-2;
always @(posedge clk)
if(rst)
begin
Modified:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/sdr_lib/rx_control.v
===================================================================
--- gnuradio/branches/developers/matt/new_eth/usrp2/fpga/sdr_lib/rx_control.v
2009-04-06 20:38:57 UTC (rev 10782)
+++ gnuradio/branches/developers/matt/new_eth/usrp2/fpga/sdr_lib/rx_control.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -9,15 +9,12 @@
input [31:0] master_time,
output overrun,
- // To Buffer interface
+ // To FIFO interface of Buffer Pool
output [31:0] wr_dat_o,
- output wr_write_o,
- output wr_done_o,
- output wr_error_o,
-
+ output [3:0] wr_flags_o,
input wr_ready_i,
- input wr_full_i,
-
+ output wr_ready_o,
+
// From DSP Core
input [31:0] sample,
output run,
@@ -68,35 +65,10 @@
// Buffer interface to internal FIFO
wire write, full, read, empty;
wire sop_o, eop_o;
-
- reg xfer_state;
- localparam XFER_IDLE = 1'b0;
- localparam XFER_GO = 1'b1;
-
- always @(posedge clk)
- if(rst)
- xfer_state <= XFER_IDLE;
- else
- if(clear_overrun)
- xfer_state <= XFER_IDLE;
- else
- case(xfer_state)
- XFER_IDLE :
- if(wr_ready_i)
- xfer_state <= XFER_GO;
- XFER_GO :
- if((eop_o | wr_full_i) & wr_write_o)
- xfer_state <= XFER_IDLE;
- default :
- xfer_state <= XFER_IDLE;
- endcase // case(xfer_state)
+ assign wr_flags_o = {2'b00, eop_o, sop_o};
+ assign wr_ready_o = ~empty;
+ assign read = wr_ready_i & wr_ready_o;
- assign wr_write_o = (xfer_state == XFER_GO) & ~empty;
- assign wr_done_o = (eop_o & wr_write_o);
- assign wr_error_o = 0; // FIXME add check here for eop if we have
wr_full_i once we have IBS
-
- assign read = wr_write_o | (~empty & ~sop_o); // FIXME what if there
is junk between packets?
-
wire [33:0] fifo_line;
// Internal FIFO, size 9 is 2K, size 10 is 4K
@@ -206,8 +178,8 @@
((ibs_state == IBS_RUNNING) & strobe & ~full &
(lines_left==1) & chain) )
& ~empty_ctrl;
- assign debug_rx = { 6'd0,send_imm,chain,
- wr_write_o, wr_done_o, wr_ready_i,
wr_full_i,xfer_state,eop_o, sop_o, run,
+ assign debug_rx = { 8'd0,
+ 1'd0, send_imm, chain, wr_ready_i,wr_ready_o, eop_o,
sop_o, run,
write,full,read,empty,write_ctrl,full_ctrl,read_ctrl,empty_ctrl,
sc_pre1, clear_overrun, go_now, too_late, overrun,
ibs_state[2:0] };
endmodule // rx_control
Modified:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/sdr_lib/tx_control.v
===================================================================
--- gnuradio/branches/developers/matt/new_eth/usrp2/fpga/sdr_lib/tx_control.v
2009-04-06 20:38:57 UTC (rev 10782)
+++ gnuradio/branches/developers/matt/new_eth/usrp2/fpga/sdr_lib/tx_control.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -9,13 +9,11 @@
input [31:0] master_time,
output underrun,
- // To Buffer interface
+ // To FIFO interface from Buffer Pool
input [31:0] rd_dat_i,
- input rd_sop_i,
- input rd_eop_i,
- output rd_read_o,
- output rd_done_o,
- output rd_error_o,
+ input [3:0] rd_flags_i,
+ input rd_ready_i,
+ output rd_ready_o,
// To DSP Core
output [31:0] sample,
@@ -31,6 +29,10 @@
output [31:0] debug
);
+ wire rd_sop_i = rd_flags_i[0]; // Unused
+ wire rd_eop_i = rd_flags_i[1];
+ wire rd_occ_i = rd_flags_i[3:2]; // Unused, should always be 0
+
// Buffer interface to internal FIFO
wire write_data, write_ctrl, full_data, full_ctrl;
wire read_data, read_ctrl, empty_data, empty_ctrl;
@@ -39,57 +41,51 @@
reg [2:0] held_flags;
localparam XFER_IDLE = 0;
- localparam XFER_1 = 1;
- localparam XFER_2 = 2;
- localparam XFER_DATA = 3;
+ localparam XFER_CTRL = 1;
+ localparam XFER_PKT = 2;
+ // Add underrun state?
always @(posedge clk)
if(rst)
xfer_state <= XFER_IDLE;
+ else if(clear_state)
+ xfer_state <= XFER_IDLE;
else
- if(clear_state)
- xfer_state <= XFER_IDLE;
- else
+ if(rd_ready_i & rd_ready_o)
case(xfer_state)
XFER_IDLE :
- if(rd_sop_i)
- xfer_state <= XFER_1;
- XFER_1 :
begin
- xfer_state <= XFER_2;
+ xfer_state <= XFER_CTRL;
held_flags <= rd_dat_i[2:0];
end
- XFER_2 :
- if(~full_ctrl)
- xfer_state <= XFER_DATA;
- XFER_DATA :
- if(rd_eop_i & ~full_data)
+ XFER_CTRL :
+ xfer_state <= XFER_PKT;
+ XFER_PKT :
+ if(rd_eop_i)
xfer_state <= XFER_IDLE;
endcase // case(xfer_state)
- assign write_data = (xfer_state == XFER_DATA) & ~full_data;
- assign write_ctrl = (xfer_state == XFER_2) & ~full_ctrl;
+ assign write_data = (xfer_state == XFER_PKT) & rd_ready_i & rd_ready_o;
+ assign write_ctrl = (xfer_state == XFER_CTRL) & rd_ready_i & rd_ready_o;
- assign rd_read_o = (xfer_state == XFER_1) | write_data | write_ctrl;
- assign rd_done_o = 0; // Always take everything we're given
- assign rd_error_o = 0; // Should we indicate overruns here?
+ assign rd_ready_o = ~full_data & ~full_ctrl;
wire [31:0] data_o;
- wire sop_o, eop_o, eob, sob, send_imm;
+ wire eop_o, eob, sob, send_imm;
wire [31:0] sendtime;
wire [4:0] occ_ctrl;
- cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) txctrlfifo
+ cascadefifo2 #(.WIDTH(33),.SIZE(FIFOSIZE)) txctrlfifo
(.clk(clk),.rst(rst),.clear(clear_state),
- .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write_data),
.full(full_data),
- .dataout({sop_o,eop_o,data_o}), .read(read_data), .empty(empty_data),
+ .datain({rd_eop_i,rd_dat_i[31:0]}), .write(write_data), .full(full_data),
+ .dataout({eop_o,data_o}), .read(read_data), .empty(empty_data),
.space(), .occupied(fifo_occupied) );
assign fifo_full = full_data;
assign fifo_empty = empty_data;
shortfifo #(.WIDTH(35)) ctrlfifo
(.clk(clk),.rst(rst),.clear(clear_state),
- .datain({held_flags[2:0],rd_dat_i}), .write(write_ctrl),
.full(full_ctrl),
+ .datain({held_flags[2:0],rd_dat_i[31:0]}), .write(write_ctrl),
.full(full_ctrl),
.dataout({send_imm,sob,eob,sendtime}), .read(read_ctrl),
.empty(empty_ctrl),
.space(), .occupied(occ_ctrl) );
Modified: gnuradio/branches/developers/matt/new_eth/usrp2/fpga/serdes/serdes.v
===================================================================
--- gnuradio/branches/developers/matt/new_eth/usrp2/fpga/serdes/serdes.v
2009-04-06 20:38:57 UTC (rev 10782)
+++ gnuradio/branches/developers/matt/new_eth/usrp2/fpga/serdes/serdes.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -7,12 +7,10 @@
(input clk, input rst,
// TX side
output ser_tx_clk, output [15:0] ser_t, output ser_tklsb, output
ser_tkmsb,
- input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output
rd_error_o,
- input rd_sop_i, input rd_eop_i,
+ input [31:0] rd_dat_i, input [3:0] rd_flags_i, output rd_ready_o, input
rd_ready_i,
// RX side
input ser_rx_clk, input [15:0] ser_r, input ser_rklsb, input ser_rkmsb,
- output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output
wr_error_o,
- input wr_ready_i, input wr_full_i,
+ output [31:0] wr_dat_o, output [3:0] wr_flags_o, output wr_ready_o, input
wr_ready_i,
output [15:0] tx_occupied, output tx_full, output tx_empty,
output [15:0] rx_occupied, output rx_full, output rx_empty,
@@ -29,8 +27,7 @@
serdes_tx #(.FIFOSIZE(TXFIFOSIZE)) serdes_tx
(.clk(clk),.rst(rst),
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
-
.rd_dat_i(rd_dat_i),.rd_read_o(rd_read_o),.rd_done_o(rd_done_o),.rd_error_o(rd_error_o),
- .rd_sop_i(rd_sop_i),.rd_eop_i(rd_eop_i),
+
.rd_dat_i(rd_dat_i),.rd_flags_i(rd_flags_i),.rd_ready_o(rd_ready_o),.rd_ready_i(rd_ready_i),
.inhibit_tx(inhibit_tx), .send_xon(send_xon), .send_xoff(send_xoff),
.sent(sent),
.fifo_occupied(tx_occupied),.fifo_full(tx_full),.fifo_empty(tx_empty),
.debug(debug_tx) );
@@ -38,8 +35,7 @@
serdes_rx #(.FIFOSIZE(RXFIFOSIZE)) serdes_rx
(.clk(clk),.rst(rst),
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
-
.wr_dat_o(wr_dat_o),.wr_write_o(wr_write_o),.wr_done_o(wr_done_o),.wr_error_o(wr_error_o),
- .wr_ready_i(wr_ready_i),.wr_full_i(wr_full_i),
+
.wr_dat_o(wr_dat_o),.wr_flags_o(wr_flags_o),.wr_ready_o(wr_ready_o),.wr_ready_i(wr_ready_i),
.fifo_space(fifo_space), .xon_rcvd(xon_rcvd), .xoff_rcvd(xoff_rcvd),
.fifo_occupied(rx_occupied),.fifo_full(rx_full),.fifo_empty(rx_empty),
.serdes_link_up(serdes_link_up), .debug(debug_rx) );
@@ -55,13 +51,13 @@
//assign debug = { fifo_space, send_xon, send_xoff, debug_rx[13:0] };
//assign debug = debug_rx;
- assign debug0 = { { debug_tx[3:0] /* xfer_active,state[2:0] */,
rd_read_o, rd_done_o, rd_sop_i, rd_eop_i },
+ assign debug0 = { { 2'b00, rd_ready_o, rd_ready_i, rd_flags_i[3:0]},
{ debug_tx[5:4] /* full,empty */ , inhibit_tx,
send_xon, send_xoff, sent, ser_tkmsb, ser_tklsb},
{ ser_t[15:8] },
{ ser_t[7:0] } };
assign debug1 = { { debug_rx[7:0] }, /*
odd,xfer_active,sop_i,eop_i,error_i,state[2:0] */
- { wr_write_o, wr_error_o, wr_ready_i, wr_done_o,
xon_rcvd, xoff_rcvd, ser_rkmsb, ser_rklsb },
+ { wr_flags_o[1:0], wr_ready_i, wr_ready_o, xon_rcvd,
xoff_rcvd, ser_rkmsb, ser_rklsb },
{ ser_r[15:8] },
{ ser_r[7:0] } };
endmodule // serdes
Modified:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/serdes/serdes_rx.v
===================================================================
--- gnuradio/branches/developers/matt/new_eth/usrp2/fpga/serdes/serdes_rx.v
2009-04-06 20:38:57 UTC (rev 10782)
+++ gnuradio/branches/developers/matt/new_eth/usrp2/fpga/serdes/serdes_rx.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -32,12 +32,10 @@
input ser_rkmsb,
output [31:0] wr_dat_o,
- output wr_write_o,
- output wr_done_o,
- output wr_error_o,
+ output [3:0] wr_flags_o,
input wr_ready_i,
- input wr_full_i,
-
+ output wr_ready_o,
+
output [15:0] fifo_space,
output xon_rcvd, output xoff_rcvd,
@@ -83,6 +81,7 @@
wire [15:0] nextCRC;
reg write_d;
+ wire rst_rxclk;
oneshot_2clk
rst_1s(.clk_in(clk),.in(rst),.clk_out(ser_rx_clk),.out(rst_rxclk));
/*
@@ -311,34 +310,21 @@
.wr_data_count() );
assign fifo_space = {{(16-FIFOSIZE){1'b0}},{FIFOSIZE{1'b1}}} -
{{(16-FIFOSIZE){1'b0}},level};
- assign fifo_occupied = { {(16-FIFOSIZE){1'b0}}, level };
- assign fifo_full = full; // Note -- fifo_full is in the wrong
clock domain
- assign fifo_empty = empty;
+ assign fifo_occupied = { {(16-FIFOSIZE){1'b0}}, level };
+ assign fifo_full = full; // Note -- fifo_full is in the
wrong clock domain
+ assign fifo_empty = empty;
`endif // `ifdef XILFIFO
// Internal FIFO to Buffer interface
- reg xfer_active;
-
- always @(posedge clk)
- if(rst)
- xfer_active <= 0;
- else if(xfer_active & ~empty & (eop_o | wr_full_i | error_o))
- xfer_active <= 0;
- else if(wr_ready_i & sop_o)
- xfer_active <= 1;
-
- assign read = (xfer_active | ~sop_o) & ~empty;
-
- assign wr_write_o = xfer_active & ~empty;
- assign wr_done_o = eop_o & ~empty & xfer_active;
- //assign wr_error_o = xfer_active & ((wr_full_i & ~eop_o &
~empty)|error_o);
- assign wr_error_o = xfer_active & ~empty & error_o;
-
- assign wr_dat_o = line_o;
-
- wire slu = ~(({2'b11,K_ERROR,K_ERROR}=={ser_rkmsb,ser_rklsb,ser_r})
||
+ assign read = wr_ready_i & wr_ready_o;
+ assign wr_ready_o = ~empty;
+ assign wr_dat_o = line_o;
+ assign wr_flags_o = { 2'b00, eop_o | error_o, sop_o | error_o };
+
+ wire slu = ~(({2'b11,K_ERROR,K_ERROR}=={ser_rkmsb,ser_rklsb,ser_r}) ||
({2'b11,K_LOS,K_LOS}=={ser_rkmsb,ser_rklsb,ser_r}));
+
reg [3:0] slu_reg;
always @(posedge clk)
@@ -348,6 +334,6 @@
always @(posedge clk)
serdes_link_up <= &slu_reg[3:1];
- assign debug = { full, empty, odd, xfer_active, sop_i, eop_i, error_i,
state[2:0] };
+ assign debug = { full, empty, odd, sop_i, eop_i, error_i, state[2:0] };
endmodule // serdes_rx
Modified:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/serdes/serdes_tx.v
===================================================================
--- gnuradio/branches/developers/matt/new_eth/usrp2/fpga/serdes/serdes_tx.v
2009-04-06 20:38:57 UTC (rev 10782)
+++ gnuradio/branches/developers/matt/new_eth/usrp2/fpga/serdes/serdes_tx.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -33,11 +33,9 @@
// TX Stream Interface
input [31:0] rd_dat_i,
- output rd_read_o,
- output rd_done_o,
- output rd_error_o,
- input rd_sop_i,
- input rd_eop_i,
+ input [3:0] rd_flags_i,
+ output rd_ready_o,
+ input rd_ready_i,
// Flow control interface
input inhibit_tx,
@@ -82,33 +80,24 @@
wire sop_o, eop_o, write, full, read, empty;
wire [31:0] data_o;
reg xfer_active;
+
+ wire rd_sop_i = rd_flags_i[0];
+ wire rd_eop_i = rd_flags_i[1];
+ wire [1:0] rd_occ_i = rd_flags_i[3:2]; // Unused
cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo
(.clk(clk),.rst(rst),.clear(0),
.datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write), .full(full),
.dataout({sop_o,eop_o,data_o}), .read(read), .empty(empty),
.space(), .occupied(fifo_occupied) );
- assign fifo_full = full;
- assign fifo_empty = empty;
+ assign fifo_full = full;
+ assign fifo_empty = empty;
+
+ assign write = rd_ready_i & rd_ready_o;
+ assign rd_ready_o = ~full;
+
- // Buffer interface to internal FIFO
- always @(posedge clk)
- if(rst)
- xfer_active <= 0;
- else if(rd_eop_i & ~full) // In case we can't store last line right away
- xfer_active <= 0;
- else if(rd_sop_i)
- xfer_active <= 1;
-
- assign write = xfer_active & ~full;
-
- assign rd_read_o = write;
- assign rd_done_o = 0; // Always take everything we're given
- assign rd_error_o = 0; // No chance for errors anticipated
-
-
- // FIXME Implement flow control
-
+ // FIXME Implement flow control
reg [15:0] second_word;
reg [33:0] pipeline;
Modified:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/delay_line.v
===================================================================
---
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/delay_line.v
2009-04-06 20:38:57 UTC (rev 10782)
+++
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/delay_line.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -7,7 +7,7 @@
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout);
- integer i;
+ genvar i;
generate
for (i=0;i<WIDTH;i=i+1)
begin : gen_delay
Modified:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/rxmac_to_ll8.v
===================================================================
---
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/rxmac_to_ll8.v
2009-04-06 20:38:57 UTC (rev 10782)
+++
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/rxmac_to_ll8.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -6,6 +6,13 @@
reg [2:0] xfer_state;
+ localparam XFER_IDLE = 0;
+ localparam XFER_ACTIVE = 1;
+ localparam XFER_ERROR = 2;
+ localparam XFER_ERROR2 = 3;
+ localparam XFER_OVERRUN = 4;
+ localparam XFER_OVERRUN2 = 5;
+
assign ll_data = rx_data;
assign ll_src_rdy = ((rx_valid & (xfer_state != XFER_OVERRUN2) )
| (xfer_state == XFER_ERROR)
@@ -14,13 +21,6 @@
assign ll_eof = (rx_ack | (xfer_state==XFER_ERROR) |
(xfer_state==XFER_OVERRUN));
assign ll_error = (xfer_state ==
XFER_ERROR)|(xfer_state==XFER_OVERRUN);
- localparam XFER_IDLE = 0;
- localparam XFER_ACTIVE = 1;
- localparam XFER_ERROR = 2;
- localparam XFER_ERROR2 = 3;
- localparam XFER_OVERRUN = 4;
- localparam XFER_OVERRUN2 = 5;
-
always @(posedge clk)
if(reset | clear)
xfer_state <= XFER_IDLE;
Modified:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/simple_gemac_rx.v
===================================================================
---
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/simple_gemac_rx.v
2009-04-06 20:38:57 UTC (rev 10782)
+++
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/simple_gemac_rx.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -8,7 +8,24 @@
input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause,
input pass_all,
output reg [15:0] pause_quanta_rcvd, output pause_rcvd );
- reg [7:0] rxd_d1;
+ localparam RX_IDLE = 0;
+ localparam RX_PREAMBLE = 1;
+ localparam RX_FRAME = 2;
+ localparam RX_GOODFRAME = 3;
+ localparam RX_DO_PAUSE = 4;
+ localparam RX_ERROR = 5;
+ localparam RX_DROP = 6;
+
+ localparam RX_PAUSE = 16;
+ localparam RX_PAUSE_CHK88 = RX_PAUSE + 5;
+ localparam RX_PAUSE_CHK08 = RX_PAUSE_CHK88 + 1;
+ localparam RX_PAUSE_CHK00 = RX_PAUSE_CHK08 + 1;
+ localparam RX_PAUSE_CHK01 = RX_PAUSE_CHK00 + 1;
+ localparam RX_PAUSE_STORE_MSB = RX_PAUSE_CHK01 + 1;
+ localparam RX_PAUSE_STORE_LSB = RX_PAUSE_STORE_MSB + 1;
+ localparam RX_PAUSE_WAIT_CRC = RX_PAUSE_STORE_LSB + 1;
+
+ reg [7:0] rxd_d1;
reg rx_dv_d1, rx_er_d1;
assign rx_clk = GMII_RX_CLK;
@@ -19,10 +36,15 @@
rxd_d1 <= GMII_RXD;
end
+ reg [7:0] rx_state;
wire [7:0] rxd_del;
wire rx_dv_del, rx_er_del;
reg go_filt;
+ wire match_crc;
+ wire clear_crc = rx_state == RX_IDLE;
+ wire calc_crc = (rx_state == RX_FRAME) | rx_state[7:4]==4'h1;
+
localparam DELAY = 6;
delay_line #(.WIDTH(10)) rx_delay
(.clk(rx_clk), .delay(DELAY),
.din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_dl,rxd_del}));
@@ -37,7 +59,6 @@
wire keep_packet = (pass_ucast & is_ucast) | (pass_mcast & is_mcast) |
(pass_bcast & is_bcast) | (pass_pause & is_pause) | pass_all;
- reg [7:0] rx_state;
assign rx_data = rxd_del;
assign rx_error = (rx_state == RX_ERROR);
@@ -58,24 +79,6 @@
address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt),
.data(rxd_d1),
.address(48'h0180_c200_0001), .match(is_pause),
.done());
- localparam RX_IDLE = 0;
- localparam RX_PREAMBLE = 1;
- localparam RX_FRAME = 2;
- localparam RX_GOODFRAME = 3;
- localparam RX_DO_PAUSE = 4;
- localparam RX_ERROR = 5;
- localparam RX_DROP = 6;
-
- localparam RX_PAUSE = 16;
- localparam RX_PAUSE_CHK88 = RX_PAUSE + 5;
- localparam RX_PAUSE_CHK08 = RX_PAUSE_CHK88 + 1;
- localparam RX_PAUSE_CHK00 = RX_PAUSE_CHK08 + 1;
- localparam RX_PAUSE_CHK01 = RX_PAUSE_CHK00 + 1;
- localparam RX_PAUSE_STORE_MSB = RX_PAUSE_CHK01 + 1;
- localparam RX_PAUSE_STORE_LSB = RX_PAUSE_STORE_MSB + 1;
- localparam RX_PAUSE_WAIT_CRC = RX_PAUSE_STORE_LSB + 1;
-
-
always @(posedge rx_clk)
go_filt <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5);
@@ -155,9 +158,6 @@
endcase // case (rx_state)
assign pause_rcvd = (rx_state == RX_DO_PAUSE);
- wire match_crc;
- wire clear_crc = rx_state == RX_IDLE;
- wire calc_crc = (rx_state == RX_FRAME) | rx_state[7:4]==4'h1;
crc crc_check(.clk(rx_clk),.reset(reset),.clear(clear_crc),
.data(rxd_d1),.calc(calc_crc),.crc_out(),.match(match_crc));
Modified:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/simple_gemac_tx.v
===================================================================
---
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/simple_gemac_tx.v
2009-04-06 20:38:57 UTC (rev 10782)
+++
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/simple_gemac_tx.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -23,14 +23,6 @@
wire [31:0] crc_out;
- localparam MIN_FRAME_LEN = 64 + 8 - 4; // Min frame length includes
preamble but not CRC
- localparam MAX_FRAME_LEN = 8192; // How big are the jumbo frames we
want to handle?
- always @(posedge tx_clk)
- if(reset |(tx_state == TX_IDLE))
- frame_len_ctr <= 0;
- else
- frame_len_ctr <= frame_len_ctr + 1;
-
localparam TX_IDLE = 0;
localparam TX_PREAMBLE = 1;
localparam TX_SOF_DEL = TX_PREAMBLE + 7;
@@ -48,6 +40,14 @@
localparam TX_PAUSE_FIRST = TX_PAUSE_SOF + 1;
localparam TX_PAUSE_END = TX_PAUSE_SOF + 18;
+ localparam MIN_FRAME_LEN = 64 + 8 - 4; // Min frame length includes
preamble but not CRC
+ localparam MAX_FRAME_LEN = 8192; // How big are the jumbo frames we
want to handle?
+ always @(posedge tx_clk)
+ if(reset |(tx_state == TX_IDLE))
+ frame_len_ctr <= 0;
+ else
+ frame_len_ctr <= frame_len_ctr + 1;
+
reg send_pause;
reg [15:0] pause_time_held;
Modified:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
===================================================================
---
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
2009-04-06 20:38:57 UTC (rev 10782)
+++
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -8,14 +8,11 @@
// Flow Control Interface
input pause_req, input [15:0] pause_time,
- // RX Client Interface
- output rx_clk, output [7:0] rx_ll_data, output rx_ll_sof, output rx_ll_eof,
- output rx_ll_error, output rx_ll_src_rdy, input rx_ll_dst_rdy,
+ // Client FIFO Interfaces
+ input sys_clk,
+ output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy,
+ input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy,
- // TX Client Interface
- output tx_clk, input [7:0] tx_ll_data, input tx_ll_sof, input tx_ll_eof,
- input tx_ll_src_rdy, output tx_ll_dst_rdy,
-
// Wishbone Interface
input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack,
input wb_we,
input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o,
@@ -59,14 +56,66 @@
.pass_ucast(pass_ucast), .pass_mcast(pass_mcast),
.pass_bcast(pass_bcast),
.pass_pause(pass_pause), .pass_all(pass_all), .pause_en(pause_en) );
+ // RX FIFO Chain
+ wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+ wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2_n, rx_ll_dst_rdy2;
+ wire [7:0] rx_ll_data, rx_ll_data2;
+ wire [35:0] rx_f36_data_int1;
+ wire rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1;
+
rxmac_to_ll8 rx_adapt
(.clk(rx_clk), .reset(rx_reset), .clear(0),
.rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error),
.rx_ack(rx_ack),
.ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof),
.ll_error(rx_ll_error),
.ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
+
+ ll8_shortfifo rx_sfifo
+ (.clk(rx_clk), .reset(rx_reset), .clear(0),
+ .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
+ .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy),
.dst_rdy_o(rx_ll_dst_rdy),
+ .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
+ .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2),
.dst_rdy_i(~rx_ll_dst_rdy2_n));
+
+ ll8_to_fifo36 ll8_to_fifo36
+ (.clk(rx_clk), .reset(rx_reset), .clear(0),
+ .ll_data(rx_ll_data2), .ll_sof_n(~rx_ll_sof2), .ll_eof_n(~rx_ll_eof2),
+ .ll_src_rdy_n(~rx_ll_src_rdy2), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
+ .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1),
.f36_dst_rdy_i(rx_f36_dst_rdy_int1));
+
+ cascadefifo_2clock #(.DWIDTH(36), .AWIDTH(9)) rx_2clk_fifo
+ (.wclk(rx_clk), .datain(rx_f36_data_int1),
+ .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1),
.level_wclk(),
+ .rclk(sys_clk), .dataout(rx_f36_data),
+ .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .level_rclk(),
.arst(reset));
+ // TX FIFO Chain
+ wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
+ wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2;
+ wire [7:0] tx_ll_data, tx_ll_data2;
+ wire [35:0] tx_f36_data_int1;
+ wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
+
+ cascadefifo_2clock #(.DWIDTH(36), .AWIDTH(9)) tx_2clk_fifo
+ (.wclk(sys_clk), .datain(tx_f36_data),
+ .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .level_wclk(),
+ .rclk(tx_clk), .dataout(tx_f36_data_int1),
+ .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1),
.level_rclk(), .arst(reset));
+
+ fifo36_to_ll8 fifo36_to_ll8
+ (.clk(tx_clk), .reset(tx_reset), .clear(clear),
+ .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1),
.f36_dst_rdy_o(tx_f36_dst_rdy_int1),
+ .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n),
+ .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(~tx_ll_dst_rdy2));
+
+ ll8_shortfifo tx_sfifo
+ (.clk(rx_clk), .reset(tx_reset), .clear(clear),
+ .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
+ .error_i(0), .src_rdy_i(~tx_ll_src_rdy2_n), .dst_rdy_o(tx_ll_dst_rdy2),
+ .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
+ .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
+
ll8_to_txmac ll8_to_txmac
- (.clk(tx_clk), .reset(tx_reset), .clear(0),
+ (.clk(tx_clk), .reset(tx_reset), .clear(clear),
.ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
.ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
.tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error),
.tx_ack(tx_ack));
Modified: gnuradio/branches/developers/matt/new_eth/usrp2/fpga/testbench/cmdfile
===================================================================
--- gnuradio/branches/developers/matt/new_eth/usrp2/fpga/testbench/cmdfile
2009-04-06 20:38:57 UTC (rev 10782)
+++ gnuradio/branches/developers/matt/new_eth/usrp2/fpga/testbench/cmdfile
2009-04-06 21:48:18 UTC (rev 10783)
@@ -3,6 +3,7 @@
-y .
-y ../top/u2_core
-y ../control_lib
+-y ../control_lib/newfifo
-y ../serdes
-y ../sdr_lib
-y ../timing
Modified:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/top/u2_core/u2_core.v
===================================================================
--- gnuradio/branches/developers/matt/new_eth/usrp2/fpga/top/u2_core/u2_core.v
2009-04-06 20:38:57 UTC (rev 10782)
+++ gnuradio/branches/developers/matt/new_eth/usrp2/fpga/top/u2_core/u2_core.v
2009-04-06 21:48:18 UTC (rev 10783)
@@ -307,19 +307,21 @@
.in(set_data),.out(),.changed(flush_icache));
// Buffer Pool, slave #1
- wire rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop;
- wire rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop;
- wire rd2_read, rd2_sop, rd2_error, rd2_done, rd2_eop;
- wire rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop;
+ wire rd0_ready_i, rd0_ready_o;
+ wire rd1_ready_i, rd1_ready_o;
+ wire rd2_ready_i, rd2_ready_o;
+ wire rd3_ready_i, rd3_ready_o;
+ wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags;
wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat;
- wire wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full;
- wire wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full;
- wire wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full;
- wire wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full;
+ wire wr0_ready_i, wr0_ready_o;
+ wire wr1_ready_i, wr1_ready_o;
+ wire wr2_ready_i, wr2_ready_o;
+ wire wr3_ready_i, wr3_ready_o;
+ wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags;
wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat;
- buffer_pool buffer_pool
+ buffer_pool #(.BUF_SIZE(9), .SET_ADDR(64)) buffer_pool
(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
.wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),
.wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty),
@@ -330,25 +332,17 @@
.s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
.s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
-
+
// Write Interfaces
- .wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done),
- .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full),
- .wr1_dat_i(wr1_dat), .wr1_write_i(wr1_write), .wr1_done_i(wr1_done),
- .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full),
- .wr2_dat_i(wr2_dat), .wr2_write_i(wr2_write), .wr2_done_i(wr2_done),
- .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full),
- .wr3_dat_i(wr3_dat), .wr3_write_i(wr3_write), .wr3_done_i(wr3_done),
- .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full),
+ .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags),
.wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o),
+ .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags),
.wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o),
+ .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags),
.wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o),
+ .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags),
.wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o),
// Read Interfaces
- .rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done),
- .rd0_error_i(rd0_error), .rd0_sop_o(rd0_sop), .rd0_eop_o(rd0_eop),
- .rd1_dat_o(rd1_dat), .rd1_read_i(rd1_read), .rd1_done_i(rd1_done),
- .rd1_error_i(rd1_error), .rd1_sop_o(rd1_sop), .rd1_eop_o(rd1_eop),
- .rd2_dat_o(rd2_dat), .rd2_read_i(rd2_read), .rd2_done_i(rd2_done),
- .rd2_error_i(rd2_error), .rd2_sop_o(rd2_sop), .rd2_eop_o(rd2_eop),
- .rd3_dat_o(rd3_dat), .rd3_read_i(rd3_read), .rd3_done_i(rd3_done),
- .rd3_error_i(rd3_error), .rd3_sop_o(rd3_sop), .rd3_eop_o(rd3_eop)
+ .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags),
.rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o),
+ .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags),
.rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o),
+ .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags),
.rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o),
+ .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags),
.rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o)
);
// SPI -- Slave #2
@@ -398,11 +392,30 @@
.word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0)
);
- assign s5_err = 1'b0;
- assign s5_rty = 1'b0;
+ assign s5_err = 1'b0;
+ assign s5_rty = 1'b0;
- // Slave, #6 Ethernet MAC, see below
+ // /////////////////////////////////////////////////////////////////////////
+ // Ethernet MAC Slave #6
+
+ simple_gemac_wrapper simple_gemac_wrapper
+ (.clk125(clk_to_mac), .reset(wb_rst),
+ .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
+ .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+ .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
+ .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+ .pause_req(0), .pause_time(0),
+ .sys_clk(dsp_clk),
+ .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i),
.rx_f36_dst_rdy(wr2_ready_o),
+ .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o),
.tx_f36_dst_rdy(rd2_ready_i),
+ .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc),
.wb_ack(s6_ack),
+ .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
+ .mdio(MDIO), .mdc(MDC) );
+ assign s6_err = 1'b0;
+ assign s6_rty = 1'b0;
+
+ // /////////////////////////////////////////////////////////////////////////
// Settings Bus -- Slave #7
settings_bus settings_bus
(.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
@@ -448,55 +461,6 @@
assign leds = (led_src & led_hw) | (~led_src & led_sw);
// /////////////////////////////////////////////////////////////////////////
- // Ethernet MAC Slave #6
-
- wire Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop;
- wire Rx_mac_empty, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_err;
- wire [31:0] Tx_mac_data, Rx_mac_data;
- wire [1:0] Tx_mac_BE, Rx_mac_BE;
- wire rst_mac;
-
- oneshot_2clk mac_rst_1shot
(.clk_in(wb_clk),.in(wb_rst),.clk_out(clk_to_mac),.out(rst_mac));
-
- MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11))
- MAC_top
- (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk),
- .rst_mac(rst_mac),.rst_user(dsp_rst),
-
.RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]),
- .WE_I(s6_we),.DAT_I(s6_dat_o),.DAT_O(s6_dat_i),.ACK_O(s6_ack),
-
.Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE),
- .Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
- .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
- .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
-
.Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),
-
.Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),
- .Crs(GMII_CRS),.Col(GMII_COL),
- .Mdio(MDIO),.Mdc(MDC),
-
.rx_fifo_occupied(eth_rx_occ2),.rx_fifo_full(eth_rx_full2),.rx_fifo_empty(eth_rx_empty2),
- .tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(),
- .debug0(debug_mac0),.debug1(debug_mac1) );
-
- assign s6_err = 1'b0;
- assign s6_rty = 1'b0;
-
- mac_rxfifo_int mac_rxfifo_int
- (.clk(dsp_clk),.rst(dsp_rst),
-
.Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),
- .Rx_mac_BE(Rx_mac_BE),.Rx_mac_sop(Rx_mac_sop),
- .Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
- .wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done),
- .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full),
-
.fifo_occupied(eth_rx_occ),.fifo_full(eth_rx_full),.fifo_empty(eth_rx_empty) );
-
- mac_txfifo_int mac_txfifo_int
- (.clk(dsp_clk),.rst(dsp_rst),.mac_clk(clk_to_mac),
- .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
- .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
- .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done),
- .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop),
-
.fifo_occupied(eth_tx_occ),.fifo_full(eth_tx_full),.fifo_empty(eth_tx_empty) );
-
- // /////////////////////////////////////////////////////////////////////////
// Interrupt Controller, Slave #8
wire [15:0] irq={{4'b0, clk_status, serdes_link_up, uart_tx_int,
uart_rx_int},
@@ -546,7 +510,7 @@
(.clk_i(wb_clk),.rst_i(wb_rst),
.adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i),
.we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack),
- .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
+ .run_rx(run_rx_d1),.run_tx(run_tx),.master_time(),
.ctrl_lines(atr_lines) );
assign s11_err = 0;
assign s11_rty = 0;
@@ -591,8 +555,7 @@
(.clk(dsp_clk), .rst(dsp_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.master_time(master_time),.overrun(overrun),
- .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done),
.wr_error_o(wr1_error),
- .wr_ready_i(wr1_ready), .wr_full_i(wr1_full),
+ .wr_dat_o(wr1_dat), .wr_flags_o(wr1_flags), .wr_ready_o(wr1_ready_i),
.wr_ready_i(wr1_ready_o),
.sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
.fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
.debug_rx(debug_rx) );
@@ -602,15 +565,14 @@
(.clk(dsp_clk),.rst(dsp_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
- .io_rx(io_rx),.sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
+ .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
.debug(debug_rx_dsp) );
tx_control #(.FIFOSIZE(10)) tx_control
(.clk(dsp_clk), .rst(dsp_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.master_time(master_time),.underrun(underrun),
- .rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop),
- .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error),
+ .rd_dat_i(rd1_dat), .rd_flags_i(rd_flags), .rd_ready_i(rd1_ready_o),
.rd_ready_o(rd1_ready_i),
.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
.fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty),
.debug(debug_txc) );
@@ -629,11 +591,9 @@
serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes
(.clk(dsp_clk),.rst(dsp_rst),
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
-
.rd_dat_i(rd0_dat),.rd_read_o(rd0_read),.rd_done_o(rd0_done),.rd_error_o(rd0_error),
- .rd_sop_i(rd0_sop),.rd_eop_i(rd0_eop),
+
.rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o),
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
-
.wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error),
- .wr_ready_i(wr0_ready),.wr_full_i(wr0_full),
+
.wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o),
.tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
.rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
.serdes_link_up(serdes_link_up),.debug0(debug_serdes0),
.debug1(debug_serdes1) );
Modified:
gnuradio/branches/developers/matt/new_eth/usrp2/fpga/top/u2_rev3/Makefile
===================================================================
--- gnuradio/branches/developers/matt/new_eth/usrp2/fpga/top/u2_rev3/Makefile
2009-04-06 20:38:57 UTC (rev 10782)
+++ gnuradio/branches/developers/matt/new_eth/usrp2/fpga/top/u2_rev3/Makefile
2009-04-06 21:48:18 UTC (rev 10783)
@@ -56,14 +56,16 @@
control_lib/CRC16_D16.v \
control_lib/atr_controller.v \
control_lib/bin2gray.v \
-control_lib/buffer_int.v \
-control_lib/buffer_pool.v \
+control_lib/newfifo/buffer_int.v \
+control_lib/newfifo/buffer_pool.v \
control_lib/cascadefifo2.v \
control_lib/dcache.v \
control_lib/decoder_3_8.v \
control_lib/dpram32.v \
control_lib/fifo_2clock.v \
control_lib/fifo_2clock_casc.v \
+control_lib/newfifo/newfifo_2clock.v \
+control_lib/newfifo/cascadefifo_2clock.v \
control_lib/gray2bin.v \
control_lib/gray_send.v \
control_lib/icache.v \
@@ -89,6 +91,22 @@
control_lib/sd_spi.v \
control_lib/sd_spi_wb.v \
control_lib/wb_bridge_16_32.v \
+control_lib/reset_sync.v \
+simple_gemac/simple_gemac_wrapper.v \
+simple_gemac/simple_gemac.v \
+simple_gemac/simple_gemac_wb.v \
+simple_gemac/simple_gemac_tx.v \
+simple_gemac/simple_gemac_rx.v \
+simple_gemac/crc.v \
+simple_gemac/delay_line.v \
+simple_gemac/flow_ctrl_tx.v \
+simple_gemac/address_filter.v \
+control_lib/newfifo/ll8_shortfifo.v \
+control_lib/newfifo/ll8_to_fifo36.v \
+simple_gemac/ll8_to_txmac.v \
+simple_gemac/rxmac_to_ll8.v \
+control_lib/newfifo/fifo_short.v \
+control_lib/newfifo/fifo36_to_ll8.v \
coregen/fifo_xlnx_2Kx36_2clk.v \
coregen/fifo_xlnx_2Kx36_2clk.xco \
coregen/fifo_xlnx_512x36_2clk.v \
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- [Commit-gnuradio] r10783 - in gnuradio/branches/developers/matt/new_eth/usrp2/fpga: control_lib control_lib/newfifo models sdr_lib serdes simple_gemac testbench top/u2_core top/u2_rev3,
matt <=