[Commit-gnuradio] r10769 - gnuradio/trunk/usrp2/fpga/simple_gemac

[matt]

Author: matt
Date: 2009-04-04 02:34:31 -0600 (Sat, 04 Apr 2009)
New Revision: 10769

Added:
   gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_wrapper_tb.v
Modified:
   gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_wb.v
   gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
Log:
basic wrapper working


Modified: gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_wb.v
===================================================================
--- gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_wb.v    2009-04-04 
06:20:57 UTC (rev 10768)
+++ gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_wb.v    2009-04-04 
08:34:31 UTC (rev 10769)
@@ -18,7 +18,7 @@
 
 module simple_gemac_wb
   (input wb_clk, input wb_rst,
-   input wb_cyc, input wb_stb, input wb_ack, input wb_we,
+   input wb_cyc, input wb_stb, output reg wb_ack, input wb_we,
    input [7:0] wb_adr, input [31:0] wb_dat_i, output reg [31:0] wb_dat_o,
    
    inout mdio, output mdc,
@@ -26,22 +26,34 @@
    output pass_ucast, output pass_mcast, output pass_bcast,
    output pass_pause, output pass_all, output pause_en  );
 
+   wire   acc    = wb_cyc & wb_stb;
    wire   wr_acc  = wb_cyc & wb_stb & wb_we;
    wire   rd_acc  = wb_cyc & wb_stb & ~wb_we;
-   
+
+   always @(posedge wb_clk)
+     if(wb_rst)
+       wb_ack   <= 0;
+     else
+       wb_ack   <= acc & ~wb_ack;
+       
    wire [5:0] misc_settings;
    assign {pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_en} 
        = misc_settings;
 
    wb_reg #(.ADDR(0),.DEFAULT(6'b111001))
-   wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), 
.dat_i(wb_dat_i), .dat_o(misc_settings) );
+   wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), 
.wr_acc(wr_acc),
+                   .dat_i(wb_dat_i), .dat_o(misc_settings) );
    wb_reg #(.ADDR(1),.DEFAULT(0))
-   wb_reg_ucast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), 
.dat_i(wb_dat_i), .dat_o(ucast_addr[47:32]) );
+   wb_reg_ucast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), 
.wr_acc(wr_acc),
+                  .dat_i(wb_dat_i), .dat_o(ucast_addr[47:32]) );
    wb_reg #(.ADDR(2),.DEFAULT(0))
-   wb_reg_ucast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), 
.dat_i(wb_dat_i), .dat_o(ucast_addr[31:0]) );
+   wb_reg_ucast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), 
.wr_acc(wr_acc),
+                  .dat_i(wb_dat_i), .dat_o(ucast_addr[31:0]) );
    wb_reg #(.ADDR(3),.DEFAULT(0))
-   wb_reg_mcast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), 
.dat_i(wb_dat_i), .dat_o(mcast_addr[47:32]) );
+   wb_reg_mcast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), 
.wr_acc(wr_acc),
+                  .dat_i(wb_dat_i), .dat_o(mcast_addr[47:32]) );
    wb_reg #(.ADDR(4),.DEFAULT(0))
-   wb_reg_mcast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), 
.dat_i(wb_dat_i), .dat_o(mcast_addr[31:0]) );
+   wb_reg_mcast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), 
.wr_acc(wr_acc),
+                  .dat_i(wb_dat_i), .dat_o(mcast_addr[31:0]) );
 
    //MII to CPU 
    wire [7:0] Divider;            // Divider for the host clock

Modified: gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v
===================================================================
--- gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v       
2009-04-04 06:20:57 UTC (rev 10768)
+++ gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_wrapper.v       
2009-04-04 08:34:31 UTC (rev 10769)
@@ -31,8 +31,8 @@
    wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_en;
 
    wire rst_rxclk, rst_txclk;
-   reset_sync reset_sync_tx 
(.clk(tx_clk),.reset_in(reset),.reset_out(rst_txclk));
-   reset_sync reset_sync_rx 
(.clk(rx_clk),.reset_in(reset),.reset_out(rst_rxclk));
+   reset_sync reset_sync_tx 
(.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset));
+   reset_sync reset_sync_rx 
(.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset));
 
    simple_gemac simple_gemac
      (.clk125(clk125),  .reset(reset),

Added: gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_wrapper_tb.v
===================================================================
--- gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_wrapper_tb.v            
                (rev 0)
+++ gnuradio/trunk/usrp2/fpga/simple_gemac/simple_gemac_wrapper_tb.v    
2009-04-04 08:34:31 UTC (rev 10769)
@@ -0,0 +1,219 @@
+
+
+module simple_gemac_wrapper_tb;
+`include "eth_tasks.v"
+     
+   reg clk     = 0;
+   reg reset   = 1;
+
+   initial #1000 reset = 0;
+   always #50 clk = ~clk;
+
+   reg wb_clk  = 0;
+   wire wb_rst         = reset;
+   always #173 wb_clk = ~wb_clk;
+       
+   wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
+   wire [7:0] GMII_RXD, GMII_TXD;
+
+   wire rx_valid, rx_error, rx_ack;
+   wire tx_ack, tx_valid, tx_error;
+   
+   wire [7:0] rx_data, tx_data;
+   
+   reg [15:0] pause_time;
+   reg pause_req      = 0;
+
+   wire GMII_RX_CLK   = GMII_GTX_CLK;
+
+   reg [7:0] FORCE_DAT_ERR = 0;
+   reg FORCE_ERR = 0;
+   
+   // Loopback
+   assign GMII_RX_DV  = GMII_TX_EN;
+   assign GMII_RX_ER  = GMII_TX_ER | FORCE_ERR;
+   assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;
+
+
+   wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+   wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2;
+   reg rx_ll_dst_rdy2 = 1;
+   wire [7:0] rx_ll_data, rx_ll_data2;
+   wire rx_ll_error, rx_ll_error2;
+
+   wire [31:0] wb_dat_o;
+   reg [31:0]  wb_dat_i;
+   reg [7:0]   wb_adr;
+   reg                wb_stb=0, wb_cyc=0, wb_we=0;
+   wire        wb_ack;
+   
+   simple_gemac_wrapper simple_gemac_wrapper
+     (.clk125(clk),  .reset(reset),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .pause_req(pause_req), .pause_time(pause_time),
+      .rx_clk(rx_clk), .rx_ll_data(rx_ll_data), .rx_ll_sof(rx_ll_sof),
+      .rx_ll_eof(rx_ll_eof), .rx_ll_src_rdy(rx_ll_src_rdy), 
.rx_ll_dst_rdy(rx_ll_dst_rdy),
+      .tx_clk(tx_clk), .tx_ll_data(tx_ll_data), .tx_ll_sof(tx_ll_sof),
+      .tx_ll_eof(tx_ll_eof), .tx_ll_src_rdy(tx_ll_src_rdy), 
.tx_ll_dst_rdy(tx_ll_dst_rdy),
+      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), 
.wb_ack(wb_ack),
+      .wb_we(wb_we), .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+      .mdio(mdio), .mdc(mdc) );
+
+   ll8_shortfifo rx_sfifo
+     (.clk(clk), .reset(reset), .clear(0),
+      .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
+      .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), 
.dst_rdy_o(rx_ll_dst_rdy),
+      .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
+      .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), 
.dst_rdy_i(rx_ll_dst_rdy2));
+
+   wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
+   reg tx_ll_sof2=0, tx_ll_eof2=0;
+   reg tx_ll_src_rdy2 = 0;
+   wire tx_ll_dst_rdy2;
+   wire [7:0] tx_ll_data;
+   reg [7:0] tx_ll_data2 = 0;
+   wire tx_ll_error;
+   wire tx_ll_error2 = 0;
+
+   ll8_shortfifo tx_sfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
+      .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), 
.dst_rdy_o(tx_ll_dst_rdy2),
+      .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
+      .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), 
.dst_rdy_i(tx_ll_dst_rdy));
+   
+   initial $dumpfile("simple_gemac_wrapper_tb.vcd");
+   initial $dumpvars(0,simple_gemac_wrapper_tb);
+
+   integer i; 
+   reg [7:0] pkt_rom[0:65535];
+   reg [1023:0] ROMFile;
+   
+   initial
+     for (i=0;i<65536;i=i+1)
+       pkt_rom[i] <= 8'h0;
+
+   initial
+     begin
+       @(negedge reset);
+       repeat (10)
+         @(posedge clk);
+       WishboneWR(0,6'b111001);
+       WishboneWR(4,16'hF1F2);
+       WishboneWR(8,32'hF3F4_F5F6);
+       WishboneWR(12,16'h0000);
+       WishboneWR(16,32'h0000_0000);
+       
+       @(posedge clk);
+       SendFlowCtrl(16'h0007);  // Send flow control
+       @(posedge clk);
+       #30000;
+       @(posedge clk);
+       SendFlowCtrl(16'h0009);  // Increas flow control before it expires
+       #10000;
+       @(posedge clk);
+       SendFlowCtrl(16'h0000);  // Cancel flow control before it expires
+       @(posedge clk); 
+
+       SendPacket_to_ll8(8'hAA,10);    // This packet gets dropped by the 
filters
+       repeat (10)
+         @(posedge clk);
+
+       SendPacketFromFile_ll8(60,0,0);  // The rest are valid packets
+       repeat (10)
+         @(posedge clk);
+
+       SendPacketFromFile_ll8(61,0,0);
+       repeat (10)
+         @(posedge clk);
+       SendPacketFromFile_ll8(62,0,0);
+       repeat (10)
+         @(posedge clk);
+       SendPacketFromFile_ll8(63,0,0);
+       repeat (1)
+         @(posedge clk);
+       SendPacketFromFile_ll8(64,0,0);
+       repeat (10)
+         @(posedge clk);
+       SendPacketFromFile_ll8(59,0,0);
+       repeat (1)
+         @(posedge clk);
+       SendPacketFromFile_ll8(58,0,0);
+       repeat (1)
+         @(posedge clk);
+       SendPacketFromFile_ll8(100,0,0);
+       repeat (1)
+         @(posedge clk);
+       SendPacketFromFile_ll8(200,150,30);  // waiting 14 empties the fifo, 15 
underruns
+       repeat (1)
+         @(posedge clk);
+       SendPacketFromFile_ll8(100,0,30);
+       #10000 $finish;
+     end
+
+   // Force a CRC error
+    initial
+     begin
+       #90000;
+       @(posedge clk);
+       FORCE_DAT_ERR <= 8'h10;
+       @(posedge clk);
+       FORCE_DAT_ERR <= 8'h00;
+     end
+
+   // Force an RX_ER error (i.e. link loss)
+   initial
+     begin
+       #116000;
+       @(posedge clk);
+       FORCE_ERR <= 1;
+       @(posedge clk);
+       FORCE_ERR <= 0;
+     end
+
+   // Cause receive fifo to fill, causing an RX overrun
+   initial
+     begin
+       #126000;
+       @(posedge clk);
+       rx_ll_dst_rdy2 <= 0;
+       repeat (30)          // Repeat of 14 fills the shortfifo, but works.  
15 overflows
+         @(posedge clk);
+       rx_ll_dst_rdy2 <= 1;
+     end
+   
+   // Tests: Send and recv flow control, send and receive good packets, RX CRC 
err, RX_ER, RX overrun, TX underrun
+   // Still need to test: CRC errors on Pause Frames, MDIO, wishbone
+
+   task WishboneWR;
+      input [7:0] adr;
+      input [31:0] value;
+      begin
+        wb_adr   <= adr;
+        wb_dat_i <= value;
+        wb_stb   <= 1;
+        wb_cyc   <= 1;
+        wb_we    <= 1;
+        while (~wb_ack)
+          @(posedge wb_clk);
+        @(posedge wb_clk);
+        wb_stb <= 0;
+        wb_cyc <= 0;
+        wb_we  <= 0;
+      end
+   endtask // WishboneWR
+   
+   always @(posedge clk)
+     if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
+       begin
+         if(rx_ll_sof2 & ~rx_ll_eof2)
+           $display("RX-PKT-START %d",$time);
+         $display("RX-PKT SOF %d EOF %d ERR%d DAT 
%x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
+         if(rx_ll_eof2 & ~rx_ll_sof2)
+           $display("RX-PKT-END %d",$time);
+       end
+   
+endmodule // simple_gemac_wrapper_tb