[Commit-gnuradio] r10695 - usrp-hw/trunk/sym/xilinx

[matt]

Author: matt
Date: 2009-03-26 18:22:52 -0600 (Thu, 26 Mar 2009)
New Revision: 10695

Modified:
   usrp-hw/trunk/sym/xilinx/xilinxgen1136-small
Log:
splits all the power stuff into separate symbols


Modified: usrp-hw/trunk/sym/xilinx/xilinxgen1136-small
===================================================================
--- usrp-hw/trunk/sym/xilinx/xilinxgen1136-small        2009-03-27 00:18:18 UTC 
(rev 10694)
+++ usrp-hw/trunk/sym/xilinx/xilinxgen1136-small        2009-03-27 00:22:52 UTC 
(rev 10695)
@@ -39,8 +39,14 @@
 [pins]
 '''
 
-powerfile = open ('xc5v-ff1136small-PWR.src', 'w')
-powerfile.write(boilerplate % ("PWR",))
+vccintfile = open ('xc5v-ff1136small-VCCINT.src', 'w')
+vccintfile.write(boilerplate % ("VCCINT",))
+vccauxfile = open ('xc5v-ff1136small-VCCAUX.src', 'w')
+vccauxfile.write(boilerplate % ("VCCAUX",))
+gndfile = open ('xc5v-ff1136small-GND.src', 'w')
+gndfile.write(boilerplate % ("GND",))
+ncfile = open ('xc5v-ff1136small-NC.src', 'w')
+ncfile.write(boilerplate % ("NC",))
 otherfile = open ('xc5v-ff1136small-OTHER.src', 'w')
 otherfile.write(boilerplate % ("OTHER",))
 
@@ -54,6 +60,7 @@
 dummy = pinfile.readline()
 lines = pinfile.readlines()
 
+alt_side_nc = alt_side_gnd = alt_side_vccint = alt_side_vccaux = 'l'
 for line in lines:
     elements = line.strip().split('\t')
 
@@ -76,9 +83,23 @@
                     writepin(otherfile,elements[0],elements[2],'line','io','r')
                     
             elif elements[2] == 'GND':
-                writepin(powerfile,elements[0],elements[2],'line','pwr','r')
-            elif elements[2] == 'VCCINT' or elements[2] == 'VCCAUX':
-                writepin(powerfile,elements[0],elements[2],'line','pwr','l')
+                
writepin(gndfile,elements[0],elements[2],'line','pwr',alt_side_gnd)
+                if alt_side_gnd == 'l':
+                    alt_side_gnd = 'r'
+                else:
+                    alt_side_gnd = 'l'
+            elif elements[2] == 'VCCINT':
+                
writepin(vccintfile,elements[0],elements[2],'line','pwr',alt_side_vccint)
+                if alt_side_vccint == 'l':
+                    alt_side_vccint = 'r'
+                else:
+                    alt_side_vccint = 'l'
+            elif elements[2] == 'VCCAUX':
+                
writepin(vccauxfile,elements[0],elements[2],'line','pwr',alt_side_vccaux)
+                if alt_side_vccaux == 'l':
+                    alt_side_vccaux = 'r'
+                else:
+                    alt_side_vccaux = 'l'
             else:
                 print elements
 
@@ -93,60 +114,12 @@
                 writepin(iofiles[bank],elements[0],elements[2],'line','io','l')
     else:
         if len(elements)==2:
-            writepin(powerfile,elements[0],elements[1],'line','pas','b')
+            writepin(ncfile,elements[0],elements[1],'line','pas',alt_side_nc)
+            if alt_side_nc == 'l':
+                alt_side_nc = 'r'
+            else:
+                alt_side_nc = 'l'
         else:
             print "Ignored line:", elements
             
 print "Total Pins: ", pincount
-"""
-    elif(pintype == 'VCCAUX'):
-        writepin(powerfile,elements[0],elements[1],'line','pwr','l')
-    elif(pintype == 'VCCO'):
-        
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','pwr','b')
-    elif(pintype == 'VCCINT'):
-        writepin(powerfile,elements[0],elements[1],'line','pwr','l')
-
-    elif(pintype == 'JTAG'):
-        writepin(jtagfile,elements[0],elements[1],'line','io','l')
-
-    elif(pintype == 'CONFIG'):
-        writepin(configfile,elements[0],elements[1],'line','io','l')
-
-    elif(pintype == 'PWRMGMT'):
-        writepin(configfile,elements[0],elements[1],'line','io','l')
-
-    elif(pintype == 'DUAL'):
-        if(int(elements[2]) == 1):   # All these are for BPI mode, so just put 
in bank 1
-            
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','io','l')
-        elif(int(elements[2]) == 2):
-            writepin(configfile,elements[0],elements[1],'line','io','r')
-        else:
-            writepin(configfile,elements[0],elements[1],'line','io','l')
-            
-    elif(pintype == 'GCLK'):
-        if(int(elements[2]) == 0):
-            writepin(topclockfile,elements[0],elements[1],'clk','clk','l')
-        else:
-            writepin(botclockfile,elements[0],elements[1],'clk','clk','l')
-            
-    elif(pintype == 'LHCLK'):
-        writepin(lhclockfile,elements[0],elements[1],'clk','clk','l')
-
-    elif(pintype == 'RHCLK'):
-        writepin(rhclockfile,elements[0],elements[1],'clk','clk','l')
-
-    elif(pintype == 'VREF'):
-        
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','io','r')
-
-    elif(pintype == 'I/O'):
-        
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','io','l')
-
-    elif(pintype == 'INPUT'):
-        
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','in','r')
-
-    elif(pintype == 'DCI'):
-        writepin(iofiles[int(elements[12])],elements[3],"%s/DCI" % 
(elements[6],),'line','io','l')
-
-    else:
-        print elements
-"""