[Commit-gnuradio] r10483 - usrp-hw/trunk/sym/xilinx

[jblum]

Author: jblum
Date: 2009-02-23 12:39:07 -0700 (Mon, 23 Feb 2009)
New Revision: 10483

Added:
   usrp-hw/trunk/sym/xilinx/XC3S1400AFT256.csv
   usrp-hw/trunk/sym/xilinx/xilinxgen256
Modified:
   usrp-hw/trunk/sym/xilinx/
   usrp-hw/trunk/sym/xilinx/Makefile
Log:
Updated makefile, added generation for XC3S1400AFT256


Property changes on: usrp-hw/trunk/sym/xilinx
___________________________________________________________________
Name: svn:ignore
   - *.log

   + *.sym
*.src
*.log


Modified: usrp-hw/trunk/sym/xilinx/Makefile
===================================================================
--- usrp-hw/trunk/sym/xilinx/Makefile   2009-02-23 17:40:39 UTC (rev 10482)
+++ usrp-hw/trunk/sym/xilinx/Makefile   2009-02-23 19:39:07 UTC (rev 10483)
@@ -2,73 +2,47 @@
 
 TRAGESYM=tragesym
 
-SOURCES= \
-       xc5v-ff1136big-PWR.sym \
-       xc5v-ff1136big-OTHER.sym \
-       xc5v-ff1136big-BANK0.sym \
-       xc5v-ff1136big-BANK1.sym \
-       xc5v-ff1136big-BANK2.sym \
-       xc5v-ff1136big-BANK3.sym \
-       xc5v-ff1136big-BANK4.sym \
-       xc5v-ff1136big-BANK5.sym \
-       xc5v-ff1136big-BANK6.sym \
-       xc5v-ff1136big-BANK11.sym \
-       xc5v-ff1136big-BANK12.sym \
-       xc5v-ff1136big-BANK13.sym \
-       xc5v-ff1136big-BANK15.sym \
-       xc5v-ff1136big-BANK17.sym \
-       xc5v-ff1136big-BANK18.sym \
-       xc5v-ff1136big-BANK19.sym \
-       xc5v-ff1136big-BANK20.sym \
-       xc5v-ff1136big-BANK21.sym \
-       xc5v-ff1136big-BANK22.sym \
-       xc5v-ff1136big-BANK23.sym \
-       xc5v-ff1136big-BANK25.sym \
-       xc5v-ff1136big-BANK112.sym \
-       xc5v-ff1136big-BANK114.sym \
-       xc5v-ff1136big-BANK116.sym \
-       xc5v-ff1136big-BANK118.sym \
-       xc5v-ff1136big-BANK120.sym \
-       xc5v-ff1136big-BANK122.sym \
-       xc5v-ff1136big-BANK124.sym \
-       xc5v-ff1136big-BANK126.sym \
-       xc5v-ff1136small-PWR.sym \
-       xc5v-ff1136small-OTHER.sym \
-       xc5v-ff1136small-BANK0.sym \
-       xc5v-ff1136small-BANK1.sym \
-       xc5v-ff1136small-BANK2.sym \
-       xc5v-ff1136small-BANK3.sym \
-       xc5v-ff1136small-BANK4.sym \
-       xc5v-ff1136small-BANK5.sym \
-       xc5v-ff1136small-BANK6.sym \
-       xc5v-ff1136small-BANK11.sym \
-       xc5v-ff1136small-BANK12.sym \
-       xc5v-ff1136small-BANK13.sym \
-       xc5v-ff1136small-BANK15.sym \
-       xc5v-ff1136small-BANK17.sym \
-       xc5v-ff1136small-BANK18.sym \
-       xc5v-ff1136small-BANK19.sym \
-       xc5v-ff1136small-BANK20.sym \
-       xc5v-ff1136small-BANK21.sym \
-       xc5v-ff1136small-BANK22.sym \
-       xc5v-ff1136small-BANK23.sym \
-       xc5v-ff1136small-BANK25.sym \
-       xc5v-ff1136small-BANK112.sym \
-       xc5v-ff1136small-BANK114.sym \
-       xc5v-ff1136small-BANK116.sym \
-       xc5v-ff1136small-BANK118.sym \
-       xc5v-ff1136small-BANK120.sym \
-       xc5v-ff1136small-BANK122.sym \
-       xc5v-ff1136small-BANK124.sym \
-       xc5v-ff1136small-BANK126.sym
+SRCFILES = \
+xc3s1400aft256-BOTCLK.src   xc3sd3400afg676-CFG.src     xc3sXX00fg456-CLK.src  
     xc5v-ff1136big-BANK15.src     xc5v-ff1136small-BANK120.src \
+xc3s1400aft256-CFG.src      xc3sd3400afg676-IO0.src     xc3sXX00fg456-IO0.src  
     xc5v-ff1136big-BANK17.src     xc5v-ff1136small-BANK122.src \
+xc3s1400aft256-IO0.src      xc3sd3400afg676-IO1.src     xc3sXX00fg456-IO1.src  
     xc5v-ff1136big-BANK18.src     xc5v-ff1136small-BANK12.src \
+xc3s1400aft256-IO1.src      xc3sd3400afg676-IO2.src     xc3sXX00fg456-IO2.src  
     xc5v-ff1136big-BANK19.src     xc5v-ff1136small-BANK13.src \
+xc3s1400aft256-IO2.src      xc3sd3400afg676-IO3.src     xc3sXX00fg456-IO3.src  
     xc5v-ff1136big-BANK1.src      xc5v-ff1136small-BANK15.src \
+xc3s1400aft256-IO3.src      xc3sd3400afg676-JTAG.src    xc3sXX00fg456-IO4.src  
     xc5v-ff1136big-BANK20.src     xc5v-ff1136small-BANK17.src \
+xc3s1400aft256-JTAG.src     xc3sd3400afg676-LHCLK.src   xc3sXX00fg456-IO5.src  
     xc5v-ff1136big-BANK21.src     xc5v-ff1136small-BANK18.src \
+xc3s1400aft256-LHCLK.src    xc3sd3400afg676-PWR.src     xc3sXX00fg456-IO6.src  
     xc5v-ff1136big-BANK22.src     xc5v-ff1136small-BANK19.src \
+xc3s1400aft256-PWR.src      xc3sd3400afg676-RHCLK.src   xc3sXX00fg456-IO7.src  
     xc5v-ff1136big-BANK23.src     xc5v-ff1136small-BANK1.src \
+xc3s1400aft256-RHCLK.src    xc3sd3400afg676-TOPCLK.src  xc3sXX00fg456-JTAG.src 
     xc5v-ff1136big-BANK25.src     xc5v-ff1136small-BANK20.src \
+xc3s1400aft256-TOPCLK.src   xc3sXX00fg320-CFG.src       xc3sXX00fg456-PWR.src  
     xc5v-ff1136big-BANK2.src      xc5v-ff1136small-BANK21.src \
+xc3sd1800acs484-BOTCLK.src  xc3sXX00fg320-CLK.src       
xc5v-ff1136big-BANK0.src    xc5v-ff1136big-BANK3.src      
xc5v-ff1136small-BANK22.src \
+xc3sd1800acs484-CFG.src     xc3sXX00fg320-IO0.src       
xc5v-ff1136big-BANK112.src  xc5v-ff1136big-BANK4.src      
xc5v-ff1136small-BANK23.src \
+xc3sd1800acs484-IO0.src     xc3sXX00fg320-IO1.src       
xc5v-ff1136big-BANK114.src  xc5v-ff1136big-BANK5.src      
xc5v-ff1136small-BANK25.src \
+xc3sd1800acs484-IO1.src     xc3sXX00fg320-IO2.src       
xc5v-ff1136big-BANK116.src  xc5v-ff1136big-BANK6.src      
xc5v-ff1136small-BANK2.src \
+xc3sd1800acs484-IO2.src     xc3sXX00fg320-IO3.src       
xc5v-ff1136big-BANK118.src  xc5v-ff1136big-OTHER.src      
xc5v-ff1136small-BANK3.src \
+xc3sd1800acs484-IO3.src     xc3sXX00fg320-IO4.src       
xc5v-ff1136big-BANK11.src   xc5v-ff1136big-PWR.src        
xc5v-ff1136small-BANK4.src \
+xc3sd1800acs484-JTAG.src    xc3sXX00fg320-IO5.src       
xc5v-ff1136big-BANK120.src  xc5v-ff1136small-BANK0.src    
xc5v-ff1136small-BANK5.src \
+xc3sd1800acs484-LHCLK.src   xc3sXX00fg320-IO6.src       
xc5v-ff1136big-BANK122.src  xc5v-ff1136small-BANK112.src  
xc5v-ff1136small-BANK6.src \
+xc3sd1800acs484-PWR.src     xc3sXX00fg320-IO7.src       
xc5v-ff1136big-BANK124.src  xc5v-ff1136small-BANK114.src  
xc5v-ff1136small-OTHER.src \
+xc3sd1800acs484-RHCLK.src   xc3sXX00fg320-JTAG.src      
xc5v-ff1136big-BANK126.src  xc5v-ff1136small-BANK116.src  
xc5v-ff1136small-PWR.src \
+xc3sd1800acs484-TOPCLK.src  xc3sXX00fg320-PWR.src       
xc5v-ff1136big-BANK12.src   xc5v-ff1136small-BANK118.src \
+xc3sd3400afg676-BOTCLK.src  xc3sXX00fg456-CFG.src       
xc5v-ff1136big-BANK13.src   xc5v-ff1136small-BANK11.src
 
+SYMFILES=$(SRCFILES:.src=.sym)
 
+all: $(SRCFILES) $(SYMFILES)
 
-all : $(SOURCES)
+$(SRCFILES):
+       ./xilinxgen1136-big
+       ./xilinxgen320
+       ./xilinxgen484
+       ./xilinxgen1136-small
+       ./xilinxgen456
+       ./xilinxgen676
+       ./xilinxgen256
 
-clean : 
-       @rm -f *.sym
+clean:
+       $(RM) *.src *.sym
 
-%.sym : %.src
+%.sym: %.src
        $(TRAGESYM) $< $@
 

Added: usrp-hw/trunk/sym/xilinx/XC3S1400AFT256.csv
===================================================================
--- usrp-hw/trunk/sym/xilinx/XC3S1400AFT256.csv                         (rev 0)
+++ usrp-hw/trunk/sym/xilinx/XC3S1400AFT256.csv 2009-02-23 19:39:07 UTC (rev 
10483)
@@ -0,0 +1,257 @@
+PIN,BANK,XC3S1400AFT256,TYPE,DIFF_PAIR,ROW,COL
+A1,GND,GND,GND,,A,1
+A2,VCCAUX,PROG_B,CONFIG,,A,2
+A3,0,IO_L19P_0,I/O,TRUE,A,3
+A4,0,IO_L18P_0,I/O,TRUE,A,4
+A5,0,IO_L17P_0,I/O,TRUE,A,5
+A6,0,IO_L15P_0,I/O,TRUE,A,6
+A7,0,IO_L13P_0,I/O,TRUE,A,7
+A8,0,IO_L12P_0/GCLK10,GCLK,TRUE,A,8
+A9,0,IO_L10N_0/GCLK7,GCLK,TRUE,A,9
+A10,0,IO_L08N_0,I/O,TRUE,A,10
+A11,0,IO_L07N_0,I/O,TRUE,A,11
+A12,0,IO_L05N_0,I/O,TRUE,A,12
+A13,0,IO_L04N_0,I/O,TRUE,A,13
+A14,0,IO_L04P_0,I/O,TRUE,A,14
+A15,0,TCK,JTAG,,A,15
+A16,GND,GND,GND,,A,16
+B1,3,TDI,JTAG,,B,1
+B2,3,TMS,JTAG,,B,2
+B3,0,IO_L19N_0,I/O,TRUE,B,3
+B4,0,IO_L18N_0,I/O,TRUE,B,4
+B5,0,VCCO_0,VCCO,,B,5
+B6,0,IO_L15N_0,I/O,TRUE,B,6
+B7,GND,GND,GND,,B,7
+B8,0,IO_L12N_0/GCLK11,GCLK,TRUE,B,8
+B9,0,VCCO_0,VCCO,,B,9
+B10,0,IO_L08P_0,I/O,TRUE,B,10
+B11,GND,GND,GND,,B,11
+B12,0,IO_L05P_0,I/O,TRUE,B,12
+B13,0,VCCO_0,VCCO,,B,13
+B14,0,IO_L02N_0,I/O,TRUE,B,14
+B15,0,IO_L02P_0/VREF_0,VREF,TRUE,B,15
+B16,1,TDO,JTAG,,B,16
+C1,3,IO_L01N_3,I/O,TRUE,C,1
+C2,3,IO_L01P_3,I/O,TRUE,C,2
+C3,GND,GND,GND,,C,3
+C4,0,IO_L20P_0/VREF_0,VREF,TRUE,C,4
+C5,0,IO_L17N_0,I/O,TRUE,C,5
+C6,0,IO_L16N_0,I/O,TRUE,C,6
+C7,0,IO_L13N_0,I/O,TRUE,C,7
+C8,0,IO_L11P_0/GCLK8,GCLK,TRUE,C,8
+C9,0,IO_L10P_0/GCLK6,GCLK,TRUE,C,9
+C10,0,IO_L09P_0/GCLK4,GCLK,TRUE,C,10
+C11,0,IO_L07P_0,I/O,TRUE,C,11
+C12,0,IO_L03P_0,I/O,TRUE,C,12
+C13,0,IO_L01N_0,I/O,TRUE,C,13
+C14,GND,GND,GND,,C,14
+C15,1,IO_L24N_1/A25,DUAL,TRUE,C,15
+C16,1,IO_L24P_1/A24,DUAL,TRUE,C,16
+D1,3,IO_L03P_3,I/O,TRUE,D,1
+D2,3,VCCO_3,VCCO,,D,2
+D3,3,IO_L02N_3,I/O,TRUE,D,3
+D4,3,IO_L02P_3,I/O,TRUE,D,4
+D5,0,IO_L20N_0/PUDC_B,DUAL,TRUE,D,5
+D6,VCCAUX,VCCAUX,VCCAUX,,D,6
+D7,0,IO_L16P_0,I/O,TRUE,D,7
+D8,0,IO_L11N_0/GCLK9,GCLK,TRUE,D,8
+D9,0,IO_L09N_0/GCLK5,GCLK,TRUE,D,9
+D10,0,IO_L06N_0/VREF_0,VREF,TRUE,D,10
+D11,0,IO_L06P_0,I/O,TRUE,D,11
+D12,0,IO_L03N_0,I/O,TRUE,D,12
+D13,0,IO_L01P_0,I/O,TRUE,D,13
+D14,1,IO_L23N_1/A23,DUAL,TRUE,D,14
+D15,1,IO_L22N_1/A21,DUAL,TRUE,D,15
+D16,1,IO_L22P_1/A20,DUAL,TRUE,D,16
+E1,3,IO_L03N_3,I/O,TRUE,E,1
+E2,3,IO_L05N_3,I/O,TRUE,E,2
+E3,3,IO_L05P_3,I/O,TRUE,E,3
+E4,3,IO_L04P_3,I/O,TRUE,E,4
+E5,GND,GND,GND,,E,5
+E6,0,IP_0,INPUT,,E,6
+E7,0,IO_L14N_0/VREF_0,VREF,TRUE,E,7
+E8,0,VCCO_0,VCCO,,E,8
+E9,0,IO_L14P_0,I/O,TRUE,E,9
+E10,GND,GND,GND,,E,10
+E11,VCCAUX,VCCAUX,VCCAUX,,E,11
+E12,GND,GND,GND,,E,12
+E13,1,IO_L23P_1/A22,DUAL,TRUE,E,13
+E14,1,IO_L20P_1/A18,DUAL,TRUE,E,14
+E15,1,VCCO_1,VCCO,,E,15
+E16,1,IO_L18P_1/A14,DUAL,TRUE,E,16
+F1,3,IO_L08P_3,I/O,TRUE,F,1
+F2,GND,GND,GND,,F,2
+F3,3,IO_L07P_3,I/O,TRUE,F,3
+F4,3,IO_L04N_3,I/O,TRUE,F,4
+F5,VCCAUX,VCCAUX,VCCAUX,,F,5
+F6,GND,GND,GND,,F,6
+F7,GND,GND,GND,,F,7
+F8,GND,GND,GND,,F,8
+F9,GND,GND,GND,,F,9
+F10,VCCINT,VCCINT,VCCINT,,F,10
+F11,GND,GND,GND,,F,11
+F12,VCCAUX,VCCAUX,VCCAUX,,F,12
+F13,1,IO_L20N_1/A19,DUAL,TRUE,F,13
+F14,1,IO_L19N_1/A17,DUAL,TRUE,F,14
+F15,1,IO_L18N_1/A15,DUAL,TRUE,F,15
+F16,1,IO_L16N_1/A11,DUAL,TRUE,F,16
+G1,3,IO_L08N_3/VREF_3,VREF,TRUE,G,1
+G2,3,IO_L11P_3/LHCLK0,LHCLK,TRUE,G,2
+G3,3,IO_L07N_3,I/O,TRUE,G,3
+G4,3,IP_3/VREF_3,VREF,,G,4
+G5,GND,GND,GND,,G,5
+G6,GND,GND,GND,,G,6
+G7,VCCINT,VCCINT,VCCINT,,G,7
+G8,GND,GND,GND,,G,8
+G9,VCCINT,VCCINT,VCCINT,,G,9
+G10,GND,GND,GND,,G,10
+G11,VCCINT,VCCINT,VCCINT,,G,11
+G12,GND,GND,GND,,G,12
+G13,1,IO_L19P_1/A16,DUAL,TRUE,G,13
+G14,1,IO_L17N_1/A13,DUAL,TRUE,G,14
+G15,GND,GND,GND,,G,15
+G16,1,IO_L16P_1/A10,DUAL,TRUE,G,16
+H1,3,IO_L11N_3/LHCLK1,LHCLK,TRUE,H,1
+H2,3,VCCO_3,VCCO,,H,2
+H3,3,IO_L12P_3/LHCLK2,LHCLK,TRUE,H,3
+H4,VCCAUX,VCCAUX,VCCAUX,,H,4
+H5,GND,GND,GND,,H,5
+H6,VCCINT,VCCINT,VCCINT,,H,6
+H7,GND,GND,GND,,H,7
+H8,VCCINT,VCCINT,VCCINT,,H,8
+H9,GND,GND,GND,,H,9
+H10,VCCINT,VCCINT,VCCINT,,H,10
+H11,GND,GND,GND,,H,11
+H12,1,IP_1/VREF_1,VREF,,H,12
+H13,1,IO_L17P_1/A12,DUAL,TRUE,H,13
+H14,VCCAUX,VCCAUX,VCCAUX,,H,14
+H15,1,IO_L15P_1/IRDY1/RHCLK6,RHCLK,TRUE,H,15
+H16,1,IO_L15N_1/RHCLK7,RHCLK,TRUE,H,16
+J1,3,IO_L14N_3/LHCLK5,LHCLK,TRUE,J,1
+J2,3,IO_L14P_3/LHCLK4,LHCLK,TRUE,J,2
+J3,3,IO_L12N_3/IRDY2/LHCLK3,LHCLK,TRUE,J,3
+J4,3,IP_3,INPUT,,J,4
+J5,3,IP_3/VREF_3,VREF,,J,5
+J6,GND,GND,GND,,J,6
+J7,VCCINT,VCCINT,VCCINT,,J,7
+J8,GND,GND,GND,,J,8
+J9,VCCINT,VCCINT,VCCINT,,J,9
+J10,GND,GND,GND,,J,10
+J11,VCCINT,VCCINT,VCCINT,,J,11
+J12,1,IO_L10P_1/A8,DUAL,TRUE,J,12
+J13,1,IO_L10N_1/A9,DUAL,TRUE,J,13
+J14,1,IP_1/VREF_1,VREF,,J,14
+J15,1,VCCO_1,VCCO,,J,15
+J16,1,IO_L12N_1/TRDY1/RHCLK3,RHCLK,TRUE,J,16
+K1,3,IO_L15N_3/LHCLK7,LHCLK,TRUE,K,1
+K2,GND,GND,GND,,K,2
+K3,3,IO_L15P_3/TRDY2/LHCLK6,LHCLK,TRUE,K,3
+K4,3,IO_L18P_3,I/O,TRUE,K,4
+K5,GND,GND,GND,,K,5
+K6,VCCINT,VCCINT,VCCINT,,K,6
+K7,GND,GND,GND,,K,7
+K8,VCCINT,VCCINT,VCCINT,,K,8
+K9,GND,GND,GND,,K,9
+K10,VCCINT,VCCINT,VCCINT,,K,10
+K11,GND,GND,GND,,K,11
+K12,GND,GND,GND,,K,12
+K13,1,IO_L06N_1/A3,DUAL,TRUE,K,13
+K14,1,IO_L11N_1/RHCLK1,RHCLK,TRUE,K,14
+K15,1,IO_L11P_1/RHCLK0,RHCLK,TRUE,K,15
+K16,1,IO_L12P_1/RHCLK2,RHCLK,TRUE,K,16
+L1,3,IO_L16P_3/VREF_3,VREF,TRUE,L,1
+L2,3,IO_L16N_3,I/O,TRUE,L,2
+L3,3,IO_L18N_3,I/O,TRUE,L,3
+L4,3,IO_L19N_3,I/O,TRUE,L,4
+L5,VCCAUX,VCCAUX,VCCAUX,,L,5
+L6,GND,GND,GND,,L,6
+L7,VCCINT,VCCINT,VCCINT,,L,7
+L8,GND,GND,GND,,L,8
+L9,VCCINT,VCCINT,VCCINT,,L,9
+L10,GND,GND,GND,,L,10
+L11,GND,GND,GND,,L,11
+L12,VCCAUX,VCCAUX,VCCAUX,,L,12
+L13,1,IO_L06P_1/A2,DUAL,TRUE,L,13
+L14,1,IO_L08P_1/A6,DUAL,TRUE,L,14
+L15,GND,GND,GND,,L,15
+L16,1,IO_L08N_1/A7,DUAL,TRUE,L,16
+M1,3,IO_L20P_3,I/O,TRUE,M,1
+M2,3,VCCO_3,VCCO,,M,2
+M3,3,IO_L19P_3,I/O,TRUE,M,3
+M4,3,IO_L24N_3,I/O,TRUE,M,4
+M5,GND,GND,GND,,M,5
+M6,VCCAUX,VCCAUX,VCCAUX,,M,6
+M7,2,IP_2/VREF_2,VREF,,M,7
+M8,GND,GND,GND,,M,8
+M9,2,IP_2/VREF_2,VREF,,M,9
+M10,VCCAUX,VCCAUX,VCCAUX,,M,10
+M11,2,IP_2/VREF_2,VREF,,M,11
+M12,GND,GND,GND,,M,12
+M13,1,IP_1/VREF_1,VREF,,M,13
+M14,1,IP_1/VREF_1,VREF,,M,14
+M15,1,IO_L07P_1/A4,DUAL,TRUE,M,15
+M16,1,IO_L07N_1/A5,DUAL,TRUE,M,16
+N1,3,IO_L20N_3,I/O,TRUE,N,1
+N2,3,IO_L22P_3/VREF_3,VREF,TRUE,N,2
+N3,3,IO_L24P_3,I/O,TRUE,N,3
+N4,2,IO_L01P_2/M1,DUAL,TRUE,N,4
+N5,2,IP_2/VREF_2,VREF,,N,5
+N6,2,IO_L04P_2/VS1,DUAL,TRUE,N,6
+N7,GND,GND,GND,,N,7
+N8,2,IO_L08N_2/D4,DUAL,TRUE,N,8
+N9,2,IO_L11P_2/GCLK0,GCLK,TRUE,N,9
+N10,GND,GND,GND,,N,10
+N11,2,IO_L16N_2,I/O,TRUE,N,11
+N12,2,IO_L19P_2,I/O,TRUE,N,12
+N13,1,IO_L01P_1/HDC,DUAL,TRUE,N,13
+N14,1,IO_L01N_1/LDC2,DUAL,TRUE,N,14
+N15,1,VCCO_1,VCCO,,N,15
+N16,1,IO_L03N_1/A1,DUAL,TRUE,N,16
+P1,3,IO_L22N_3,I/O,TRUE,P,1
+P2,3,IO_L23N_3,I/O,TRUE,P,2
+P3,GND,GND,GND,,P,3
+P4,2,IO_L01N_2/M0,DUAL,TRUE,P,4
+P5,2,IO_L04N_2/VS0,DUAL,TRUE,P,5
+P6,2,IP_2/VREF_2,VREF,,P,6
+P7,2,IO_L08P_2/D5,DUAL,TRUE,P,7
+P8,2,IO_L10P_2/GCLK14,GCLK,TRUE,P,8
+P9,2,IO_L11N_2/GCLK1,GCLK,TRUE,P,9
+P10,2,IO_L14N_2/MOSI/CSI_B,DUAL,TRUE,P,10
+P11,2,IO_L16P_2,I/O,TRUE,P,11
+P12,2,IO_L17N_2/D3,DUAL,TRUE,P,12
+P13,2,IO_L19N_2,I/O,TRUE,P,13
+P14,GND,GND,GND,,P,14
+P15,1,IO_L02N_1/LDC0,DUAL,TRUE,P,15
+P16,1,IO_L03P_1/A0,DUAL,TRUE,P,16
+R1,3,IO_L23P_3,I/O,TRUE,R,1
+R2,2,IO_L02P_2/M2,DUAL,TRUE,R,2
+R3,2,IO_L03P_2/RDWR_B,DUAL,TRUE,R,3
+R4,2,VCCO_2,VCCO,,R,4
+R5,2,IO_L05N_2,I/O,TRUE,R,5
+R6,GND,GND,GND,,R,6
+R7,2,IO_L09P_2/GCLK12,GCLK,TRUE,R,7
+R8,2,VCCO_2,VCCO,,R,8
+R9,2,IO_L12P_2/GCLK2,GCLK,TRUE,R,9
+R10,GND,GND,GND,,R,10
+R11,2,IO_L15N_2/DOUT,DUAL,TRUE,R,11
+R12,2,VCCO_2,VCCO,,R,12
+R13,2,IO_L18N_2/D1,DUAL,TRUE,R,13
+R14,2,IO_L20N_2/CCLK,DUAL,TRUE,R,14
+R15,1,IO_L02P_1/LDC1,DUAL,TRUE,R,15
+R16,VCCAUX,SUSPEND,PWRMGT,,R,16
+T1,GND,GND,GND,,T,1
+T2,2,IO_L02N_2/CSO_B,DUAL,TRUE,T,2
+T3,2,IO_L03N_2/VS2,DUAL,TRUE,T,3
+T4,2,IO_L05P_2,I/O,TRUE,T,4
+T5,2,IO_L06P_2/D7,DUAL,TRUE,T,5
+T6,2,IO_L06N_2/D6,DUAL,TRUE,T,6
+T7,2,IO_L09N_2/GCLK13,GCLK,TRUE,T,7
+T8,2,IO_L10N_2/GCLK15,GCLK,TRUE,T,8
+T9,2,IO_L12N_2/GCLK3,GCLK,TRUE,T,9
+T10,2,IO_L14P_2,I/O,TRUE,T,10
+T11,2,IO_L15P_2/AWAKE,PWRMGT,TRUE,T,11
+T12,2,IO_L17P_2/INIT_B,DUAL,TRUE,T,12
+T13,2,IO_L18P_2/D2,DUAL,TRUE,T,13
+T14,2,IO_L20P_2/D0/DIN/MISO,DUAL,TRUE,T,14
+T15,VCCAUX,DONE,CONFIG,,T,15
+T16,GND,GND,GND,,T,16

Copied: usrp-hw/trunk/sym/xilinx/xilinxgen256 (from rev 10471, 
usrp-hw/trunk/sym/xilinx/xilinxgen484)
===================================================================
--- usrp-hw/trunk/sym/xilinx/xilinxgen256                               (rev 0)
+++ usrp-hw/trunk/sym/xilinx/xilinxgen256       2009-02-23 19:39:07 UTC (rev 
10483)
@@ -0,0 +1,125 @@
+#!/usr/bin/python
+
+import re
+matchstr = re.compile("_")
+
+def writepin(file,number,name,linetype,pintype,pos):
+    #newname = matchstr.sub("\\_",name)
+    newname = name
+    file.write("%s\t\t%s\t%s\t%s\t\t%s\n" % 
(number,pintype,linetype,pos,newname))
+
+pinfile = open ('XC3S1400AFT256.csv','r')
+
+boilerplate = '''
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3S1400AFT256-%s
+device=XC3S1400AFT256
+refdes=U?
+footprint=CS484
+description=Xilinx Spartan 3A 1400 FT256
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+'''
+
+configfile = open ('xc3s1400aft256-CFG.src', 'w')
+configfile.write(boilerplate % ("CFG",))
+
+jtagfile = open ('xc3s1400aft256-JTAG.src', 'w')
+jtagfile.write(boilerplate % ("JTAG",))
+powerfile = open ('xc3s1400aft256-PWR.src', 'w')
+powerfile.write(boilerplate % ("PWR",))
+topclockfile = open ('xc3s1400aft256-TOPCLK.src', 'w')
+topclockfile.write(boilerplate % ("TOPCLK",))
+botclockfile = open ('xc3s1400aft256-BOTCLK.src', 'w')
+botclockfile.write(boilerplate % ("BOTCLK",))
+lhclockfile = open ('xc3s1400aft256-LHCLK.src', 'w')
+lhclockfile.write(boilerplate % ("LHCLK",))
+rhclockfile = open ('xc3s1400aft256-RHCLK.src', 'w')
+rhclockfile.write(boilerplate % ("RHCLK",))
+
+iofiles = [0] * 4
+for i in range(4):
+    iofiles[i] = open ( ('xc3s1400aft256-IO%d.src' % (i,)), 'w')
+    iofiles[i].write(boilerplate % ('IO%d' % (i,),))
+    
+dummy = pinfile.readline()
+lines = pinfile.readlines()
+
+for line in lines:
+    elements = line.strip().split(',')
+
+    pintype = elements[3]
+    #nc = elements[5] == "N.C."
+
+    #if(elements[5] != elements[9]) and not nc:
+    #    print "error"
+    #    print elements
+
+    #if nc and pintype != 'I/O' and pintype != 'VREF':
+    #    print "error"
+    #    print elements
+    
+    if(pintype == 'GND'):
+        writepin(powerfile,elements[0],elements[2],'line','pwr','r')
+    elif(pintype == 'VCCAUX'):
+        writepin(powerfile,elements[0],elements[2],'line','pwr','l')
+    elif(pintype == 'VCCO'):
+        #writepin(powerfile,elements[3],elements[6],'line','pwr','l')
+        
writepin(iofiles[int(elements[1])],elements[0],elements[2],'line','pwr','b')
+    elif(pintype == 'VCCINT'):
+        writepin(powerfile,elements[0],elements[2],'line','pwr','l')
+
+    elif(pintype == 'JTAG'):
+        writepin(jtagfile,elements[0],elements[2],'line','io','l')
+
+    elif(pintype == 'CONFIG'):
+        writepin(configfile,elements[0],elements[2],'line','io','b')
+
+    elif(pintype == 'PWRMGMT'):
+        writepin(configfile,elements[0],elements[2],'line','io','b')
+
+    elif(pintype == 'DUAL'):
+        if(int(elements[1]) == 1):   # All these are for BPI mode, so just put 
in bank 1
+            
writepin(iofiles[int(elements[1])],elements[0],elements[2],'line','io','l')
+        elif(int(elements[1]) == 2):
+            writepin(configfile,elements[0],elements[2],'line','io','r')
+        else:
+            writepin(configfile,elements[0],elements[2],'line','io','l')
+            
+    elif(pintype == 'GCLK'):
+        if(int(elements[1]) == 0):
+            writepin(topclockfile,elements[0],elements[2],'clk','clk','l')
+        else:
+            writepin(botclockfile,elements[0],elements[2],'clk','clk','l')
+            
+    elif(pintype == 'LHCLK'):
+        writepin(lhclockfile,elements[0],elements[2],'clk','clk','l')
+
+    elif(pintype == 'RHCLK'):
+        writepin(rhclockfile,elements[0],elements[2],'clk','clk','l')
+
+    elif(pintype == 'VREF'):
+        
writepin(iofiles[int(elements[1])],elements[0],elements[2],'line','io','r')
+
+    elif(pintype == 'I/O'):
+        
writepin(iofiles[int(elements[1])],elements[0],elements[2],'line','io','l')
+
+    elif(pintype == 'INPUT'):
+        
writepin(iofiles[int(elements[1])],elements[0],elements[2],'line','in','r')
+
+    elif(pintype == 'DCI'):
+        writepin(iofiles[int(elements[12])],elements[3],"%s/DCI" % 
(elements[6],),'line','io','l')
+
+    else:
+        print elements


Property changes on: usrp-hw/trunk/sym/xilinx/xilinxgen256
___________________________________________________________________
Name: svn:executable
   + *
Name: svn:mergeinfo
   +