[Commit-gnuradio] r10337 - usrp-hw/trunk/sym/xilinx

[matt]

Author: matt
Date: 2009-01-29 17:47:31 -0700 (Thu, 29 Jan 2009)
New Revision: 10337

Added:
   usrp-hw/trunk/sym/xilinx/xilinxgen1136-small
Log:
480 pin version


Added: usrp-hw/trunk/sym/xilinx/xilinxgen1136-small
===================================================================
--- usrp-hw/trunk/sym/xilinx/xilinxgen1136-small                                
(rev 0)
+++ usrp-hw/trunk/sym/xilinx/xilinxgen1136-small        2009-01-30 00:47:31 UTC 
(rev 10337)
@@ -0,0 +1,152 @@
+#!/usr/bin/python
+
+pincount = 0
+
+import re
+underscore = re.compile("_")
+vcco = re.compile("VCCO")
+mgt = re.compile("MGT")
+av = re.compile("MGTAV")
+
+def writepin(file,number,name,linetype,pintype,pos):
+    #newname = underscore.sub("\\_",name)
+    newname = name
+    global pincount
+    file.write("%s\t\t%s\t%s\t%s\t\t%s\n" % 
(number,pintype,linetype,pos,newname))
+    pincount = pincount + 1
+
+pinfile = open ('ff1136_small.txt','r')
+
+boilerplate = '''
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=6000
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC5V-FF1136SMALL-%s
+device=XC5V-FF1136SMALL
+refdes=U?
+footprint=FF1136
+description=Xilinx Virtex5 1136 pin BGA
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+'''
+
+powerfile = open ('xc5v-ff1136small-PWR.src', 'w')
+powerfile.write(boilerplate % ("PWR",))
+otherfile = open ('xc5v-ff1136small-OTHER.src', 'w')
+otherfile.write(boilerplate % ("OTHER",))
+
+banks = 26
+iofiles = [0] * banks
+mgtbanks = 127
+mgtfiles = [0] * mgtbanks
+
+    
+dummy = pinfile.readline()
+dummy = pinfile.readline()
+lines = pinfile.readlines()
+
+for line in lines:
+    elements = line.strip().split('\t')
+
+    #writepin(file,number,name,linetype,pintype,pos):
+
+    if len(elements) == 3:
+        if elements[1] == 'NA':
+            if re.match(mgt,elements[2]):
+                if re.search(underscore,elements[2]):
+                    (dummy,bank) = elements[2].split('_')
+                    bank = int(bank)
+                    if(not(mgtfiles[bank])):
+                        mgtfiles[bank] = open ( ('xc5v-ff1136small-BANK%d.src' 
% (bank,)), 'w')
+                        mgtfiles[bank].write(boilerplate % ('BANK%d' % 
(bank,),))
+                    if re.match(av,elements[2]):
+                        
writepin(mgtfiles[bank],elements[0],elements[2],'line','pwr','l')
+                    else:
+                        
writepin(mgtfiles[bank],elements[0],elements[2],'line','io','r')
+                else:
+                    writepin(otherfile,elements[0],elements[2],'line','io','r')
+                    
+            elif elements[2] == 'GND':
+                writepin(powerfile,elements[0],elements[2],'line','pwr','r')
+            elif elements[2] == 'VCCINT' or elements[2] == 'VCCAUX':
+                writepin(powerfile,elements[0],elements[2],'line','pwr','l')
+            else:
+                print elements
+
+        else:    
+            bank = int(elements[1])
+            if(not(iofiles[bank])):
+                iofiles[bank] = open ( ('xc5v-ff1136small-BANK%d.src' % 
(bank,)), 'w')
+                iofiles[bank].write(boilerplate % ('BANK%d' % (bank,),))
+            if re.match(vcco,elements[2]):
+                
writepin(iofiles[bank],elements[0],elements[2],'line','pwr','b')
+            else:
+                writepin(iofiles[bank],elements[0],elements[2],'line','io','l')
+    else:
+        if len(elements)==2:
+            writepin(powerfile,elements[0],elements[1],'line','nc','b')
+        else:
+            print "Ignored line:", elements
+            
+print "Total Pins: ", pincount
+"""
+    elif(pintype == 'VCCAUX'):
+        writepin(powerfile,elements[0],elements[1],'line','pwr','l')
+    elif(pintype == 'VCCO'):
+        
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','pwr','b')
+    elif(pintype == 'VCCINT'):
+        writepin(powerfile,elements[0],elements[1],'line','pwr','l')
+
+    elif(pintype == 'JTAG'):
+        writepin(jtagfile,elements[0],elements[1],'line','io','l')
+
+    elif(pintype == 'CONFIG'):
+        writepin(configfile,elements[0],elements[1],'line','io','l')
+
+    elif(pintype == 'PWRMGMT'):
+        writepin(configfile,elements[0],elements[1],'line','io','l')
+
+    elif(pintype == 'DUAL'):
+        if(int(elements[2]) == 1):   # All these are for BPI mode, so just put 
in bank 1
+            
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','io','l')
+        elif(int(elements[2]) == 2):
+            writepin(configfile,elements[0],elements[1],'line','io','r')
+        else:
+            writepin(configfile,elements[0],elements[1],'line','io','l')
+            
+    elif(pintype == 'GCLK'):
+        if(int(elements[2]) == 0):
+            writepin(topclockfile,elements[0],elements[1],'clk','clk','l')
+        else:
+            writepin(botclockfile,elements[0],elements[1],'clk','clk','l')
+            
+    elif(pintype == 'LHCLK'):
+        writepin(lhclockfile,elements[0],elements[1],'clk','clk','l')
+
+    elif(pintype == 'RHCLK'):
+        writepin(rhclockfile,elements[0],elements[1],'clk','clk','l')
+
+    elif(pintype == 'VREF'):
+        
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','io','r')
+
+    elif(pintype == 'I/O'):
+        
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','io','l')
+
+    elif(pintype == 'INPUT'):
+        
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','in','r')
+
+    elif(pintype == 'DCI'):
+        writepin(iofiles[int(elements[12])],elements[3],"%s/DCI" % 
(elements[6],),'line','io','l')
+
+    else:
+        print elements
+"""


Property changes on: usrp-hw/trunk/sym/xilinx/xilinxgen1136-small
___________________________________________________________________
Name: svn:executable
   + *