[Commit-gnuradio] r10302 - gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib

[pcreekmore]

Author: pcreekmore
Date: 2009-01-25 22:53:16 -0700 (Sun, 25 Jan 2009)
New Revision: 10302

Modified:
   
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
Log:
Added buffer output assignments, new rounding functions, write strobe, and 
write phase counter for new quantization options.

Modified: 
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
===================================================================
--- 
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
  2009-01-25 22:19:08 UTC (rev 10301)
+++ 
gnuradio/branches/developers/pcreekmore/quantization/usrp/fpga/sdr_lib/rx_buffer.v
  2009-01-26 05:53:16 UTC (rev 10302)
@@ -53,7 +53,7 @@
     output [31:0] debugbus
     );
    
-   wire [15:0]           fifodata, fifodata_8;
+   wire [15:0]           fifodata, fifodata_8_old;
    reg [15:0]    fifodata_16;
    
    wire [11:0]           rxfifolevel;
@@ -67,7 +67,9 @@
                                            
.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
                                            
.out({bypass_hb,want_q,bitwidth,bitshift}));
 
+   // ----------------------
    // USB Read Side of FIFO
+   // ----------------------
    always @(negedge usbclk)
      have_pkt_rdy <= (rxfifolevel >= 256);
 
@@ -102,16 +104,18 @@
        .rdusedw ( rxfifolevel ),
        // Async, shared
        .aclr ( reset ) );
-
+   
+   // -----------------------
    // DSP Write Side of FIFO
+   // -----------------------
    reg [15:0] ch_0_buff0, ch_0_buff1, ch_0_buff2, ch_0_buff3, ch_0_buff4;
    reg [15:0] ch_0_buff5, ch_0_buff6, ch_0_buff7;
    reg [15:0] ch_1_buff0, ch_1_buff1, ch_1_buff2, ch_1_buff3, ch_1_buff4;
    reg [15:0] ch_1_buff5, ch_1_buff6, ch_1_buff7;
    reg [15:0] ch_2_buff0, ch_2_buff1, ch_2_buff2, ch_2_buff3;
    reg [15:0] ch_3_buff0, ch_3_buff1, ch_3_buff2, ch_3_buff3;
-   reg [15:0] ch_4_buff0, ch_4_buff1, ch_4_buff2;
-   reg [15:0] ch_5_buff0, ch_5_buff1, ch_5_buff2;
+   reg [15:0] ch_4_buff0, ch_4_buff1, ch_4_buff2, ch_4_buff3;
+   reg [15:0] ch_5_buff0, ch_5_buff1, ch_5_buff2, ch_5_buff3;
    reg [15:0] ch_6_buff0, ch_6_buff1;
    reg [15:0] ch_7_buff0, ch_7_buff1;
 
@@ -150,10 +154,12 @@
          ch_4_buff0 <= ch_4;
          ch_4_buff1 <= ch_4_buff0;
          ch_4_buff2 <= ch_4_buff1;
+         ch_4_buff3 <= ch_4_buff2;
 
          ch_5_buff0 <= ch_5;
          ch_5_buff1 <= ch_5_buff0;
          ch_5_buff2 <= ch_5_buff1;
+         ch_5_buff3 <= ch_5_buff2;
 
          ch_6_buff0 <= ch_6;
          ch_6_buff1 <= ch_6_buff0;
@@ -225,6 +231,13 @@
      else
        buffs_ready <= 0;
 
+   // write strobe; begins fifo write for a single read phase
+   reg write_strobe;
+   always @(posedge buffs_ready)
+     write_strobe <= 1;
+   always @(posedge rxclk)
+     write_strobe <= 0;
+
    // "read phase" counter to keep track of 6-channel cases
    // Note: could easily change this to only increment for the 6-channel case 
if necessary
    reg [1:0] read_phase;
@@ -233,13 +246,174 @@
        read_phase <= 2'd0;
      else
        case(bitwidth)
-         5'd4 : if (read_phase == 2) read_phase <= 1; else read_phase <= 
read_phase+1;
-         5'd2 : if (read_phase == 3) read_phase <= 1; else read_phase <= 
read_phase+1;
-         5'd1 : if (read_phase == 3) read_phase <= 1; else read_phase <= 
read_phase+1;
-         default : read_phase <= 1;
+         5'd4 : if (read_phase == 2'd2) read_phase <= 2'd1; else read_phase <= 
read_phase+2'd1;
+         5'd2 : if (read_phase == 2'd3) read_phase <= 2'd1; else read_phase <= 
read_phase+2'd1;
+         5'd1 : if (read_phase == 2'd3) read_phase <= 2'd1; else read_phase <= 
read_phase+2'd1;
+         default : read_phase <= 2'd1;
        endcase
 
-   // "write phase" counter to keep track of cases with multiple fifo writes 
per rxstrobe
+   // Buffer output assignments, based on number of channels and sample width 
(bitwidth)
+   reg [15:0] fifodata_1, fifodata_2, fifodata_3, fifodata_4, fifodata_5, 
fifodata_6, fifodata_7, fifodata_8;
+   always @(posedge write_strobe)
+     begin
+       if (bitwidth == 5'd16)
+         begin
+           fifodata_1 <= ch_0_buff0;
+           fifodata_2 <= ch_1_buff0;
+           fifodata_3 <= ch_2_buff0;
+           fifodata_4 <= ch_3_buff0;
+           fifodata_5 <= ch_4_buff0;
+           fifodata_6 <= ch_5_buff0;
+           fifodata_7 <= ch_6_buff0;
+           fifodata_8 <= ch_7_buff0;
+         end
+       else if (bitwidth == 5'd8)
+         begin
+           fifodata_1 <= {round_8(ch_1_buff0),round_8(ch_0_buff0)};
+           fifodata_2 <= {round_8(ch_3_buff0),round_8(ch_2_buff0)};
+           fifodata_3 <= {round_8(ch_5_buff0),round_8(ch_4_buff0)};
+           fifodata_4 <= {round_8(ch_7_buff0),round_8(ch_6_buff0)};
+         end
+       else
+         case(channels)
+           4'd2 :
+             case(bitwidth)
+               5'd4 : fifodata_1 <= 
{round_4(ch_1_buff0),round_4(ch_0_buff0),round_4(ch_1_buff1),round_4(ch_0_buff1)};
+               5'd2 : fifodata_1 <= 
{round_2(ch_1_buff0),round_2(ch_0_buff0),round_2(ch_1_buff1),round_2(ch_0_buff1),
+                                     
round_2(ch_1_buff2),round_2(ch_0_buff2),round_2(ch_1_buff3),round_2(ch_0_buff3)};
+               5'd1 : fifodata_1 <= 
{round_1(ch_1_buff0),round_1(ch_0_buff0),round_1(ch_1_buff1),round_1(ch_0_buff1),
+                                     
round_1(ch_1_buff2),round_1(ch_0_buff2),round_1(ch_1_buff3),round_1(ch_0_buff3),
+                                     
round_1(ch_1_buff4),round_1(ch_0_buff4),round_1(ch_1_buff5),round_1(ch_0_buff5),
+                                     
round_1(ch_1_buff6),round_1(ch_0_buff6),round_1(ch_1_buff7),round_1(ch_0_buff7)};
+               default: fifodata_1 <= 16'b0;
+             endcase
+           4'd4 :
+             case(bitwidth)
+               5'd4 : fifodata_1 <= 
{round_4(ch_3_buff0),round_4(ch_2_buff0),round_4(ch_1_buff0),round_4(ch_0_buff0)};
+               5'd2 : fifodata_1 <= 
{round_2(ch_3_buff0),round_2(ch_2_buff0),round_2(ch_1_buff0),round_2(ch_0_buff0),
+                                     
round_2(ch_3_buff1),round_2(ch_2_buff1),round_2(ch_1_buff1),round_2(ch_0_buff1)};
+               5'd1 : fifodata_1 <= 
{round_1(ch_3_buff0),round_1(ch_2_buff0),round_1(ch_1_buff0),round_1(ch_0_buff0),
+                                     
round_1(ch_3_buff1),round_1(ch_2_buff1),round_1(ch_1_buff1),round_1(ch_0_buff1),
+                                     
round_1(ch_3_buff2),round_1(ch_2_buff2),round_1(ch_1_buff2),round_1(ch_0_buff2),
+                                     
round_1(ch_3_buff3),round_1(ch_2_buff3),round_1(ch_1_buff3),round_1(ch_0_buff3)};
+               default : fifodata_1 <= 16'b0;
+             endcase
+           4'd6 :
+             case(bitwidth)
+               5'd4 :
+                 case(read_phase)
+                   2'd1 : fifodata_1 <= 
{round_4(ch_3_buff0),round_4(ch_2_buff0),round_4(ch_1_buff0),round_4(ch_0_buff0)};
+                   2'd2 : begin
+                     fifodata_1 <= 
{round_4(ch_1_buff0),round_4(ch_0_buff0),round_4(ch_5_buff1),round_4(ch_4_buff1)};
+                     fifodata_2 <= 
{round_4(ch_5_buff0),round_4(ch_4_buff0),round_4(ch_3_buff0),round_4(ch_2_buff0)};
+                   end
+                   default : fifodata_1 <= 16'b0;
+                 endcase
+               5'd2 :
+                 case(read_phase)
+                   2'd1 : fifodata_1 <= 
{round_2(ch_1_buff0),round_2(ch_0_buff0),round_2(ch_5_buff1),round_2(ch_4_buff1),
+                                         
round_2(ch_3_buff1),round_2(ch_2_buff1),round_2(ch_1_buff1),round_2(ch_0_buff1)};
+                   2'd2 : fifodata_1 <= 
{round_2(ch_3_buff0),round_2(ch_2_buff0),round_2(ch_1_buff0),round_2(ch_0_buff0),
+                                         
round_2(ch_5_buff1),round_2(ch_4_buff1),round_2(ch_3_buff1),round_2(ch_2_buff1)};
+                   2'd3 : fifodata_1 <= 
{round_2(ch_5_buff0),round_2(ch_4_buff0),round_2(ch_3_buff0),round_2(ch_2_buff0),
+                                         
round_2(ch_1_buff0),round_2(ch_0_buff0),round_2(ch_5_buff1),round_2(ch_4_buff1)};
+                   default : fifodata_1 <= 16'b0;
+                 endcase
+               5'd1 :
+                 case(read_phase)
+                   2'd1 : fifodata_1 <= 
{round_1(ch_3_buff0),round_1(ch_2_buff0),round_1(ch_1_buff0),round_1(ch_0_buff0),
+                                         
round_1(ch_5_buff1),round_1(ch_4_buff1),round_1(ch_3_buff1),round_1(ch_2_buff1),
+                                         
round_1(ch_1_buff1),round_1(ch_0_buff1),round_1(ch_5_buff2),round_1(ch_4_buff2),
+                                         
round_1(ch_3_buff2),round_1(ch_2_buff2),round_1(ch_1_buff2),round_1(ch_0_buff2)};
+                   2'd2 : fifodata_1 <= 
{round_1(ch_1_buff0),round_1(ch_0_buff0),round_1(ch_5_buff1),round_1(ch_4_buff1),
+                                         
round_1(ch_3_buff1),round_1(ch_2_buff1),round_1(ch_1_buff1),round_1(ch_0_buff1),
+                                         
round_1(ch_5_buff2),round_1(ch_4_buff2),round_1(ch_3_buff2),round_1(ch_2_buff2),
+                                         
round_1(ch_1_buff2),round_1(ch_0_buff2),round_1(ch_5_buff3),round_1(ch_4_buff3)};
+                   2'd3 : fifodata_1 <= 
{round_1(ch_5_buff0),round_1(ch_4_buff0),round_1(ch_3_buff0),round_1(ch_2_buff0),
+                                         
round_1(ch_1_buff0),round_1(ch_0_buff0),round_1(ch_5_buff1),round_1(ch_4_buff1),
+                                         
round_1(ch_3_buff1),round_1(ch_2_buff1),round_1(ch_1_buff1),round_1(ch_0_buff1),
+                                         
round_1(ch_5_buff2),round_1(ch_4_buff2),round_1(ch_3_buff2),round_1(ch_2_buff2)};
+                   default : fifodata_1 <= 16'b0;
+                 endcase
+               default : fifodata_1 <= 16'b0;
+             endcase
+           4'd8 :
+             case(bitwidth)
+               5'd4 : begin
+                 fifodata_1 <= 
{round_4(ch_3_buff0),round_4(ch_2_buff0),round_4(ch_1_buff0),round_4(ch_0_buff0)};
+                 fifodata_2 <= 
{round_4(ch_7_buff0),round_4(ch_6_buff0),round_4(ch_5_buff0),round_4(ch_4_buff0)};
+               end
+               5'd2 : fifodata_1 <= 
{round_2(ch_7_buff0),round_2(ch_6_buff0),round_2(ch_5_buff0),round_2(ch_4_buff0),
+                                     
round_2(ch_3_buff0),round_2(ch_2_buff0),round_2(ch_1_buff0),round_2(ch_0_buff0)};
+               5'd1 : fifodata_1 <= 
{round_1(ch_7_buff0),round_1(ch_6_buff0),round_1(ch_5_buff0),round_1(ch_4_buff0),
+                                     
round_1(ch_3_buff0),round_1(ch_2_buff0),round_1(ch_1_buff0),round_1(ch_0_buff0),
+                                     
round_1(ch_7_buff1),round_1(ch_6_buff1),round_1(ch_5_buff1),round_1(ch_4_buff1),
+                                     
round_1(ch_3_buff1),round_1(ch_2_buff1),round_1(ch_1_buff1),round_1(ch_0_buff1)};
+               default : fifodata_1 <= 16'b0;
+             endcase
+           default : fifodata_1 <= 16'b0;
+         endcase
+     end
+
+   // total number of writes per read phase
+   reg [3:0] total_writes;
+   always @(bitwidth or channels or read_phase)
+     if (bitwidth == 5'd2 || bitwidth == 5'd1)
+       total_writes <= 1;
+     else
+       case(bitwidth)
+         5'd4 :
+           case(channels)
+             4'd2 : total_writes <= 4'd1;
+             4'd4 : total_writes <= 4'd1;
+             4'd6 :
+               case(read_phase)
+                 2'd1 : total_writes <= 4'd1;
+                 2'd2 : total_writes <= 4'd2;
+                 default : total_writes <= 4'b0;
+               endcase
+             4'd8 : total_writes <= 4'd2;
+             default : total_writes <= 4'd0;
+           endcase
+         5'd8 :
+           case(channels)
+             4'd2 : total_writes <= 4'd1;
+             4'd4 : total_writes <= 4'd2;
+             4'd6 : total_writes <= 4'd3;
+             4'd8 : total_writes <= 4'd4;
+             default : total_writes <= 4'd0;
+           endcase
+         5'd16 :
+           case(channels)
+             4'd2 : total_writes <= 4'd2;
+             4'd4 : total_writes <= 4'd4;
+             4'd6 : total_writes <= 4'd6;
+             4'd8 : total_writes <= 4'd8;
+             default : total_writes <= 4'd0;
+           endcase
+         default : total_writes <= 0;
+       endcase
+
+   // "write phase" counter to keep track of cases with multiple fifo writes 
per read phase
+   //  FIXME: in the event of a write strobe every clock cycle and a faulty 
channel/bitwidth
+   //         combination, the write_phase will stay at 1, possibly sending 
junk data to
+   //         the fifo.
+   reg [3:0] write_phase;
+   always @(posedge rxclk)
+     if (reset)
+       write_phase <= 0;
+     else if (write_phase == 4'd0 && write_strobe)
+       write_phase <= 1;
+     else if (write_phase >= total_writes)
+       if (write_strobe)
+         write_phase <= 1;
+       else 
+         write_phase <= 0;
+     else if (write_phase != 4'd0)
+       write_phase <= write_phase + 4'd1;
+     else
+       write_phase <= 0;
+
    reg [3:0] phase;
    always @(posedge rxclk)
      if(reset)
@@ -255,16 +429,32 @@
        else
         phase <= phase + 4'd1;
    
-   assign    fifodata = (bitwidth == 5'd8) ? fifodata_8 : fifodata_16;
+   assign    fifodata = (bitwidth == 5'd8) ? fifodata_8_old : fifodata_16;
    
-   assign    fifodata_8 = {round_8(top),round_8(bottom)};
+   assign    fifodata_8_old = {round_8(top),round_8(bottom)};
    reg [15:0] top,bottom;
    
+   // Rounding (Quantization) functions
    function [7:0] round_8;
       input [15:0] in_val;
       
       round_8 = in_val[15:8] + (in_val[15] & |in_val[7:0]);
    endfunction // round_8
+
+   function [3:0] round_4;
+     input [15:0] in_val;
+     round_4 = in_val[15:12] + (in_val[15] & |in_val[11:0]);
+   endfunction // round_4
+
+   function [1:0] round_2;
+     input [15:0] in_val;
+     round_2 = in_val[15:14] + (in_val[15] & |in_val[13:0]);
+   endfunction // round_2
+
+   function [0:0] round_1;
+     input [15:0] in_val;
+     round_1 = ~in_val[15];
+   endfunction // round_1
       
    always @*
      case(phase)