[Commit-gnuradio] r10289 - in gnuradio/trunk/usrp2/fpga/opencores/aemb/rtl/verilog: . CVS

[matt]

Author: matt
Date: 2009-01-22 11:22:11 -0700 (Thu, 22 Jan 2009)
New Revision: 10289

Modified:
   gnuradio/trunk/usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Entries
   gnuradio/trunk/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_sim.v
Log:
catching up with shawn.  these aren't used here anyway.


Modified: gnuradio/trunk/usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Entries
===================================================================
--- gnuradio/trunk/usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Entries    
2009-01-22 18:06:58 UTC (rev 10288)
+++ gnuradio/trunk/usrp2/fpga/opencores/aemb/rtl/verilog/CVS/Entries    
2009-01-22 18:22:11 UTC (rev 10289)
@@ -1,11 +1,3 @@
-/aeMB_bpcu.v/1.4/Mon Feb  4 17:16:00 2008//
-/aeMB_core.v/1.9/Mon Feb  4 17:16:00 2008//
-/aeMB_ctrl.v/1.10/Mon Feb  4 17:16:00 2008//
-/aeMB_edk32.v/1.14/Mon Feb  4 17:16:00 2008//
-/aeMB_ibuf.v/1.10/Tue May 20 17:45:01 2008//
-/aeMB_regf.v/1.3/Mon Feb  4 17:16:00 2008//
-/aeMB_sim.v/1.1/Mon Feb  4 17:16:00 2008//
-/aeMB_xecu.v/1.12/Tue May 20 17:48:57 2008//
 /aeMB2_aslu.v/1.10/Tue May 20 18:13:50 2008//
 /aeMB2_bpcu.v/1.5/Tue May 20 18:13:50 2008//
 /aeMB2_brcc.v/1.3/Tue May 20 18:13:50 2008//
@@ -35,4 +27,12 @@
 /aeMB2_sysc.v/1.5/Tue May 20 18:13:51 2008//
 /aeMB2_tpsram.v/1.3/Tue May 20 18:13:51 2008//
 /aeMB2_xslif.v/1.7/Tue May 20 18:13:52 2008//
+/aeMB_bpcu.v/1.4/Thu Sep 11 02:11:12 2008//
+/aeMB_core.v/1.9/Thu Sep 11 02:11:12 2008//
+/aeMB_ctrl.v/1.10/Thu Sep 11 02:11:12 2008//
+/aeMB_edk32.v/1.14/Thu Sep 11 02:11:12 2008//
+/aeMB_ibuf.v/1.10/Thu Sep 11 02:11:12 2008//
+/aeMB_regf.v/1.3/Thu Sep 11 02:11:12 2008//
+/aeMB_sim.v/1.2/Thu Jan 22 05:50:30 2009//
+/aeMB_xecu.v/1.12/Thu Sep 11 02:11:12 2008//
 D

Modified: gnuradio/trunk/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_sim.v
===================================================================
--- gnuradio/trunk/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_sim.v     
2009-01-22 18:06:58 UTC (rev 10288)
+++ gnuradio/trunk/usrp2/fpga/opencores/aemb/rtl/verilog/aeMB_sim.v     
2009-01-22 18:22:11 UTC (rev 10289)
@@ -1,4 +1,4 @@
-/* $Id: aeMB_sim.v,v 1.1 2007/12/23 20:40:45 sybreon Exp $
+/* $Id: aeMB_sim.v,v 1.2 2008/06/06 09:36:02 sybreon Exp $
 **
 ** AEMB EDK 3.2 Compatible Core
 ** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -104,7 +104,9 @@
    wire [DW-1:0]       dwb_adr = {dwb_adr_o,2'd0};   
    wire [1:0]          wBRA = {cpu.rBRA, cpu.rDLY};   
    wire [3:0]          wMSR = {cpu.xecu.rMSR_BIP, cpu.xecu.rMSR_C, 
cpu.xecu.rMSR_IE, cpu.xecu.rMSR_BE};
-   
+
+
+   `ifdef AEMB_SIM_KERNEL
    always @(posedge cpu.gclk) begin
       if (cpu.gena) begin
         
@@ -293,6 +295,7 @@
       end // if (cpu.gena)
       
    end // always @ (posedge cpu.gclk)
+   `endif //  `ifdef AEMB_SIM_KERNEL
    
    // synopsys translate_on
    
@@ -300,6 +303,9 @@
 
 /* 
  $Log: aeMB_sim.v,v $
+ Revision 1.2  2008/06/06 09:36:02  sybreon
+ single thread design
+
  Revision 1.1  2007/12/23 20:40:45  sybreon
  Abstracted simulation kernel (aeMB_sim) to split simulation models from 
synthesis models.