[Commit-gnuradio] r10210 - usrp-hw/trunk/sym/xilinx

[matt]

Author: matt
Date: 2009-01-12 18:28:02 -0700 (Mon, 12 Jan 2009)
New Revision: 10210

Added:
   usrp-hw/trunk/sym/xilinx/Makefile
Modified:
   usrp-hw/trunk/sym/xilinx/
   usrp-hw/trunk/sym/xilinx/xilinxgen1136
Log:
seems to generate ok parts



Property changes on: usrp-hw/trunk/sym/xilinx
___________________________________________________________________
Name: svn:ignore
   + *.log


Added: usrp-hw/trunk/sym/xilinx/Makefile
===================================================================
--- usrp-hw/trunk/sym/xilinx/Makefile                           (rev 0)
+++ usrp-hw/trunk/sym/xilinx/Makefile   2009-01-13 01:28:02 UTC (rev 10210)
@@ -0,0 +1,45 @@
+#!/usr/bin/make
+
+TRAGESYM=tragesym
+
+SOURCES= \
+       xc5v-ff1136big-PWR.sym \
+       xc5v-ff1136big-OTHER.sym \
+       xc5v-ff1136big-BANK0.sym \
+       xc5v-ff1136big-BANK1.sym \
+       xc5v-ff1136big-BANK2.sym \
+       xc5v-ff1136big-BANK3.sym \
+       xc5v-ff1136big-BANK4.sym \
+       xc5v-ff1136big-BANK5.sym \
+       xc5v-ff1136big-BANK6.sym \
+       xc5v-ff1136big-BANK11.sym \
+       xc5v-ff1136big-BANK12.sym \
+       xc5v-ff1136big-BANK13.sym \
+       xc5v-ff1136big-BANK15.sym \
+       xc5v-ff1136big-BANK17.sym \
+       xc5v-ff1136big-BANK18.sym \
+       xc5v-ff1136big-BANK19.sym \
+       xc5v-ff1136big-BANK20.sym \
+       xc5v-ff1136big-BANK21.sym \
+       xc5v-ff1136big-BANK22.sym \
+       xc5v-ff1136big-BANK23.sym \
+       xc5v-ff1136big-BANK25.sym \
+       xc5v-ff1136big-BANK112.sym \
+       xc5v-ff1136big-BANK114.sym \
+       xc5v-ff1136big-BANK116.sym \
+       xc5v-ff1136big-BANK118.sym \
+       xc5v-ff1136big-BANK120.sym \
+       xc5v-ff1136big-BANK122.sym \
+       xc5v-ff1136big-BANK124.sym \
+       xc5v-ff1136big-BANK126.sym
+
+
+
+all : $(SOURCES)
+
+clean : 
+       @rm -f *.sym
+
+%.sym : %.src
+       $(TRAGESYM) $< $@
+

Modified: usrp-hw/trunk/sym/xilinx/xilinxgen1136
===================================================================
--- usrp-hw/trunk/sym/xilinx/xilinxgen1136      2009-01-12 22:39:36 UTC (rev 
10209)
+++ usrp-hw/trunk/sym/xilinx/xilinxgen1136      2009-01-13 01:28:02 UTC (rev 
10210)
@@ -1,14 +1,21 @@
 #!/usr/bin/python
 
+pincount = 0
+
 import re
-matchstr = re.compile("_")
+underscore = re.compile("_")
+vcco = re.compile("VCCO")
+mgt = re.compile("MGT")
+av = re.compile("MGTAV")
 
 def writepin(file,number,name,linetype,pintype,pos):
-    #newname = matchstr.sub("\\_",name)
+    #newname = underscore.sub("\\_",name)
     newname = name
+    global pincount
     file.write("%s\t\t%s\t%s\t%s\t\t%s\n" % 
(number,pintype,linetype,pos,newname))
+    pincount = pincount + 1
 
-pinfile = open ('XC3SD3400AFG676.csv','r')
+pinfile = open ('ff1136_big.txt','r')
 
 boilerplate = '''
 [options]
@@ -21,61 +28,80 @@
 pinwidthhorizontal=400
 [geda_attr]
 version=20060906
-name=XC3SD3400AFG676-%s
-device=XC3SD3400AFG676
+name=XC5V-FF1136BIG-%s
+device=XC5V-FF1136BIG
 refdes=U?
-footprint=FG676
-description=Xilinx Spartan 3A-DSP 1800/3400 FG676
+footprint=FF1136
+description=Xilinx Virtex5 1136 pin BGA
 documentation=http://www.xilinx.com
 author=xilinxgen.py
 numslots=0
 [pins]
 '''
 
-configfile = open ('xc3sd3400afg676-CFG.src', 'w')
-configfile.write(boilerplate % ("CFG",))
-
-jtagfile = open ('xc3sd3400afg676-JTAG.src', 'w')
-jtagfile.write(boilerplate % ("JTAG",))
-powerfile = open ('xc3sd3400afg676-PWR.src', 'w')
+powerfile = open ('xc5v-ff1136big-PWR.src', 'w')
 powerfile.write(boilerplate % ("PWR",))
-topclockfile = open ('xc3sd3400afg676-TOPCLK.src', 'w')
-topclockfile.write(boilerplate % ("TOPCLK",))
-botclockfile = open ('xc3sd3400afg676-BOTCLK.src', 'w')
-botclockfile.write(boilerplate % ("BOTCLK",))
-lhclockfile = open ('xc3sd3400afg676-LHCLK.src', 'w')
-lhclockfile.write(boilerplate % ("LHCLK",))
-rhclockfile = open ('xc3sd3400afg676-RHCLK.src', 'w')
-rhclockfile.write(boilerplate % ("RHCLK",))
+otherfile = open ('xc5v-ff1136big-OTHER.src', 'w')
+otherfile.write(boilerplate % ("OTHER",))
 
-iofiles = [0] * 4
-for i in range(4):
-    iofiles[i] = open ( ('xc3sd3400afg676-IO%d.src' % (i,)), 'w')
-    iofiles[i].write(boilerplate % ('IO%d' % (i,),))
+banks = 26
+iofiles = [0] * banks
+mgtbanks = 127
+mgtfiles = [0] * mgtbanks
+
     
 dummy = pinfile.readline()
+dummy = pinfile.readline()
 lines = pinfile.readlines()
 
 for line in lines:
-    elements = line.strip().split(',')
+    elements = line.strip().split('\t')
 
-    pintype = elements[3]
-    #nc = elements[5] == "N.C."
+    #writepin(file,number,name,linetype,pintype,pos):
 
-    #if(elements[5] != elements[9]) and not nc:
-    #    print "error"
-    #    print elements
+    if len(elements) == 3:
+        if elements[1] == 'NA':
+            if re.match(mgt,elements[2]):
+                if re.search(underscore,elements[2]):
+                    (dummy,bank) = elements[2].split('_')
+                    bank = int(bank)
+                    if(not(mgtfiles[bank])):
+                        mgtfiles[bank] = open ( ('xc5v-ff1136big-BANK%d.src' % 
(bank,)), 'w')
+                        mgtfiles[bank].write(boilerplate % ('BANK%d' % 
(bank,),))
+                    if re.match(av,elements[2]):
+                        
writepin(mgtfiles[bank],elements[0],elements[2],'line','pwr','l')
+                    else:
+                        
writepin(mgtfiles[bank],elements[0],elements[2],'line','io','r')
+                else:
+                    writepin(otherfile,elements[0],elements[2],'line','io','r')
+                    
+            elif elements[2] == 'GND':
+                writepin(powerfile,elements[0],elements[2],'line','pwr','r')
+            elif elements[2] == 'VCCINT' or elements[2] == 'VCCAUX':
+                writepin(powerfile,elements[0],elements[2],'line','pwr','l')
+            else:
+                print elements
 
-    #if nc and pintype != 'I/O' and pintype != 'VREF':
-    #    print "error"
-    #    print elements
-    
-    if(pintype == 'GND'):
-        writepin(powerfile,elements[0],elements[1],'line','pwr','r')
+        else:    
+            bank = int(elements[1])
+            if(not(iofiles[bank])):
+                iofiles[bank] = open ( ('xc5v-ff1136big-BANK%d.src' % 
(bank,)), 'w')
+                iofiles[bank].write(boilerplate % ('BANK%d' % (bank,),))
+            if re.match(vcco,elements[2]):
+                
writepin(iofiles[bank],elements[0],elements[2],'line','pwr','b')
+            else:
+                writepin(iofiles[bank],elements[0],elements[2],'line','io','l')
+    else:
+        if len(elements)==2:
+            writepin(powerfile,elements[0],elements[1],'line','nc','b')
+        else:
+            print "Ignored line:", elements
+            
+print "Total Pins: ", pincount
+"""
     elif(pintype == 'VCCAUX'):
         writepin(powerfile,elements[0],elements[1],'line','pwr','l')
     elif(pintype == 'VCCO'):
-        #writepin(powerfile,elements[3],elements[6],'line','pwr','l')
         
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','pwr','b')
     elif(pintype == 'VCCINT'):
         writepin(powerfile,elements[0],elements[1],'line','pwr','l')
@@ -84,11 +110,9 @@
         writepin(jtagfile,elements[0],elements[1],'line','io','l')
 
     elif(pintype == 'CONFIG'):
-        #writepin(configfile,elements[0],elements[1],'line','io','b')
         writepin(configfile,elements[0],elements[1],'line','io','l')
 
     elif(pintype == 'PWRMGMT'):
-        #writepin(configfile,elements[0],elements[1],'line','io','b')
         writepin(configfile,elements[0],elements[1],'line','io','l')
 
     elif(pintype == 'DUAL'):
@@ -125,3 +149,4 @@
 
     else:
         print elements
+"""