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[Commit-gnuradio] r10159 - usrp-hw/trunk/sym/generated
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r10159 - usrp-hw/trunk/sym/generated |
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Date: |
Tue, 23 Dec 2008 01:13:45 -0700 (MST) |
Author: matt
Date: 2008-12-23 01:13:43 -0700 (Tue, 23 Dec 2008)
New Revision: 10159
Added:
usrp-hw/trunk/sym/generated/XC3SD1800AFG676.csv
usrp-hw/trunk/sym/generated/XC3SD3400AFG676.csv
usrp-hw/trunk/sym/generated/cy7c1354cv25-ac-CTRL.src
usrp-hw/trunk/sym/generated/cy7c1354cv25-ac-PWR.src
usrp-hw/trunk/sym/generated/cy7c1354cv25-ac-RAM.src
usrp-hw/trunk/sym/generated/xc3sd3400afg676-BOTCLK.src
usrp-hw/trunk/sym/generated/xc3sd3400afg676-CFG.src
usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO0.src
usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO1.src
usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO2.src
usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO3.src
usrp-hw/trunk/sym/generated/xc3sd3400afg676-JTAG.src
usrp-hw/trunk/sym/generated/xc3sd3400afg676-LHCLK.src
usrp-hw/trunk/sym/generated/xc3sd3400afg676-PWR.src
usrp-hw/trunk/sym/generated/xc3sd3400afg676-RHCLK.src
usrp-hw/trunk/sym/generated/xc3sd3400afg676-TOPCLK.src
usrp-hw/trunk/sym/generated/xilinxgen676
Modified:
usrp-hw/trunk/sym/generated/Makefile
Log:
yet more chips
Modified: usrp-hw/trunk/sym/generated/Makefile
===================================================================
--- usrp-hw/trunk/sym/generated/Makefile 2008-12-23 04:20:34 UTC (rev
10158)
+++ usrp-hw/trunk/sym/generated/Makefile 2008-12-23 08:13:43 UTC (rev
10159)
@@ -165,6 +165,9 @@
cy7c1356cv25-ac-PWR.sym \
cy7c1356cv25-ac-CTRL.sym \
cy7c1356cv25-ac-RAM.sym \
+ cy7c1354cv25-ac-PWR.sym \
+ cy7c1354cv25-ac-CTRL.sym \
+ cy7c1354cv25-ac-RAM.sym \
ipass-sas-x4.sym \
adl5385-PWR.sym \
adl5385-MIX.sym \
@@ -194,6 +197,17 @@
xc3sd1800acs484-RHCLK.sym \
xc3sd1800acs484-JTAG.sym \
xc3sd1800acs484-PWR.sym \
+ xc3sd3400afg676-CFG.sym \
+ xc3sd3400afg676-TOPCLK.sym \
+ xc3sd3400afg676-BOTCLK.sym \
+ xc3sd3400afg676-IO0.sym \
+ xc3sd3400afg676-IO1.sym \
+ xc3sd3400afg676-IO2.sym \
+ xc3sd3400afg676-IO3.sym \
+ xc3sd3400afg676-LHCLK.sym \
+ xc3sd3400afg676-RHCLK.sym \
+ xc3sd3400afg676-JTAG.sym \
+ xc3sd3400afg676-PWR.sym \
adl5375-MIX.sym \
adl5375-PWR.sym \
spi-flash-so16.sym \
Added: usrp-hw/trunk/sym/generated/XC3SD1800AFG676.csv
===================================================================
--- usrp-hw/trunk/sym/generated/XC3SD1800AFG676.csv
(rev 0)
+++ usrp-hw/trunk/sym/generated/XC3SD1800AFG676.csv 2008-12-23 08:13:43 UTC
(rev 10159)
@@ -0,0 +1,677 @@
+PIN,XC3SD1800AFG676_PIN,XC3SD1800AFG676_BANK,TYPE,DIFF_PAIR,ROW,ROW_#,COLUMN
+A1,GND,GND,GND,,A,1,1
+A2,PROG_B,VCCAUX,CONFIG,,A,1,2
+A3,IO_L51P_0,0,I/O,TRUE,A,1,3
+A4,IO_L45P_0,0,I/O,TRUE,A,1,4
+A5,IP_0,0,INPUT,,A,1,5
+A6,GND,GND,GND,,A,1,6
+A7,IP_0,0,INPUT,,A,1,7
+A8,IO_L38P_0,0,I/O,TRUE,A,1,8
+A9,IO_L36P_0,0,I/O,TRUE,A,1,9
+A10,IO_L33P_0,0,I/O,TRUE,A,1,10
+A11,GND,GND,GND,,A,1,11
+A12,IO_L29P_0,0,I/O,TRUE,A,1,12
+A13,IP_0,0,INPUT,,A,1,13
+A14,IO_L26N_0/GCLK7,0,GCLK,TRUE,A,1,14
+A15,IO_L23N_0,0,I/O,TRUE,A,1,15
+A16,GND,GND,GND,,A,1,16
+A17,IP_0,0,INPUT,,A,1,17
+A18,IO_L18N_0,0,I/O,TRUE,A,1,18
+A19,IO_L15N_0,0,I/O,TRUE,A,1,19
+A20,IO_L14N_0,0,I/O,TRUE,A,1,20
+A21,GND,GND,GND,,A,1,21
+A22,IO_L07N_0,0,I/O,TRUE,A,1,22
+A23,IP_0,0,INPUT,,A,1,23
+A24,IP_0,0,INPUT,,A,1,24
+A25,TCK,VCCAUX,JTAG,,A,1,25
+A26,GND,GND,GND,,A,1,26
+AA1,GND,GND,GND,,AA,21,1
+AA2,IO_L55P_3,3,I/O,TRUE,AA,21,2
+AA3,IO_L55N_3,3,I/O,TRUE,AA,21,3
+AA4,IP_L58P_3,3,INPUT,TRUE,AA,21,4
+AA5,IP_L58N_3/VREF_3,3,VREF,TRUE,AA,21,5
+AA6,GND,GND,GND,,AA,21,6
+AA7,IO_L02N_2/CSO_B,2,DUAL,TRUE,AA,21,7
+AA8,IP_2,2,INPUT,,AA,21,8
+AA9,IP_2/VREF_2,2,VREF,,AA,21,9
+AA10,IO_L12N_2,2,I/O,TRUE,AA,21,10
+AA11,GND,GND,GND,,AA,21,11
+AA12,IO_L17N_2/VS2,2,DUAL,TRUE,AA,21,12
+AA13,IO_L25P_2/GCLK12,2,GCLK,TRUE,AA,21,13
+AA14,IO_L27N_2/GCLK1,2,GCLK,TRUE,AA,21,14
+AA15,IO_L34P_2/INIT_B,2,DUAL,TRUE,AA,21,15
+AA16,GND,GND,GND,,AA,21,16
+AA17,IO_L43P_2,2,I/O,TRUE,AA,21,17
+AA18,IO_L47N_2,2,I/O,TRUE,AA,21,18
+AA19,IP_2,2,INPUT,,AA,21,19
+AA20,IP_2/VREF_2,2,VREF,,AA,21,20
+AA21,GND,GND,GND,,AA,21,21
+AA22,IO_L09P_1,1,I/O,TRUE,AA,21,22
+AA23,IO_L09N_1,1,I/O,TRUE,AA,21,23
+AA24,IO_L11P_1,1,I/O,TRUE,AA,21,24
+AA25,IO_L11N_1,1,I/O,TRUE,AA,21,25
+AA26,GND,GND,GND,,AA,21,26
+AB1,IO_L60P_3,3,I/O,TRUE,AB,22,1
+AB2,VCCO_3,3,VCCO,,AB,22,2
+AB3,IP_L62P_3,3,INPUT,TRUE,AB,22,3
+AB4,IP_L62N_3,3,INPUT,TRUE,AB,22,4
+AB5,VCCAUX,VCCAUX,VCCAUX,,AB,22,5
+AB6,IP_2/VREF_2,2,VREF,,AB,22,6
+AB7,IO_L14N_2,2,I/O,TRUE,AB,22,7
+AB8,VCCO_2,2,VCCO,,AB,22,8
+AB9,IO_L15P_2,2,I/O,TRUE,AB,22,9
+AB10,IP_2/VREF_2,2,VREF,,AB,22,10
+AB11,VCCAUX,VCCAUX,VCCAUX,,AB,22,11
+AB12,IO_L21P_2,2,I/O,TRUE,AB,22,12
+AB13,IP_2,2,INPUT,,AB,22,13
+AB14,VCCO_2,2,VCCO,,AB,22,14
+AB15,IO_L30N_2/MOSI/CSI_B,2,DUAL,TRUE,AB,22,15
+AB16,IO_L38N_2,2,I/O,TRUE,AB,22,16
+AB17,IP_2,2,INPUT,,AB,22,17
+AB18,IO_L47P_2,2,I/O,TRUE,AB,22,18
+AB19,VCCO_2,2,VCCO,,AB,22,19
+AB20,IP_2,2,INPUT,,AB,22,20
+AB21,DONE,VCCAUX,CONFIG,,AB,22,21
+AB22,VCCAUX,VCCAUX,VCCAUX,,AB,22,22
+AB23,IO_L07P_1,1,I/O,TRUE,AB,22,23
+AB24,IO_L07N_1/VREF_1,1,VREF,TRUE,AB,22,24
+AB25,VCCO_1,1,VCCO,,AB,22,25
+AB26,IO_L06N_1,1,I/O,TRUE,AB,22,26
+AC1,IO_L60N_3,3,I/O,TRUE,AC,23,1
+AC2,IO_L64P_3,3,I/O,TRUE,AC,23,2
+AC3,IO_L64N_3,3,I/O,TRUE,AC,23,3
+AC4,IO_L01P_2/M1,2,DUAL,TRUE,AC,23,4
+AC5,IP_2,2,INPUT,,AC,23,5
+AC6,IO_L08P_2,2,I/O,TRUE,AC,23,6
+AC7,IP_2,2,INPUT,,AC,23,7
+AC8,IO_L14P_2,2,I/O,TRUE,AC,23,8
+AC9,IO_L15N_2,2,I/O,TRUE,AC,23,9
+AC10,IP_2/VREF_2,2,VREF,,AC,23,10
+AC11,IO_L23N_2,2,I/O,TRUE,AC,23,11
+AC12,IO_L21N_2,2,I/O,TRUE,AC,23,12
+AC13,IP_2,2,INPUT,,AC,23,13
+AC14,IO_L29N_2,2,I/O,TRUE,AC,23,14
+AC15,IO_L30P_2,2,I/O,TRUE,AC,23,15
+AC16,IO_L38P_2,2,I/O,TRUE,AC,23,16
+AC17,IP_2,2,INPUT,,AC,23,17
+AC18,IP_2,2,INPUT,,AC,23,18
+AC19,IO_L40N_2,2,I/O,TRUE,AC,23,19
+AC20,IO_L41N_2,2,I/O,TRUE,AC,23,20
+AC21,IO_L45N_2,2,I/O,TRUE,AC,23,21
+AC22,IO_2,2,I/O,,AC,23,22
+AC23,IO_L03P_1/A0,1,DUAL,TRUE,AC,23,23
+AC24,IO_L03N_1/A1,1,DUAL,TRUE,AC,23,24
+AC25,IO_L05N_1,1,I/O,TRUE,AC,23,25
+AC26,IO_L06P_1,1,I/O,TRUE,AC,23,26
+AD1,IO_L65P_3,3,I/O,TRUE,AD,24,1
+AD2,IO_L65N_3,3,I/O,TRUE,AD,24,2
+AD3,GND,GND,GND,,AD,24,3
+AD4,IO_L01N_2/M0,2,DUAL,TRUE,AD,24,4
+AD5,IP_2,2,INPUT,,AD,24,5
+AD6,IO_L08N_2,2,I/O,TRUE,AD,24,6
+AD7,IO_L11P_2,2,I/O,TRUE,AD,24,7
+AD8,GND,GND,GND,,AD,24,8
+AD9,IP_2,2,INPUT,,AD,24,9
+AD10,IP_2,2,INPUT,,AD,24,10
+AD11,IO_L23P_2,2,I/O,TRUE,AD,24,11
+AD12,IP_2/VREF_2,2,VREF,,AD,24,12
+AD13,GND,GND,GND,,AD,24,13
+AD14,IO_L29P_2,2,I/O,TRUE,AD,24,14
+AD15,IO_L32P_2/AWAKE,2,PWRMGMT,TRUE,AD,24,15
+AD16,IP_2,2,INPUT,,AD,24,16
+AD17,IO_L33N_2,2,I/O,TRUE,AD,24,17
+AD18,GND,GND,GND,,AD,24,18
+AD19,IO_L40P_2,2,I/O,TRUE,AD,24,19
+AD20,IO_L41P_2,2,I/O,TRUE,AD,24,20
+AD21,IO_L44N_2,2,I/O,TRUE,AD,24,21
+AD22,IO_L45P_2,2,I/O,TRUE,AD,24,22
+AD23,IP_2,2,INPUT,,AD,24,23
+AD24,GND,GND,GND,,AD,24,24
+AD25,IO_L02N_1/LDC0,1,DUAL,TRUE,AD,24,25
+AD26,IO_L05P_1,1,I/O,TRUE,AD,24,26
+AE1,IP_L66P_3,3,INPUT,TRUE,AE,25,1
+AE2,IP_L66N_3/VREF_3,3,VREF,TRUE,AE,25,2
+AE3,IO_L06P_2,2,I/O,TRUE,AE,25,3
+AE4,IO_L07P_2,2,I/O,TRUE,AE,25,4
+AE5,VCCO_2,2,VCCO,,AE,25,5
+AE6,IO_L10N_2,2,I/O,TRUE,AE,25,6
+AE7,IO_L11N_2,2,I/O,TRUE,AE,25,7
+AE8,IO_L18P_2,2,I/O,TRUE,AE,25,8
+AE9,IO_L19P_2/VS1,2,DUAL,TRUE,AE,25,9
+AE10,IO_L22P_2/D7,2,DUAL,TRUE,AE,25,10
+AE11,VCCO_2,2,VCCO,,AE,25,11
+AE12,IO_L24N_2/D4,2,DUAL,TRUE,AE,25,12
+AE13,IO_L26N_2/GCLK15,2,GCLK,TRUE,AE,25,13
+AE14,IO_L28N_2/GCLK3,2,GCLK,TRUE,AE,25,14
+AE15,IO_L32N_2/DOUT,2,DUAL,TRUE,AE,25,15
+AE16,VCCO_2,2,VCCO,,AE,25,16
+AE17,IO_L33P_2,2,I/O,TRUE,AE,25,17
+AE18,IO_L36N_2/D1,2,DUAL,TRUE,AE,25,18
+AE19,IO_L37N_2,2,I/O,TRUE,AE,25,19
+AE20,IO_L39N_2,2,I/O,TRUE,AE,25,20
+AE21,IO_L44P_2,2,I/O,TRUE,AE,25,21
+AE22,VCCO_2,2,VCCO,,AE,25,22
+AE23,IO_L48N_2,2,I/O,TRUE,AE,25,23
+AE24,IO_L52N_2/CCLK,2,DUAL,TRUE,AE,25,24
+AE25,IO_L51N_2,2,I/O,TRUE,AE,25,25
+AE26,IO_L02P_1/LDC1,1,DUAL,TRUE,AE,25,26
+AF1,GND,GND,GND,,AF,26,1
+AF2,IP_2,2,INPUT,,AF,26,2
+AF3,IO_L06N_2,2,I/O,TRUE,AF,26,3
+AF4,IO_L07N_2,2,I/O,TRUE,AF,26,4
+AF5,IO_L10P_2,2,I/O,TRUE,AF,26,5
+AF6,GND,GND,GND,,AF,26,6
+AF7,IP_2,2,INPUT,,AF,26,7
+AF8,IO_L18N_2,2,I/O,TRUE,AF,26,8
+AF9,IO_L19N_2/VS0,2,DUAL,TRUE,AF,26,9
+AF10,IO_L22N_2/D6,2,DUAL,TRUE,AF,26,10
+AF11,GND,GND,GND,,AF,26,11
+AF12,IO_L24P_2/D5,2,DUAL,TRUE,AF,26,12
+AF13,IO_L26P_2/GCLK14,2,GCLK,TRUE,AF,26,13
+AF14,IO_L28P_2/GCLK2,2,GCLK,TRUE,AF,26,14
+AF15,IP_2/VREF_2,2,VREF,,AF,26,15
+AF16,GND,GND,GND,,AF,26,16
+AF17,IP_2/VREF_2,2,VREF,,AF,26,17
+AF18,IO_L36P_2/D2,2,DUAL,TRUE,AF,26,18
+AF19,IO_L37P_2,2,I/O,TRUE,AF,26,19
+AF20,IO_L39P_2,2,I/O,TRUE,AF,26,20
+AF21,GND,GND,GND,,AF,26,21
+AF22,IP_2/VREF_2,2,VREF,,AF,26,22
+AF23,IO_L48P_2,2,I/O,TRUE,AF,26,23
+AF24,IO_L52P_2/D0/DIN/MISO,2,DUAL,TRUE,AF,26,24
+AF25,IO_L51P_2,2,I/O,TRUE,AF,26,25
+AF26,GND,GND,GND,,AF,26,26
+B1,IO_L02N_3,3,I/O,TRUE,B,2,1
+B2,IO_L02P_3,3,I/O,TRUE,B,2,2
+B3,IO_L51N_0,0,I/O,TRUE,B,2,3
+B4,IO_L45N_0,0,I/O,TRUE,B,2,4
+B5,VCCO_0,0,VCCO,,B,2,5
+B6,IO_L41P_0,0,I/O,TRUE,B,2,6
+B7,IO_L42P_0,0,I/O,TRUE,B,2,7
+B8,IO_L38N_0,0,I/O,TRUE,B,2,8
+B9,IO_L36N_0,0,I/O,TRUE,B,2,9
+B10,IO_L33N_0,0,I/O,TRUE,B,2,10
+B11,VCCO_0,0,VCCO,,B,2,11
+B12,IO_L29N_0,0,I/O,TRUE,B,2,12
+B13,IO_L28P_0/GCLK10,0,GCLK,TRUE,B,2,13
+B14,IO_L26P_0/GCLK6,0,GCLK,TRUE,B,2,14
+B15,IO_L23P_0,0,I/O,TRUE,B,2,15
+B16,VCCO_0,0,VCCO,,B,2,16
+B17,IO_L19N_0,0,I/O,TRUE,B,2,17
+B18,IO_L18P_0,0,I/O,TRUE,B,2,18
+B19,IO_L15P_0,0,I/O,TRUE,B,2,19
+B20,IO_L14P_0/VREF_0,0,VREF,TRUE,B,2,20
+B21,IO_L09N_0,0,I/O,TRUE,B,2,21
+B22,VCCO_0,0,VCCO,,B,2,22
+B23,IO_L07P_0,0,I/O,TRUE,B,2,23
+B24,IP_0,0,INPUT,,B,2,24
+B25,IP_L65N_1,1,INPUT,TRUE,B,2,25
+B26,IP_L65P_1/VREF_1,1,VREF,TRUE,B,2,26
+C1,IP_L04N_3/VREF_3,3,VREF,TRUE,C,3,1
+C2,IP_L04P_3,3,INPUT,TRUE,C,3,2
+C3,GND,GND,GND,,C,3,3
+C4,IP_0,0,INPUT,,C,3,4
+C5,IO_L44P_0,0,I/O,TRUE,C,3,5
+C6,IO_L41N_0,0,I/O,TRUE,C,3,6
+C7,IO_L42N_0,0,I/O,TRUE,C,3,7
+C8,IO_L40P_0,0,I/O,TRUE,C,3,8
+C9,GND,GND,GND,,C,3,9
+C10,IO_L34P_0,0,I/O,TRUE,C,3,10
+C11,IO_L32P_0,0,I/O,TRUE,C,3,11
+C12,IO_L30N_0,0,I/O,TRUE,C,3,12
+C13,IO_L28N_0/GCLK11,0,GCLK,TRUE,C,3,13
+C14,GND,GND,GND,,C,3,14
+C15,IO_L22N_0,0,I/O,TRUE,C,3,15
+C16,IO_L21N_0,0,I/O,TRUE,C,3,16
+C17,IO_L19P_0,0,I/O,TRUE,C,3,17
+C18,IO_L17N_0,0,I/O,TRUE,C,3,18
+C19,GND,GND,GND,,C,3,19
+C20,IO_L11N_0,0,I/O,TRUE,C,3,20
+C21,IO_L09P_0,0,I/O,TRUE,C,3,21
+C22,IO_L05N_0,0,I/O,TRUE,C,3,22
+C23,IO_L06N_0,0,I/O,TRUE,C,3,23
+C24,GND,GND,GND,,C,3,24
+C25,IO_L63N_1/A23,1,DUAL,TRUE,C,3,25
+C26,IO_L63P_1/A22,1,DUAL,TRUE,C,3,26
+D1,IP_L08N_3,3,INPUT,TRUE,D,4,1
+D2,IP_L08P_3,3,INPUT,TRUE,D,4,2
+D3,IO_L06P_3,3,I/O,TRUE,D,4,3
+D4,TMS,VCCAUX,JTAG,,D,4,4
+D5,IP_0,0,INPUT,,D,4,5
+D6,IO_L44N_0,0,I/O,TRUE,D,4,6
+D7,IP_0/VREF_0,0,VREF,,D,4,7
+D8,IO_L40N_0,0,I/O,TRUE,D,4,8
+D9,IO_L37N_0,0,I/O,TRUE,D,4,9
+D10,IO_L34N_0,0,I/O,TRUE,D,4,10
+D11,IO_L32N_0/VREF_0,0,VREF,TRUE,D,4,11
+D12,IP_0,0,INPUT,,D,4,12
+D13,IO_L30P_0,0,I/O,TRUE,D,4,13
+D14,IP_0/VREF_0,0,VREF,,D,4,14
+D15,IP_0,0,INPUT,,D,4,15
+D16,IO_L22P_0,0,I/O,TRUE,D,4,16
+D17,IO_L21P_0,0,I/O,TRUE,D,4,17
+D18,IO_L17P_0,0,I/O,TRUE,D,4,18
+D19,IP_0,0,INPUT,,D,4,19
+D20,IO_L11P_0,0,I/O,TRUE,D,4,20
+D21,IO_L10N_0,0,I/O,TRUE,D,4,21
+D22,IO_L05P_0,0,I/O,TRUE,D,4,22
+D23,IO_L06P_0,0,I/O,TRUE,D,4,23
+D24,IO_L61N_1,1,I/O,TRUE,D,4,24
+D25,IO_L61P_1,1,I/O,TRUE,D,4,25
+D26,IO_L60N_1,1,I/O,TRUE,D,4,26
+E1,IO_L11P_3,3,I/O,TRUE,E,5,1
+E2,VCCO_3,3,VCCO,,E,5,2
+E3,IO_L07P_3,3,I/O,TRUE,E,5,3
+E4,IO_L06N_3,3,I/O,TRUE,E,5,4
+E5,VCCAUX,VCCAUX,VCCAUX,,E,5,5
+E6,IP_0,0,INPUT,,E,5,6
+E7,IO_L48N_0,0,I/O,TRUE,E,5,7
+E8,VCCO_0,0,VCCO,,E,5,8
+E9,IP_0,0,INPUT,,E,5,9
+E10,IO_L37P_0,0,I/O,TRUE,E,5,10
+E11,IP_0,0,INPUT,,E,5,11
+E12,IO_L31P_0,0,I/O,TRUE,E,5,12
+E13,VCCO_0,0,VCCO,,E,5,13
+E14,IO_L24P_0,0,I/O,TRUE,E,5,14
+E15,IO_L20N_0/VREF_0,0,VREF,TRUE,E,5,15
+E16,VCCAUX,VCCAUX,VCCAUX,,E,5,16
+E17,IO_L13N_0,0,I/O,TRUE,E,5,17
+E18,IP_0,0,INPUT,,E,5,18
+E19,VCCO_0,0,VCCO,,E,5,19
+E20,IP_0,0,INPUT,,E,5,20
+E21,IO_L10P_0,0,I/O,TRUE,E,5,21
+E22,VCCAUX,VCCAUX,VCCAUX,,E,5,22
+E23,TDO,VCCAUX,JTAG,,E,5,23
+E24,IO_L56P_1,1,I/O,TRUE,E,5,24
+E25,VCCO_1,1,VCCO,,E,5,25
+E26,IO_L60P_1,1,I/O,TRUE,E,5,26
+F1,GND,GND,GND,,F,6,1
+F2,IO_L11N_3,3,I/O,TRUE,F,6,2
+F3,IO_L14N_3,3,I/O,TRUE,F,6,3
+F4,IO_L07N_3,3,I/O,TRUE,F,6,4
+F5,IO_L09P_3,3,I/O,TRUE,F,6,5
+F6,GND,GND,GND,,F,6,6
+F7,IO_L48P_0,0,I/O,TRUE,F,6,7
+F8,IO_L52P_0/VREF_0,0,VREF,TRUE,F,6,8
+F9,IP_0,0,INPUT,,F,6,9
+F10,IP_0,0,INPUT,,F,6,10
+F11,GND,GND,GND,,F,6,11
+F12,IO_L31N_0,0,I/O,TRUE,F,6,12
+F13,IO_L27P_0/GCLK8,0,GCLK,TRUE,F,6,13
+F14,IO_L24N_0,0,I/O,TRUE,F,6,14
+F15,IO_L20P_0,0,I/O,TRUE,F,6,15
+F16,GND,GND,GND,,F,6,16
+F17,IO_L13P_0,0,I/O,TRUE,F,6,17
+F18,IP_0,0,INPUT,,F,6,18
+F19,IO_L02N_0,0,I/O,TRUE,F,6,19
+F20,IO_L01N_0,0,I/O,TRUE,F,6,20
+F21,GND,GND,GND,,F,6,21
+F22,IO_L58P_1/VREF_1,1,VREF,TRUE,F,6,22
+F23,IO_L56N_1,1,I/O,TRUE,F,6,23
+F24,IO_L54N_1,1,I/O,TRUE,F,6,24
+F25,IO_L54P_1,1,I/O,TRUE,F,6,25
+F26,GND,GND,GND,,F,6,26
+G1,IP_L16N_3,3,INPUT,TRUE,G,7,1
+G2,IP_L16P_3,3,INPUT,TRUE,G,7,2
+G3,IO_L14P_3,3,I/O,TRUE,G,7,3
+G4,IO_L09N_3,3,I/O,TRUE,G,7,4
+G5,IP_L12P_3,3,INPUT,TRUE,G,7,5
+G6,IO_L03P_3,3,I/O,TRUE,G,7,6
+G7,TDI,VCCAUX,JTAG,,G,7,7
+G8,IO_L52N_0/PUDC_B,0,DUAL,TRUE,G,7,8
+G9,IO_L47P_0,0,I/O,TRUE,G,7,9
+G10,IO_L46P_0,0,I/O,TRUE,G,7,10
+G11,IP_0/VREF_0,0,VREF,,G,7,11
+G12,IO_L35P_0,0,I/O,TRUE,G,7,12
+G13,IO_L27N_0/GCLK9,0,GCLK,TRUE,G,7,13
+G14,IP_0,0,INPUT,,G,7,14
+G15,IO_L16P_0,0,I/O,TRUE,G,7,15
+G16,IP_0,0,INPUT,,G,7,16
+G17,IO_L08N_0,0,I/O,TRUE,G,7,17
+G18,IP_0,0,INPUT,,G,7,18
+G19,IO_L02P_0/VREF_0,0,VREF,TRUE,G,7,19
+G20,IO_L01P_0,0,I/O,TRUE,G,7,20
+G21,IO_L64N_1/A25,1,DUAL,TRUE,G,7,21
+G22,IO_L58N_1,1,I/O,TRUE,G,7,22
+G23,IO_L51P_1,1,I/O,TRUE,G,7,23
+G24,IO_L51N_1,1,I/O,TRUE,G,7,24
+G25,IP_L52N_1/VREF_1,1,VREF,TRUE,G,7,25
+G26,IP_L52P_1,1,INPUT,TRUE,G,7,26
+H1,IO_L17N_3,3,I/O,TRUE,H,8,1
+H2,IO_L17P_3,3,I/O,TRUE,H,8,2
+H3,GND,GND,GND,,H,8,3
+H4,IP_L12N_3/VREF_3,3,VREF,TRUE,H,8,4
+H5,VCCO_3,3,VCCO,,H,8,5
+H6,IO_L10N_3,3,I/O,TRUE,H,8,6
+H7,IO_L03N_3,3,I/O,TRUE,H,8,7
+H8,GND,GND,GND,,H,8,8
+H9,IO_L47N_0,0,I/O,TRUE,H,8,9
+H10,IO_L46N_0,0,I/O,TRUE,H,8,10
+H11,VCCO_0,0,VCCO,,H,8,11
+H12,IO_L35N_0,0,I/O,TRUE,H,8,12
+H13,IP_0,0,INPUT,,H,8,13
+H14,GND,GND,GND,,H,8,14
+H15,IO_L16N_0,0,I/O,TRUE,H,8,15
+H16,VCCO_0,0,VCCO,,H,8,16
+H17,IO_L08P_0,0,I/O,TRUE,H,8,17
+H18,IP_0,0,INPUT,,H,8,18
+H19,GND,GND,GND,,H,8,19
+H20,IO_L64P_1/A24,1,DUAL,TRUE,H,8,20
+H21,IO_L62N_1/A21,1,DUAL,TRUE,H,8,21
+H22,VCCO_1,1,VCCO,,H,8,22
+H23,IP_L48P_1,1,INPUT,TRUE,H,8,23
+H24,IP_L48N_1,1,INPUT,TRUE,H,8,24
+H25,IP_L44N_1,1,INPUT,TRUE,H,8,25
+H26,IP_L44P_1/VREF_1,1,VREF,TRUE,H,8,26
+J1,IP_L24P_3,3,INPUT,TRUE,J,9,1
+J2,IP_L20N_3/VREF_3,3,VREF,TRUE,J,9,2
+J3,IP_L20P_3,3,INPUT,TRUE,J,9,3
+J4,IO_L19N_3,3,I/O,TRUE,J,9,4
+J5,IO_L19P_3,3,I/O,TRUE,J,9,5
+J6,IO_L13N_3,3,I/O,TRUE,J,9,6
+J7,IO_L10P_3,3,I/O,TRUE,J,9,7
+J8,IO_L01P_3,3,I/O,TRUE,J,9,8
+J9,IO_L01N_3,3,I/O,TRUE,J,9,9
+J10,IP_0,0,INPUT,,J,9,10
+J11,IO_L43P_0,0,I/O,TRUE,J,9,11
+J12,IO_L39P_0,0,I/O,TRUE,J,9,12
+J13,IP_0,0,INPUT,,J,9,13
+J14,IO_L25N_0/GCLK5,0,GCLK,TRUE,J,9,14
+J15,IP_0,0,INPUT,,J,9,15
+J16,IO_L12P_0,0,I/O,TRUE,J,9,16
+J17,IP_0/VREF_0,0,VREF,,J,9,17
+J18,VCCAUX,VCCAUX,VCCAUX,,J,9,18
+J19,IO_L59P_1,1,I/O,TRUE,J,9,19
+J20,IO_L59N_1,1,I/O,TRUE,J,9,20
+J21,IO_L62P_1/A20,1,DUAL,TRUE,J,9,21
+J22,IO_L49N_1,1,I/O,TRUE,J,9,22
+J23,IO_L49P_1,1,I/O,TRUE,J,9,23
+J24,GND,GND,GND,,J,9,24
+J25,IO_L43N_1/A19,1,DUAL,TRUE,J,9,25
+J26,IO_L43P_1/A18,1,DUAL,TRUE,J,9,26
+K1,IP_L24N_3,3,INPUT,TRUE,K,10,1
+K2,IO_L23N_3,3,I/O,TRUE,K,10,2
+K3,IO_L23P_3,3,I/O,TRUE,K,10,3
+K4,IO_L22N_3,3,I/O,TRUE,K,10,4
+K5,IO_L22P_3,3,I/O,TRUE,K,10,5
+K6,IO_L18P_3,3,I/O,TRUE,K,10,6
+K7,IO_L13P_3,3,I/O,TRUE,K,10,7
+K8,IO_L05N_3,3,I/O,TRUE,K,10,8
+K9,IO_L05P_3,3,I/O,TRUE,K,10,9
+K10,GND,GND,GND,,K,10,10
+K11,IO_L43N_0,0,I/O,TRUE,K,10,11
+K12,IO_L39N_0,0,I/O,TRUE,K,10,12
+K13,VCCAUX,VCCAUX,VCCAUX,,K,10,13
+K14,IO_L25P_0/GCLK4,0,GCLK,TRUE,K,10,14
+K15,VCCINT,VCCINT,VCCINT,,K,10,15
+K16,IO_L12N_0,0,I/O,TRUE,K,10,16
+K17,GND,GND,GND,,K,10,17
+K18,IO_L57N_1,1,I/O,TRUE,K,10,18
+K19,IO_L57P_1,1,I/O,TRUE,K,10,19
+K20,IO_L53N_1,1,I/O,TRUE,K,10,20
+K21,IO_L50N_1,1,I/O,TRUE,K,10,21
+K22,IO_L46N_1,1,I/O,TRUE,K,10,22
+K23,IO_L46P_1,1,I/O,TRUE,K,10,23
+K24,IP_L40P_1,1,INPUT,TRUE,K,10,24
+K25,IO_L41P_1,1,I/O,TRUE,K,10,25
+K26,IO_L41N_1,1,I/O,TRUE,K,10,26
+L1,GND,GND,GND,,L,11,1
+L2,VCCO_3,3,VCCO,,L,11,2
+L3,IO_L25N_3,3,I/O,TRUE,L,11,3
+L4,IO_L25P_3,3,I/O,TRUE,L,11,4
+L5,VCCAUX,VCCAUX,VCCAUX,,L,11,5
+L6,GND,GND,GND,,L,11,6
+L7,IO_L18N_3,3,I/O,TRUE,L,11,7
+L8,VCCO_3,3,VCCO,,L,11,8
+L9,IO_L15N_3,3,I/O,TRUE,L,11,9
+L10,IO_L15P_3,3,I/O,TRUE,L,11,10
+L11,GND,GND,GND,,L,11,11
+L12,VCCINT,VCCINT,VCCINT,,L,11,12
+L13,GND,GND,GND,,L,11,13
+L14,VCCINT,VCCINT,VCCINT,,L,11,14
+L15,GND,GND,GND,,L,11,15
+L16,VCCINT,VCCINT,VCCINT,,L,11,16
+L17,IO_L55N_1,1,I/O,TRUE,L,11,17
+L18,IO_L55P_1,1,I/O,TRUE,L,11,18
+L19,VCCO_1,1,VCCO,,L,11,19
+L20,IO_L53P_1,1,I/O,TRUE,L,11,20
+L21,GND,GND,GND,,L,11,21
+L22,IO_L50P_1,1,I/O,TRUE,L,11,22
+L23,IP_L40N_1,1,INPUT,TRUE,L,11,23
+L24,IO_L38P_1/A12,1,DUAL,TRUE,L,11,24
+L25,VCCO_1,1,VCCO,,L,11,25
+L26,GND,GND,GND,,L,11,26
+M1,IO_L29N_3/VREF_3,3,VREF,TRUE,M,12,1
+M2,IO_L29P_3,3,I/O,TRUE,M,12,2
+M3,IO_L27N_3,3,I/O,TRUE,M,12,3
+M4,IO_L27P_3,3,I/O,TRUE,M,12,4
+M5,IO_L28P_3,3,I/O,TRUE,M,12,5
+M6,IO_L28N_3,3,I/O,TRUE,M,12,6
+M7,IO_L26N_3,3,I/O,TRUE,M,12,7
+M8,IO_L26P_3,3,I/O,TRUE,M,12,8
+M9,IO_L21N_3,3,I/O,TRUE,M,12,9
+M10,IO_L21P_3,3,I/O,TRUE,M,12,10
+M11,VCCINT,VCCINT,VCCINT,,M,12,11
+M12,GND,GND,GND,,M,12,12
+M13,VCCINT,VCCINT,VCCINT,,M,12,13
+M14,GND,GND,GND,,M,12,14
+M15,VCCINT,VCCINT,VCCINT,,M,12,15
+M16,GND,GND,GND,,M,12,16
+M17,VCCINT,VCCINT,VCCINT,,M,12,17
+M18,IO_L47N_1,1,I/O,TRUE,M,12,18
+M19,IO_L47P_1,1,I/O,TRUE,M,12,19
+M20,IO_L42N_1/A17,1,DUAL,TRUE,M,12,20
+M21,IO_L45P_1,1,I/O,TRUE,M,12,21
+M22,IO_L45N_1,1,I/O,TRUE,M,12,22
+M23,IO_L38N_1/A13,1,DUAL,TRUE,M,12,23
+M24,IP_L36P_1/VREF_1,1,VREF,TRUE,M,12,24
+M25,IO_L35N_1/A11,1,DUAL,TRUE,M,12,25
+M26,IO_L35P_1/A10,1,DUAL,TRUE,M,12,26
+N1,IO_L31P_3,3,I/O,TRUE,N,13,1
+N2,IO_L31N_3,3,I/O,TRUE,N,13,2
+N3,GND,GND,GND,,N,13,3
+N4,IO_L30N_3,3,I/O,TRUE,N,13,4
+N5,IO_L30P_3,3,I/O,TRUE,N,13,5
+N6,IO_L32P_3/LHCLK0,3,LHCLK,TRUE,N,13,6
+N7,IO_L32N_3/LHCLK1,3,LHCLK,TRUE,N,13,7
+N8,GND,GND,GND,,N,13,8
+N9,IO_L35P_3/TRDY2/LHCLK6,3,LHCLK,TRUE,N,13,9
+N10,VCCAUX,VCCAUX,VCCAUX,,N,13,10
+N11,GND,GND,GND,,N,13,11
+N12,VCCINT,VCCINT,VCCINT,,N,13,12
+N13,VCCINT,VCCINT,VCCINT,,N,13,13
+N14,VCCINT,VCCINT,VCCINT,,N,13,14
+N15,GND,GND,GND,,N,13,15
+N16,VCCINT,VCCINT,VCCINT,,N,13,16
+N17,IO_L39N_1/A15,1,DUAL,TRUE,N,13,17
+N18,IO_L39P_1/A14,1,DUAL,TRUE,N,13,18
+N19,IO_L34N_1/RHCLK7,1,RHCLK,TRUE,N,13,19
+N20,IO_L42P_1/A16,1,DUAL,TRUE,N,13,20
+N21,IO_L37N_1,1,I/O,TRUE,N,13,21
+N22,VCCO_1,1,VCCO,,N,13,22
+N23,IP_L36N_1,1,INPUT,TRUE,N,13,23
+N24,IO_L33N_1/RHCLK5,1,RHCLK,TRUE,N,13,24
+N25,IP_L32N_1,1,INPUT,TRUE,N,13,25
+N26,IP_L32P_1,1,INPUT,TRUE,N,13,26
+P1,IO_L33P_3/LHCLK2,3,LHCLK,TRUE,P,14,1
+P2,IO_L33N_3/IRDY2/LHCLK3,3,LHCLK,TRUE,P,14,2
+P3,IO_L34N_3/LHCLK5,3,LHCLK,TRUE,P,14,3
+P4,IO_L34P_3/LHCLK4,3,LHCLK,TRUE,P,14,4
+P5,VCCO_3,3,VCCO,,P,14,5
+P6,IO_L39N_3,3,I/O,TRUE,P,14,6
+P7,IO_L39P_3,3,I/O,TRUE,P,14,7
+P8,IO_L41P_3,3,I/O,TRUE,P,14,8
+P9,IO_L41N_3,3,I/O,TRUE,P,14,9
+P10,IO_L35N_3/LHCLK7,3,LHCLK,TRUE,P,14,10
+P11,VCCINT,VCCINT,VCCINT,,P,14,11
+P12,GND,GND,GND,,P,14,12
+P13,VCCINT,VCCINT,VCCINT,,P,14,13
+P14,VCCINT,VCCINT,VCCINT,,P,14,14
+P15,VCCINT,VCCINT,VCCINT,,P,14,15
+P16,GND,GND,GND,,P,14,16
+P17,VCCAUX,VCCAUX,VCCAUX,,P,14,17
+P18,IO_L34P_1/IRDY1/RHCLK6,1,RHCLK,TRUE,P,14,18
+P19,GND,GND,GND,,P,14,19
+P20,IO_L30N_1/RHCLK1,1,RHCLK,TRUE,P,14,20
+P21,IO_L30P_1/RHCLK0,1,RHCLK,TRUE,P,14,21
+P22,IO_L37P_1,1,I/O,TRUE,P,14,22
+P23,IO_L33P_1/RHCLK4,1,RHCLK,TRUE,P,14,23
+P24,GND,GND,GND,,P,14,24
+P25,IO_L31N_1/TRDY1/RHCLK3,1,RHCLK,TRUE,P,14,25
+P26,IO_L31P_1/RHCLK2,1,RHCLK,TRUE,P,14,26
+R1,IO_L36P_3/VREF_3,3,VREF,TRUE,R,15,1
+R2,IO_L36N_3,3,I/O,TRUE,R,15,2
+R3,IO_L37P_3,3,I/O,TRUE,R,15,3
+R4,IO_L37N_3,3,I/O,TRUE,R,15,4
+R5,IO_L40P_3,3,I/O,TRUE,R,15,5
+R6,IO_L40N_3,3,I/O,TRUE,R,15,6
+R7,IO_L45N_3,3,I/O,TRUE,R,15,7
+R8,IO_L45P_3,3,I/O,TRUE,R,15,8
+R9,IO_L43N_3,3,I/O,TRUE,R,15,9
+R10,IO_L43P_3/VREF_3,3,VREF,TRUE,R,15,10
+R11,GND,GND,GND,,R,15,11
+R12,VCCINT,VCCINT,VCCINT,,R,15,12
+R13,GND,GND,GND,,R,15,13
+R14,VCCINT,VCCINT,VCCINT,,R,15,14
+R15,GND,GND,GND,,R,15,15
+R16,VCCINT,VCCINT,VCCINT,,R,15,16
+R17,IO_L27N_1/A7,1,DUAL,TRUE,R,15,17
+R18,IO_L27P_1/A6,1,DUAL,TRUE,R,15,18
+R19,IO_L22P_1,1,I/O,TRUE,R,15,19
+R20,IO_L22N_1,1,I/O,TRUE,R,15,20
+R21,IO_L25P_1/A2,1,DUAL,TRUE,R,15,21
+R22,IO_L25N_1/A3,1,DUAL,TRUE,R,15,22
+R23,IP_L28P_1/VREF_1,1,VREF,TRUE,R,15,23
+R24,IP_L28N_1,1,INPUT,TRUE,R,15,24
+R25,IO_L29P_1/A8,1,DUAL,TRUE,R,15,25
+R26,IO_L29N_1/A9,1,DUAL,TRUE,R,15,26
+T1,GND,GND,GND,,T,16,1
+T2,VCCO_3,3,VCCO,,T,16,2
+T3,IO_L38P_3,3,I/O,TRUE,T,16,3
+T4,IO_L38N_3,3,I/O,TRUE,T,16,4
+T5,IO_L42P_3,3,I/O,TRUE,T,16,5
+T6,GND,GND,GND,,T,16,6
+T7,IO_L51P_3,3,I/O,TRUE,T,16,7
+T8,VCCO_3,3,VCCO,,T,16,8
+T9,IO_L48N_3,3,I/O,TRUE,T,16,9
+T10,IO_L48P_3,3,I/O,TRUE,T,16,10
+T11,VCCINT,VCCINT,VCCINT,,T,16,11
+T12,GND,GND,GND,,T,16,12
+T13,VCCINT,VCCINT,VCCINT,,T,16,13
+T14,GND,GND,GND,,T,16,14
+T15,VCCINT,VCCINT,VCCINT,,T,16,15
+T16,GND,GND,GND,,T,16,16
+T17,IO_L17N_1,1,I/O,TRUE,T,16,17
+T18,IO_L17P_1,1,I/O,TRUE,T,16,18
+T19,VCCO_1,1,VCCO,,T,16,19
+T20,IO_L14N_1,1,I/O,TRUE,T,16,20
+T21,GND,GND,GND,,T,16,21
+T22,VCCAUX,VCCAUX,VCCAUX,,T,16,22
+T23,IO_L26P_1/A4,1,DUAL,TRUE,T,16,23
+T24,IO_L26N_1/A5,1,DUAL,TRUE,T,16,24
+T25,VCCO_1,1,VCCO,,T,16,25
+T26,GND,GND,GND,,T,16,26
+U1,IO_L44P_3,3,I/O,TRUE,U,17,1
+U2,IO_L44N_3,3,I/O,TRUE,U,17,2
+U3,IP_L46P_3,3,INPUT,TRUE,U,17,3
+U4,IO_L42N_3,3,I/O,TRUE,U,17,4
+U5,IO_L49P_3,3,I/O,TRUE,U,17,5
+U6,IO_L51N_3,3,I/O,TRUE,U,17,6
+U7,IO_L56P_3,3,I/O,TRUE,U,17,7
+U8,IO_L56N_3,3,I/O,TRUE,U,17,8
+U9,IO_L61P_3,3,I/O,TRUE,U,17,9
+U10,GND,GND,GND,,U,17,10
+U11,IO_L13N_2,2,I/O,TRUE,U,17,11
+U12,VCCINT,VCCINT,VCCINT,,U,17,12
+U13,GND,GND,GND,,U,17,13
+U14,VCCAUX,VCCAUX,VCCAUX,,U,17,14
+U15,IO_L35N_2,2,I/O,TRUE,U,17,15
+U16,IO_L42N_2,2,I/O,TRUE,U,17,16
+U17,GND,GND,GND,,U,17,17
+U18,IO_L12N_1,1,I/O,TRUE,U,17,18
+U19,IO_L12P_1,1,I/O,TRUE,U,17,19
+U20,IO_L10N_1,1,I/O,TRUE,U,17,20
+U21,IO_L14P_1,1,I/O,TRUE,U,17,21
+U22,IO_L21N_1,1,I/O,TRUE,U,17,22
+U23,IO_L23P_1,1,I/O,TRUE,U,17,23
+U24,IO_L23N_1/VREF_1,1,VREF,TRUE,U,17,24
+U25,IP_L24P_1,1,INPUT,TRUE,U,17,25
+U26,IP_L24N_1/VREF_1,1,VREF,TRUE,U,17,26
+V1,IO_L47P_3,3,I/O,TRUE,V,18,1
+V2,IO_L47N_3,3,I/O,TRUE,V,18,2
+V3,GND,GND,GND,,V,18,3
+V4,IP_L46N_3,3,INPUT,TRUE,V,18,4
+V5,IO_L49N_3,3,I/O,TRUE,V,18,5
+V6,IO_L59N_3,3,I/O,TRUE,V,18,6
+V7,IO_L59P_3,3,I/O,TRUE,V,18,7
+V8,IO_L61N_3,3,I/O,TRUE,V,18,8
+V9,VCCAUX,VCCAUX,VCCAUX,,V,18,9
+V10,IO_L09P_2,2,I/O,TRUE,V,18,10
+V11,IO_L13P_2,2,I/O,TRUE,V,18,11
+V12,IO_L16P_2,2,I/O,TRUE,V,18,12
+V13,IO_L20P_2,2,I/O,TRUE,V,18,13
+V14,IO_L31P_2,2,I/O,TRUE,V,18,14
+V15,IO_L35P_2,2,I/O,TRUE,V,18,15
+V16,IO_L42P_2,2,I/O,TRUE,V,18,16
+V17,IO_L46N_2,2,I/O,TRUE,V,18,17
+V18,IO_L08P_1,1,I/O,TRUE,V,18,18
+V19,IO_L08N_1,1,I/O,TRUE,V,18,19
+V20,SUSPEND,1,PWRMGMT,,V,18,20
+V21,IO_L10P_1,1,I/O,TRUE,V,18,21
+V22,IO_L18N_1,1,I/O,TRUE,V,18,22
+V23,IO_L21P_1,1,I/O,TRUE,V,18,23
+V24,IO_L19P_1,1,I/O,TRUE,V,18,24
+V25,IO_L19N_1,1,I/O,TRUE,V,18,25
+V26,IP_L20N_1/VREF_1,1,VREF,TRUE,V,18,26
+W1,IP_L50P_3,3,INPUT,TRUE,W,19,1
+W2,IP_L50N_3/VREF_3,3,VREF,TRUE,W,19,2
+W3,IO_L52P_3,3,I/O,TRUE,W,19,3
+W4,IO_L52N_3,3,I/O,TRUE,W,19,4
+W5,VCCO_3,3,VCCO,,W,19,5
+W6,IO_L63N_3,3,I/O,TRUE,W,19,6
+W7,IO_L63P_3,3,I/O,TRUE,W,19,7
+W8,GND,GND,GND,,W,19,8
+W9,IO_L05P_2,2,I/O,TRUE,W,19,9
+W10,IO_L09N_2,2,I/O,TRUE,W,19,10
+W11,VCCO_2,2,VCCO,,W,19,11
+W12,IO_L16N_2,2,I/O,TRUE,W,19,12
+W13,IO_L20N_2,2,I/O,TRUE,W,19,13
+W14,GND,GND,GND,,W,19,14
+W15,IO_L31N_2,2,I/O,TRUE,W,19,15
+W16,VCCO_2,2,VCCO,,W,19,16
+W17,IO_L46P_2,2,I/O,TRUE,W,19,17
+W18,IP_2,2,INPUT,,W,19,18
+W19,GND,GND,GND,,W,19,19
+W20,IO_L04P_1,1,I/O,TRUE,W,19,20
+W21,IO_L04N_1,1,I/O,TRUE,W,19,21
+W22,VCCO_1,1,VCCO,,W,19,22
+W23,IO_L18P_1,1,I/O,TRUE,W,19,23
+W24,GND,GND,GND,,W,19,24
+W25,IP_L16P_1,1,INPUT,TRUE,W,19,25
+W26,IP_L20P_1,1,INPUT,TRUE,W,19,26
+Y1,IO_L53P_3,3,I/O,TRUE,Y,20,1
+Y2,IO_L53N_3,3,I/O,TRUE,Y,20,2
+Y3,IP_L54P_3,3,INPUT,TRUE,Y,20,3
+Y4,IP_L54N_3,3,INPUT,TRUE,Y,20,4
+Y5,IO_L57P_3,3,I/O,TRUE,Y,20,5
+Y6,IO_L57N_3,3,I/O,TRUE,Y,20,6
+Y7,IO_L02P_2/M2,2,DUAL,TRUE,Y,20,7
+Y8,IP_2,2,INPUT,,Y,20,8
+Y9,IO_L05N_2,2,I/O,TRUE,Y,20,9
+Y10,IO_L12P_2,2,I/O,TRUE,Y,20,10
+Y11,IP_2,2,INPUT,,Y,20,11
+Y12,IO_L17P_2/RDWR_B,2,DUAL,TRUE,Y,20,12
+Y13,IO_L25N_2/GCLK13,2,GCLK,TRUE,Y,20,13
+Y14,IO_L27P_2/GCLK0,2,GCLK,TRUE,Y,20,14
+Y15,IO_L34N_2/D3,2,DUAL,TRUE,Y,20,15
+Y16,IP_2/VREF_2,2,VREF,,Y,20,16
+Y17,IO_L43N_2,2,I/O,TRUE,Y,20,17
+Y18,IP_2,2,INPUT,,Y,20,18
+Y19,IP_2/VREF_2,2,VREF,,Y,20,19
+Y20,IO_L01P_1/HDC,1,DUAL,TRUE,Y,20,20
+Y21,IO_L01N_1/LDC2,1,DUAL,TRUE,Y,20,21
+Y22,IO_L13P_1,1,I/O,TRUE,Y,20,22
+Y23,IO_L13N_1,1,I/O,TRUE,Y,20,23
+Y24,IO_L15P_1,1,I/O,TRUE,Y,20,24
+Y25,IO_L15N_1,1,I/O,TRUE,Y,20,25
+Y26,IP_L16N_1,1,INPUT,TRUE,Y,20,26
Added: usrp-hw/trunk/sym/generated/XC3SD3400AFG676.csv
===================================================================
--- usrp-hw/trunk/sym/generated/XC3SD3400AFG676.csv
(rev 0)
+++ usrp-hw/trunk/sym/generated/XC3SD3400AFG676.csv 2008-12-23 08:13:43 UTC
(rev 10159)
@@ -0,0 +1,677 @@
+PIN,XC3SD3400AFG676_PIN,XC3SD3400AFG676_BANK,TYPE,DIFF_PAIR,ROW,ROW_#,COLUMN
+A1,GND,GND,GND,,A,1,1
+A2,PROG_B,VCCAUX,CONFIG,,A,1,2
+A3,IO_L51P_0,0,I/O,TRUE,A,1,3
+A4,IO_L45P_0,0,I/O,TRUE,A,1,4
+A5,GND,GND,GND,,A,1,5
+A6,GND,GND,GND,,A,1,6
+A7,VCCO_0,0,VCCO,,A,1,7
+A8,IO_L38P_0,0,I/O,TRUE,A,1,8
+A9,IO_L36P_0,0,I/O,TRUE,A,1,9
+A10,IO_L33P_0,0,I/O,TRUE,A,1,10
+A11,GND,GND,GND,,A,1,11
+A12,IO_L29P_0,0,I/O,TRUE,A,1,12
+A13,IP_0,0,INPUT,,A,1,13
+A14,IO_L26N_0/GCLK7,0,GCLK,TRUE,A,1,14
+A15,IO_L23N_0,0,I/O,TRUE,A,1,15
+A16,GND,GND,GND,,A,1,16
+A17,IP_0,0,INPUT,,A,1,17
+A18,IO_L18N_0,0,I/O,TRUE,A,1,18
+A19,IO_L15N_0,0,I/O,TRUE,A,1,19
+A20,IO_L14N_0,0,I/O,TRUE,A,1,20
+A21,GND,GND,GND,,A,1,21
+A22,IO_L07N_0,0,I/O,TRUE,A,1,22
+A23,GND,GND,GND,,A,1,23
+A24,VCCAUX,VCCAUX,VCCAUX,,A,1,24
+A25,TCK,VCCAUX,JTAG,,A,1,25
+A26,GND,GND,GND,,A,1,26
+AA1,GND,GND,GND,,AA,21,1
+AA2,IO_L55P_3,3,I/O,TRUE,AA,21,2
+AA3,IO_L55N_3,3,I/O,TRUE,AA,21,3
+AA4,GND,GND,GND,,AA,21,4
+AA5,IP_3/VREF_3,3,VREF,,AA,21,5
+AA6,GND,GND,GND,,AA,21,6
+AA7,IO_L02N_2/CSO_B,2,DUAL,TRUE,AA,21,7
+AA8,VCCINT,VCCINT,VCCINT,,AA,21,8
+AA9,IP_2/VREF_2,2,VREF,,AA,21,9
+AA10,IO_L12N_2,2,I/O,TRUE,AA,21,10
+AA11,GND,GND,GND,,AA,21,11
+AA12,IO_L17N_2/VS2,2,DUAL,TRUE,AA,21,12
+AA13,IO_L25P_2/GCLK12,2,GCLK,TRUE,AA,21,13
+AA14,IO_L27N_2/GCLK1,2,GCLK,TRUE,AA,21,14
+AA15,IO_L34P_2/INIT_B,2,DUAL,TRUE,AA,21,15
+AA16,GND,GND,GND,,AA,21,16
+AA17,IO_L43P_2,2,I/O,TRUE,AA,21,17
+AA18,IO_L47N_2,2,I/O,TRUE,AA,21,18
+AA19,GND,GND,GND,,AA,21,19
+AA20,IP_2/VREF_2,2,VREF,,AA,21,20
+AA21,GND,GND,GND,,AA,21,21
+AA22,IO_L09P_1,1,I/O,TRUE,AA,21,22
+AA23,IO_L09N_1,1,I/O,TRUE,AA,21,23
+AA24,IO_L11P_1,1,I/O,TRUE,AA,21,24
+AA25,IO_L11N_1,1,I/O,TRUE,AA,21,25
+AA26,GND,GND,GND,,AA,21,26
+AB1,IO_L60P_3,3,I/O,TRUE,AB,22,1
+AB2,VCCO_3,3,VCCO,,AB,22,2
+AB3,GND,GND,GND,,AB,22,3
+AB4,VCCAUX,VCCAUX,VCCAUX,,AB,22,4
+AB5,VCCAUX,VCCAUX,VCCAUX,,AB,22,5
+AB6,IP_2/VREF_2,2,VREF,,AB,22,6
+AB7,IO_L14N_2,2,I/O,TRUE,AB,22,7
+AB8,VCCO_2,2,VCCO,,AB,22,8
+AB9,IO_L15P_2,2,I/O,TRUE,AB,22,9
+AB10,GND,GND,GND,,AB,22,10
+AB11,VCCAUX,VCCAUX,VCCAUX,,AB,22,11
+AB12,IO_L21P_2,2,I/O,TRUE,AB,22,12
+AB13,IP_2,2,INPUT,,AB,22,13
+AB14,VCCO_2,2,VCCO,,AB,22,14
+AB15,IO_L30N_2/MOSI/CSI_B,2,DUAL,TRUE,AB,22,15
+AB16,IO_L38N_2,2,I/O,TRUE,AB,22,16
+AB17,VCCAUX,VCCAUX,VCCAUX,,AB,22,17
+AB18,IO_L47P_2,2,I/O,TRUE,AB,22,18
+AB19,VCCO_2,2,VCCO,,AB,22,19
+AB20,GND,GND,GND,,AB,22,20
+AB21,DONE,VCCAUX,CONFIG,,AB,22,21
+AB22,VCCAUX,VCCAUX,VCCAUX,,AB,22,22
+AB23,IO_L07P_1,1,I/O,TRUE,AB,22,23
+AB24,IO_L07N_1/VREF_1,1,VREF,TRUE,AB,22,24
+AB25,VCCO_1,1,VCCO,,AB,22,25
+AB26,IO_L06N_1,1,I/O,TRUE,AB,22,26
+AC1,IO_L60N_3,3,I/O,TRUE,AC,23,1
+AC2,IO_L64P_3,3,I/O,TRUE,AC,23,2
+AC3,IO_L64N_3,3,I/O,TRUE,AC,23,3
+AC4,IO_L01P_2/M1,2,DUAL,TRUE,AC,23,4
+AC5,GND,GND,GND,,AC,23,5
+AC6,IO_L08P_2,2,I/O,TRUE,AC,23,6
+AC7,GND,GND,GND,,AC,23,7
+AC8,IO_L14P_2,2,I/O,TRUE,AC,23,8
+AC9,IO_L15N_2,2,I/O,TRUE,AC,23,9
+AC10,IP_2/VREF_2,2,VREF,,AC,23,10
+AC11,IO_L23N_2,2,I/O,TRUE,AC,23,11
+AC12,IO_L21N_2,2,I/O,TRUE,AC,23,12
+AC13,IP_2,2,INPUT,,AC,23,13
+AC14,IO_L29N_2,2,I/O,TRUE,AC,23,14
+AC15,IO_L30P_2,2,I/O,TRUE,AC,23,15
+AC16,IO_L38P_2,2,I/O,TRUE,AC,23,16
+AC17,IP_2,2,INPUT,,AC,23,17
+AC18,GND,GND,GND,,AC,23,18
+AC19,IO_L40N_2,2,I/O,TRUE,AC,23,19
+AC20,IO_L41N_2,2,I/O,TRUE,AC,23,20
+AC21,IO_L45N_2,2,I/O,TRUE,AC,23,21
+AC22,IO_2,2,I/O,,AC,23,22
+AC23,IO_L03P_1/A0,1,DUAL,TRUE,AC,23,23
+AC24,IO_L03N_1/A1,1,DUAL,TRUE,AC,23,24
+AC25,IO_L05N_1,1,I/O,TRUE,AC,23,25
+AC26,IO_L06P_1,1,I/O,TRUE,AC,23,26
+AD1,IO_L65P_3,3,I/O,TRUE,AD,24,1
+AD2,IO_L65N_3,3,I/O,TRUE,AD,24,2
+AD3,GND,GND,GND,,AD,24,3
+AD4,IO_L01N_2/M0,2,DUAL,TRUE,AD,24,4
+AD5,GND,GND,GND,,AD,24,5
+AD6,IO_L08N_2,2,I/O,TRUE,AD,24,6
+AD7,IO_L11P_2,2,I/O,TRUE,AD,24,7
+AD8,GND,GND,GND,,AD,24,8
+AD9,IP_2,2,INPUT,,AD,24,9
+AD10,IP_2,2,INPUT,,AD,24,10
+AD11,IO_L23P_2,2,I/O,TRUE,AD,24,11
+AD12,IP_2/VREF_2,2,VREF,,AD,24,12
+AD13,GND,GND,GND,,AD,24,13
+AD14,IO_L29P_2,2,I/O,TRUE,AD,24,14
+AD15,IO_L32P_2/AWAKE,2,PWRMGMT,TRUE,AD,24,15
+AD16,IP_2,2,INPUT,,AD,24,16
+AD17,IO_L33N_2,2,I/O,TRUE,AD,24,17
+AD18,GND,GND,GND,,AD,24,18
+AD19,IO_L40P_2,2,I/O,TRUE,AD,24,19
+AD20,IO_L41P_2,2,I/O,TRUE,AD,24,20
+AD21,IO_L44N_2,2,I/O,TRUE,AD,24,21
+AD22,IO_L45P_2,2,I/O,TRUE,AD,24,22
+AD23,GND,GND,GND,,AD,24,23
+AD24,GND,GND,GND,,AD,24,24
+AD25,IO_L02N_1/LDC0,1,DUAL,TRUE,AD,24,25
+AD26,IO_L05P_1,1,I/O,TRUE,AD,24,26
+AE1,IP_L66P_3,3,INPUT,TRUE,AE,25,1
+AE2,IP_L66N_3/VREF_3,3,VREF,TRUE,AE,25,2
+AE3,IO_L06P_2,2,I/O,TRUE,AE,25,3
+AE4,IO_L07P_2,2,I/O,TRUE,AE,25,4
+AE5,VCCO_2,2,VCCO,,AE,25,5
+AE6,IO_L10N_2,2,I/O,TRUE,AE,25,6
+AE7,IO_L11N_2,2,I/O,TRUE,AE,25,7
+AE8,IO_L18P_2,2,I/O,TRUE,AE,25,8
+AE9,IO_L19P_2/VS1,2,DUAL,TRUE,AE,25,9
+AE10,IO_L22P_2/D7,2,DUAL,TRUE,AE,25,10
+AE11,VCCO_2,2,VCCO,,AE,25,11
+AE12,IO_L24N_2/D4,2,DUAL,TRUE,AE,25,12
+AE13,IO_L26N_2/GCLK15,2,GCLK,TRUE,AE,25,13
+AE14,IO_L28N_2/GCLK3,2,GCLK,TRUE,AE,25,14
+AE15,IO_L32N_2/DOUT,2,DUAL,TRUE,AE,25,15
+AE16,VCCO_2,2,VCCO,,AE,25,16
+AE17,IO_L33P_2,2,I/O,TRUE,AE,25,17
+AE18,IO_L36N_2/D1,2,DUAL,TRUE,AE,25,18
+AE19,IO_L37N_2,2,I/O,TRUE,AE,25,19
+AE20,IO_L39N_2,2,I/O,TRUE,AE,25,20
+AE21,IO_L44P_2,2,I/O,TRUE,AE,25,21
+AE22,VCCO_2,2,VCCO,,AE,25,22
+AE23,IO_L48N_2,2,I/O,TRUE,AE,25,23
+AE24,IO_L52N_2/CCLK,2,DUAL,TRUE,AE,25,24
+AE25,IO_L51N_2,2,I/O,TRUE,AE,25,25
+AE26,IO_L02P_1/LDC1,1,DUAL,TRUE,AE,25,26
+AF1,GND,GND,GND,,AF,26,1
+AF2,VCCAUX,VCCAUX,VCCAUX,,AF,26,2
+AF3,IO_L06N_2,2,I/O,TRUE,AF,26,3
+AF4,IO_L07N_2,2,I/O,TRUE,AF,26,4
+AF5,IO_L10P_2,2,I/O,TRUE,AF,26,5
+AF6,GND,GND,GND,,AF,26,6
+AF7,VCCO_2,2,VCCO,,AF,26,7
+AF8,IO_L18N_2,2,I/O,TRUE,AF,26,8
+AF9,IO_L19N_2/VS0,2,DUAL,TRUE,AF,26,9
+AF10,IO_L22N_2/D6,2,DUAL,TRUE,AF,26,10
+AF11,GND,GND,GND,,AF,26,11
+AF12,IO_L24P_2/D5,2,DUAL,TRUE,AF,26,12
+AF13,IO_L26P_2/GCLK14,2,GCLK,TRUE,AF,26,13
+AF14,IO_L28P_2/GCLK2,2,GCLK,TRUE,AF,26,14
+AF15,IP_2/VREF_2,2,VREF,,AF,26,15
+AF16,GND,GND,GND,,AF,26,16
+AF17,IP_2/VREF_2,2,VREF,,AF,26,17
+AF18,IO_L36P_2/D2,2,DUAL,TRUE,AF,26,18
+AF19,IO_L37P_2,2,I/O,TRUE,AF,26,19
+AF20,IO_L39P_2,2,I/O,TRUE,AF,26,20
+AF21,GND,GND,GND,,AF,26,21
+AF22,IP_2/VREF_2,2,VREF,,AF,26,22
+AF23,IO_L48P_2,2,I/O,TRUE,AF,26,23
+AF24,IO_L52P_2/D0/DIN/MISO,2,DUAL,TRUE,AF,26,24
+AF25,IO_L51P_2,2,I/O,TRUE,AF,26,25
+AF26,GND,GND,GND,,AF,26,26
+B1,IO_L02N_3,3,I/O,TRUE,B,2,1
+B2,IO_L02P_3,3,I/O,TRUE,B,2,2
+B3,IO_L51N_0,0,I/O,TRUE,B,2,3
+B4,IO_L45N_0,0,I/O,TRUE,B,2,4
+B5,VCCO_0,0,VCCO,,B,2,5
+B6,IO_L41P_0,0,I/O,TRUE,B,2,6
+B7,IO_L42P_0,0,I/O,TRUE,B,2,7
+B8,IO_L38N_0,0,I/O,TRUE,B,2,8
+B9,IO_L36N_0,0,I/O,TRUE,B,2,9
+B10,IO_L33N_0,0,I/O,TRUE,B,2,10
+B11,VCCO_0,0,VCCO,,B,2,11
+B12,IO_L29N_0,0,I/O,TRUE,B,2,12
+B13,IO_L28P_0/GCLK10,0,GCLK,TRUE,B,2,13
+B14,IO_L26P_0/GCLK6,0,GCLK,TRUE,B,2,14
+B15,IO_L23P_0,0,I/O,TRUE,B,2,15
+B16,VCCO_0,0,VCCO,,B,2,16
+B17,IO_L19N_0,0,I/O,TRUE,B,2,17
+B18,IO_L18P_0,0,I/O,TRUE,B,2,18
+B19,IO_L15P_0,0,I/O,TRUE,B,2,19
+B20,IO_L14P_0/VREF_0,0,VREF,TRUE,B,2,20
+B21,IO_L09N_0,0,I/O,TRUE,B,2,21
+B22,VCCO_0,0,VCCO,,B,2,22
+B23,IO_L07P_0,0,I/O,TRUE,B,2,23
+B24,GND,GND,GND,,B,2,24
+B25,GND,GND,GND,,B,2,25
+B26,IP_1/VREF_1,1,VREF,,B,2,26
+C1,IP_3/VREF_3,3,VREF,,C,3,1
+C2,VCCO_3,3,VCCO,,C,3,2
+C3,GND,GND,GND,,C,3,3
+C4,VCCINT,VCCINT,VCCINT,,C,3,4
+C5,IO_L44P_0,0,I/O,TRUE,C,3,5
+C6,IO_L41N_0,0,I/O,TRUE,C,3,6
+C7,IO_L42N_0,0,I/O,TRUE,C,3,7
+C8,IO_L40P_0,0,I/O,TRUE,C,3,8
+C9,GND,GND,GND,,C,3,9
+C10,IO_L34P_0,0,I/O,TRUE,C,3,10
+C11,IO_L32P_0,0,I/O,TRUE,C,3,11
+C12,IO_L30N_0,0,I/O,TRUE,C,3,12
+C13,IO_L28N_0/GCLK11,0,GCLK,TRUE,C,3,13
+C14,GND,GND,GND,,C,3,14
+C15,IO_L22N_0,0,I/O,TRUE,C,3,15
+C16,IO_L21N_0,0,I/O,TRUE,C,3,16
+C17,IO_L19P_0,0,I/O,TRUE,C,3,17
+C18,IO_L17N_0,0,I/O,TRUE,C,3,18
+C19,GND,GND,GND,,C,3,19
+C20,IO_L11N_0,0,I/O,TRUE,C,3,20
+C21,IO_L09P_0,0,I/O,TRUE,C,3,21
+C22,IO_L05N_0,0,I/O,TRUE,C,3,22
+C23,IO_L06N_0,0,I/O,TRUE,C,3,23
+C24,GND,GND,GND,,C,3,24
+C25,IO_L63N_1/A23,1,DUAL,TRUE,C,3,25
+C26,IO_L63P_1/A22,1,DUAL,TRUE,C,3,26
+D1,VCCAUX,VCCAUX,VCCAUX,,D,4,1
+D2,GND,GND,GND,,D,4,2
+D3,IO_L06P_3,3,I/O,TRUE,D,4,3
+D4,TMS,VCCAUX,JTAG,,D,4,4
+D5,VCCINT,VCCINT,VCCINT,,D,4,5
+D6,IO_L44N_0,0,I/O,TRUE,D,4,6
+D7,IP_0/VREF_0,0,VREF,,D,4,7
+D8,IO_L40N_0,0,I/O,TRUE,D,4,8
+D9,IO_L37N_0,0,I/O,TRUE,D,4,9
+D10,IO_L34N_0,0,I/O,TRUE,D,4,10
+D11,IO_L32N_0/VREF_0,0,VREF,TRUE,D,4,11
+D12,IP_0,0,INPUT,,D,4,12
+D13,IO_L30P_0,0,I/O,TRUE,D,4,13
+D14,IP_0/VREF_0,0,VREF,,D,4,14
+D15,GND,GND,GND,,D,4,15
+D16,IO_L22P_0,0,I/O,TRUE,D,4,16
+D17,IO_L21P_0,0,I/O,TRUE,D,4,17
+D18,IO_L17P_0,0,I/O,TRUE,D,4,18
+D19,GND,GND,GND,,D,4,19
+D20,IO_L11P_0,0,I/O,TRUE,D,4,20
+D21,IO_L10N_0,0,I/O,TRUE,D,4,21
+D22,IO_L05P_0,0,I/O,TRUE,D,4,22
+D23,IO_L06P_0,0,I/O,TRUE,D,4,23
+D24,IO_L61N_1,1,I/O,TRUE,D,4,24
+D25,IO_L61P_1,1,I/O,TRUE,D,4,25
+D26,IO_L60N_1,1,I/O,TRUE,D,4,26
+E1,IO_L11P_3,3,I/O,TRUE,E,5,1
+E2,VCCO_3,3,VCCO,,E,5,2
+E3,IO_L07P_3,3,I/O,TRUE,E,5,3
+E4,IO_L06N_3,3,I/O,TRUE,E,5,4
+E5,VCCAUX,VCCAUX,VCCAUX,,E,5,5
+E6,VCCINT,VCCINT,VCCINT,,E,5,6
+E7,IO_L48N_0,0,I/O,TRUE,E,5,7
+E8,VCCO_0,0,VCCO,,E,5,8
+E9,GND,GND,GND,,E,5,9
+E10,IO_L37P_0,0,I/O,TRUE,E,5,10
+E11,IP_0,0,INPUT,,E,5,11
+E12,IO_L31P_0,0,I/O,TRUE,E,5,12
+E13,VCCO_0,0,VCCO,,E,5,13
+E14,IO_L24P_0,0,I/O,TRUE,E,5,14
+E15,IO_L20N_0/VREF_0,0,VREF,TRUE,E,5,15
+E16,VCCAUX,VCCAUX,VCCAUX,,E,5,16
+E17,IO_L13N_0,0,I/O,TRUE,E,5,17
+E18,IP_0,0,INPUT,,E,5,18
+E19,VCCO_0,0,VCCO,,E,5,19
+E20,VCCAUX,VCCAUX,VCCAUX,,E,5,20
+E21,IO_L10P_0,0,I/O,TRUE,E,5,21
+E22,VCCAUX,VCCAUX,VCCAUX,,E,5,22
+E23,TDO,VCCAUX,JTAG,,E,5,23
+E24,IO_L56P_1,1,I/O,TRUE,E,5,24
+E25,VCCO_1,1,VCCO,,E,5,25
+E26,IO_L60P_1,1,I/O,TRUE,E,5,26
+F1,GND,GND,GND,,F,6,1
+F2,IO_L11N_3,3,I/O,TRUE,F,6,2
+F3,IO_L14N_3,3,I/O,TRUE,F,6,3
+F4,IO_L07N_3,3,I/O,TRUE,F,6,4
+F5,IO_L09P_3,3,I/O,TRUE,F,6,5
+F6,GND,GND,GND,,F,6,6
+F7,IO_L48P_0,0,I/O,TRUE,F,6,7
+F8,IO_L52P_0/VREF_0,0,VREF,TRUE,F,6,8
+F9,VCCAUX,VCCAUX,VCCAUX,,F,6,9
+F10,VCCINT,VCCINT,VCCINT,,F,6,10
+F11,GND,GND,GND,,F,6,11
+F12,IO_L31N_0,0,I/O,TRUE,F,6,12
+F13,IO_L27P_0/GCLK8,0,GCLK,TRUE,F,6,13
+F14,IO_L24N_0,0,I/O,TRUE,F,6,14
+F15,IO_L20P_0,0,I/O,TRUE,F,6,15
+F16,GND,GND,GND,,F,6,16
+F17,IO_L13P_0,0,I/O,TRUE,F,6,17
+F18,VCCINT,VCCINT,VCCINT,,F,6,18
+F19,IO_L02N_0,0,I/O,TRUE,F,6,19
+F20,IO_L01N_0,0,I/O,TRUE,F,6,20
+F21,GND,GND,GND,,F,6,21
+F22,IO_L58P_1/VREF_1,1,VREF,TRUE,F,6,22
+F23,IO_L56N_1,1,I/O,TRUE,F,6,23
+F24,IO_L54N_1,1,I/O,TRUE,F,6,24
+F25,IO_L54P_1,1,I/O,TRUE,F,6,25
+F26,GND,GND,GND,,F,6,26
+G1,IP_3,3,INPUT,,G,7,1
+G2,GND,GND,GND,,G,7,2
+G3,IO_L14P_3,3,I/O,TRUE,G,7,3
+G4,IO_L09N_3,3,I/O,TRUE,G,7,4
+G5,GND,GND,GND,,G,7,5
+G6,IO_L03P_3,3,I/O,TRUE,G,7,6
+G7,TDI,VCCAUX,JTAG,,G,7,7
+G8,IO_L52N_0/PUDC_B,0,DUAL,TRUE,G,7,8
+G9,IO_L47P_0,0,I/O,TRUE,G,7,9
+G10,IO_L46P_0,0,I/O,TRUE,G,7,10
+G11,IP_0/VREF_0,0,VREF,,G,7,11
+G12,IO_L35P_0,0,I/O,TRUE,G,7,12
+G13,IO_L27N_0/GCLK9,0,GCLK,TRUE,G,7,13
+G14,IP_0,0,INPUT,,G,7,14
+G15,IO_L16P_0,0,I/O,TRUE,G,7,15
+G16,GND,GND,GND,,G,7,16
+G17,IO_L08N_0,0,I/O,TRUE,G,7,17
+G18,VCCINT,VCCINT,VCCINT,,G,7,18
+G19,IO_L02P_0/VREF_0,0,VREF,TRUE,G,7,19
+G20,IO_L01P_0,0,I/O,TRUE,G,7,20
+G21,IO_L64N_1/A25,1,DUAL,TRUE,G,7,21
+G22,IO_L58N_1,1,I/O,TRUE,G,7,22
+G23,IO_L51P_1,1,I/O,TRUE,G,7,23
+G24,IO_L51N_1,1,I/O,TRUE,G,7,24
+G25,IP_1/VREF_1,1,VREF,,G,7,25
+G26,VCCAUX,VCCAUX,VCCAUX,,G,7,26
+H1,IO_L17N_3,3,I/O,TRUE,H,8,1
+H2,IO_L17P_3,3,I/O,TRUE,H,8,2
+H3,GND,GND,GND,,H,8,3
+H4,IP_3/VREF_3,3,VREF,,H,8,4
+H5,VCCO_3,3,VCCO,,H,8,5
+H6,IO_L10N_3,3,I/O,TRUE,H,8,6
+H7,IO_L03N_3,3,I/O,TRUE,H,8,7
+H8,GND,GND,GND,,H,8,8
+H9,IO_L47N_0,0,I/O,TRUE,H,8,9
+H10,IO_L46N_0,0,I/O,TRUE,H,8,10
+H11,VCCO_0,0,VCCO,,H,8,11
+H12,IO_L35N_0,0,I/O,TRUE,H,8,12
+H13,IP_0,0,INPUT,,H,8,13
+H14,GND,GND,GND,,H,8,14
+H15,IO_L16N_0,0,I/O,TRUE,H,8,15
+H16,VCCO_0,0,VCCO,,H,8,16
+H17,IO_L08P_0,0,I/O,TRUE,H,8,17
+H18,IP_0,0,INPUT,,H,8,18
+H19,GND,GND,GND,,H,8,19
+H20,IO_L64P_1/A24,1,DUAL,TRUE,H,8,20
+H21,IO_L62N_1/A21,1,DUAL,TRUE,H,8,21
+H22,VCCO_1,1,VCCO,,H,8,22
+H23,VCCAUX,VCCAUX,VCCAUX,,H,8,23
+H24,IP_1,1,INPUT,,H,8,24
+H25,VCCO_1,1,VCCO,,H,8,25
+H26,IP_1/VREF_1,1,VREF,,H,8,26
+J1,IP_L24P_3,3,INPUT,TRUE,J,9,1
+J2,IP_L20N_3/VREF_3,3,VREF,TRUE,J,9,2
+J3,IP_L20P_3,3,INPUT,TRUE,J,9,3
+J4,IO_L19N_3,3,I/O,TRUE,J,9,4
+J5,IO_L19P_3,3,I/O,TRUE,J,9,5
+J6,IO_L13N_3,3,I/O,TRUE,J,9,6
+J7,IO_L10P_3,3,I/O,TRUE,J,9,7
+J8,IO_L01P_3,3,I/O,TRUE,J,9,8
+J9,IO_L01N_3,3,I/O,TRUE,J,9,9
+J10,IP_0,0,INPUT,,J,9,10
+J11,IO_L43P_0,0,I/O,TRUE,J,9,11
+J12,IO_L39P_0,0,I/O,TRUE,J,9,12
+J13,IP_0,0,INPUT,,J,9,13
+J14,IO_L25N_0/GCLK5,0,GCLK,TRUE,J,9,14
+J15,IP_0,0,INPUT,,J,9,15
+J16,IO_L12P_0,0,I/O,TRUE,J,9,16
+J17,IP_0/VREF_0,0,VREF,,J,9,17
+J18,VCCAUX,VCCAUX,VCCAUX,,J,9,18
+J19,IO_L59P_1,1,I/O,TRUE,J,9,19
+J20,IO_L59N_1,1,I/O,TRUE,J,9,20
+J21,IO_L62P_1/A20,1,DUAL,TRUE,J,9,21
+J22,IO_L49N_1,1,I/O,TRUE,J,9,22
+J23,IO_L49P_1,1,I/O,TRUE,J,9,23
+J24,GND,GND,GND,,J,9,24
+J25,IO_L43N_1/A19,1,DUAL,TRUE,J,9,25
+J26,IO_L43P_1/A18,1,DUAL,TRUE,J,9,26
+K1,IP_L24N_3,3,INPUT,TRUE,K,10,1
+K2,IO_L23N_3,3,I/O,TRUE,K,10,2
+K3,IO_L23P_3,3,I/O,TRUE,K,10,3
+K4,IO_L22N_3,3,I/O,TRUE,K,10,4
+K5,IO_L22P_3,3,I/O,TRUE,K,10,5
+K6,IO_L18P_3,3,I/O,TRUE,K,10,6
+K7,IO_L13P_3,3,I/O,TRUE,K,10,7
+K8,IO_L05N_3,3,I/O,TRUE,K,10,8
+K9,IO_L05P_3,3,I/O,TRUE,K,10,9
+K10,GND,GND,GND,,K,10,10
+K11,IO_L43N_0,0,I/O,TRUE,K,10,11
+K12,IO_L39N_0,0,I/O,TRUE,K,10,12
+K13,VCCAUX,VCCAUX,VCCAUX,,K,10,13
+K14,IO_L25P_0/GCLK4,0,GCLK,TRUE,K,10,14
+K15,VCCINT,VCCINT,VCCINT,,K,10,15
+K16,IO_L12N_0,0,I/O,TRUE,K,10,16
+K17,GND,GND,GND,,K,10,17
+K18,IO_L57N_1,1,I/O,TRUE,K,10,18
+K19,IO_L57P_1,1,I/O,TRUE,K,10,19
+K20,IO_L53N_1,1,I/O,TRUE,K,10,20
+K21,IO_L50N_1,1,I/O,TRUE,K,10,21
+K22,IO_L46N_1,1,I/O,TRUE,K,10,22
+K23,IO_L46P_1,1,I/O,TRUE,K,10,23
+K24,IP_L40P_1,1,INPUT,TRUE,K,10,24
+K25,IO_L41P_1,1,I/O,TRUE,K,10,25
+K26,IO_L41N_1,1,I/O,TRUE,K,10,26
+L1,GND,GND,GND,,L,11,1
+L2,VCCO_3,3,VCCO,,L,11,2
+L3,IO_L25N_3,3,I/O,TRUE,L,11,3
+L4,IO_L25P_3,3,I/O,TRUE,L,11,4
+L5,VCCAUX,VCCAUX,VCCAUX,,L,11,5
+L6,GND,GND,GND,,L,11,6
+L7,IO_L18N_3,3,I/O,TRUE,L,11,7
+L8,VCCO_3,3,VCCO,,L,11,8
+L9,IO_L15N_3,3,I/O,TRUE,L,11,9
+L10,IO_L15P_3,3,I/O,TRUE,L,11,10
+L11,GND,GND,GND,,L,11,11
+L12,VCCINT,VCCINT,VCCINT,,L,11,12
+L13,GND,GND,GND,,L,11,13
+L14,VCCINT,VCCINT,VCCINT,,L,11,14
+L15,GND,GND,GND,,L,11,15
+L16,VCCINT,VCCINT,VCCINT,,L,11,16
+L17,IO_L55N_1,1,I/O,TRUE,L,11,17
+L18,IO_L55P_1,1,I/O,TRUE,L,11,18
+L19,VCCO_1,1,VCCO,,L,11,19
+L20,IO_L53P_1,1,I/O,TRUE,L,11,20
+L21,GND,GND,GND,,L,11,21
+L22,IO_L50P_1,1,I/O,TRUE,L,11,22
+L23,IP_L40N_1,1,INPUT,TRUE,L,11,23
+L24,IO_L38P_1/A12,1,DUAL,TRUE,L,11,24
+L25,VCCO_1,1,VCCO,,L,11,25
+L26,GND,GND,GND,,L,11,26
+M1,IO_L29N_3/VREF_3,3,VREF,TRUE,M,12,1
+M2,IO_L29P_3,3,I/O,TRUE,M,12,2
+M3,IO_L27N_3,3,I/O,TRUE,M,12,3
+M4,IO_L27P_3,3,I/O,TRUE,M,12,4
+M5,IO_L28P_3,3,I/O,TRUE,M,12,5
+M6,IO_L28N_3,3,I/O,TRUE,M,12,6
+M7,IO_L26N_3,3,I/O,TRUE,M,12,7
+M8,IO_L26P_3,3,I/O,TRUE,M,12,8
+M9,IO_L21N_3,3,I/O,TRUE,M,12,9
+M10,IO_L21P_3,3,I/O,TRUE,M,12,10
+M11,VCCINT,VCCINT,VCCINT,,M,12,11
+M12,GND,GND,GND,,M,12,12
+M13,VCCINT,VCCINT,VCCINT,,M,12,13
+M14,GND,GND,GND,,M,12,14
+M15,VCCINT,VCCINT,VCCINT,,M,12,15
+M16,GND,GND,GND,,M,12,16
+M17,VCCINT,VCCINT,VCCINT,,M,12,17
+M18,IO_L47N_1,1,I/O,TRUE,M,12,18
+M19,IO_L47P_1,1,I/O,TRUE,M,12,19
+M20,IO_L42N_1/A17,1,DUAL,TRUE,M,12,20
+M21,IO_L45P_1,1,I/O,TRUE,M,12,21
+M22,IO_L45N_1,1,I/O,TRUE,M,12,22
+M23,IO_L38N_1/A13,1,DUAL,TRUE,M,12,23
+M24,IP_L36P_1/VREF_1,1,VREF,TRUE,M,12,24
+M25,IO_L35N_1/A11,1,DUAL,TRUE,M,12,25
+M26,IO_L35P_1/A10,1,DUAL,TRUE,M,12,26
+N1,IO_L31P_3,3,I/O,TRUE,N,13,1
+N2,IO_L31N_3,3,I/O,TRUE,N,13,2
+N3,GND,GND,GND,,N,13,3
+N4,IO_L30N_3,3,I/O,TRUE,N,13,4
+N5,IO_L30P_3,3,I/O,TRUE,N,13,5
+N6,IO_L32P_3/LHCLK0,3,LHCLK,TRUE,N,13,6
+N7,IO_L32N_3/LHCLK1,3,LHCLK,TRUE,N,13,7
+N8,GND,GND,GND,,N,13,8
+N9,IO_L35P_3/TRDY2/LHCLK6,3,LHCLK,TRUE,N,13,9
+N10,VCCAUX,VCCAUX,VCCAUX,,N,13,10
+N11,GND,GND,GND,,N,13,11
+N12,VCCINT,VCCINT,VCCINT,,N,13,12
+N13,VCCINT,VCCINT,VCCINT,,N,13,13
+N14,VCCINT,VCCINT,VCCINT,,N,13,14
+N15,GND,GND,GND,,N,13,15
+N16,VCCINT,VCCINT,VCCINT,,N,13,16
+N17,IO_L39N_1/A15,1,DUAL,TRUE,N,13,17
+N18,IO_L39P_1/A14,1,DUAL,TRUE,N,13,18
+N19,IO_L34N_1/RHCLK7,1,RHCLK,TRUE,N,13,19
+N20,IO_L42P_1/A16,1,DUAL,TRUE,N,13,20
+N21,IO_L37N_1,1,I/O,TRUE,N,13,21
+N22,VCCO_1,1,VCCO,,N,13,22
+N23,IP_L36N_1,1,INPUT,TRUE,N,13,23
+N24,IO_L33N_1/RHCLK5,1,RHCLK,TRUE,N,13,24
+N25,IP_L32N_1,1,INPUT,TRUE,N,13,25
+N26,IP_L32P_1,1,INPUT,TRUE,N,13,26
+P1,IO_L33P_3/LHCLK2,3,LHCLK,TRUE,P,14,1
+P2,IO_L33N_3/IRDY2/LHCLK3,3,LHCLK,TRUE,P,14,2
+P3,IO_L34N_3/LHCLK5,3,LHCLK,TRUE,P,14,3
+P4,IO_L34P_3/LHCLK4,3,LHCLK,TRUE,P,14,4
+P5,VCCO_3,3,VCCO,,P,14,5
+P6,IO_L39N_3,3,I/O,TRUE,P,14,6
+P7,IO_L39P_3,3,I/O,TRUE,P,14,7
+P8,IO_L41P_3,3,I/O,TRUE,P,14,8
+P9,IO_L41N_3,3,I/O,TRUE,P,14,9
+P10,IO_L35N_3/LHCLK7,3,LHCLK,TRUE,P,14,10
+P11,VCCINT,VCCINT,VCCINT,,P,14,11
+P12,GND,GND,GND,,P,14,12
+P13,VCCINT,VCCINT,VCCINT,,P,14,13
+P14,VCCINT,VCCINT,VCCINT,,P,14,14
+P15,VCCINT,VCCINT,VCCINT,,P,14,15
+P16,GND,GND,GND,,P,14,16
+P17,VCCAUX,VCCAUX,VCCAUX,,P,14,17
+P18,IO_L34P_1/IRDY1/RHCLK6,1,RHCLK,TRUE,P,14,18
+P19,GND,GND,GND,,P,14,19
+P20,IO_L30N_1/RHCLK1,1,RHCLK,TRUE,P,14,20
+P21,IO_L30P_1/RHCLK0,1,RHCLK,TRUE,P,14,21
+P22,IO_L37P_1,1,I/O,TRUE,P,14,22
+P23,IO_L33P_1/RHCLK4,1,RHCLK,TRUE,P,14,23
+P24,GND,GND,GND,,P,14,24
+P25,IO_L31N_1/TRDY1/RHCLK3,1,RHCLK,TRUE,P,14,25
+P26,IO_L31P_1/RHCLK2,1,RHCLK,TRUE,P,14,26
+R1,IO_L36P_3/VREF_3,3,VREF,TRUE,R,15,1
+R2,IO_L36N_3,3,I/O,TRUE,R,15,2
+R3,IO_L37P_3,3,I/O,TRUE,R,15,3
+R4,IO_L37N_3,3,I/O,TRUE,R,15,4
+R5,IO_L40P_3,3,I/O,TRUE,R,15,5
+R6,IO_L40N_3,3,I/O,TRUE,R,15,6
+R7,IO_L45N_3,3,I/O,TRUE,R,15,7
+R8,IO_L45P_3,3,I/O,TRUE,R,15,8
+R9,IO_L43N_3,3,I/O,TRUE,R,15,9
+R10,IO_L43P_3/VREF_3,3,VREF,TRUE,R,15,10
+R11,GND,GND,GND,,R,15,11
+R12,VCCINT,VCCINT,VCCINT,,R,15,12
+R13,GND,GND,GND,,R,15,13
+R14,VCCINT,VCCINT,VCCINT,,R,15,14
+R15,GND,GND,GND,,R,15,15
+R16,VCCINT,VCCINT,VCCINT,,R,15,16
+R17,IO_L27N_1/A7,1,DUAL,TRUE,R,15,17
+R18,IO_L27P_1/A6,1,DUAL,TRUE,R,15,18
+R19,IO_L22P_1,1,I/O,TRUE,R,15,19
+R20,IO_L22N_1,1,I/O,TRUE,R,15,20
+R21,IO_L25P_1/A2,1,DUAL,TRUE,R,15,21
+R22,IO_L25N_1/A3,1,DUAL,TRUE,R,15,22
+R23,IP_L28P_1/VREF_1,1,VREF,TRUE,R,15,23
+R24,IP_L28N_1,1,INPUT,TRUE,R,15,24
+R25,IO_L29P_1/A8,1,DUAL,TRUE,R,15,25
+R26,IO_L29N_1/A9,1,DUAL,TRUE,R,15,26
+T1,GND,GND,GND,,T,16,1
+T2,VCCO_3,3,VCCO,,T,16,2
+T3,IO_L38P_3,3,I/O,TRUE,T,16,3
+T4,IO_L38N_3,3,I/O,TRUE,T,16,4
+T5,IO_L42P_3,3,I/O,TRUE,T,16,5
+T6,GND,GND,GND,,T,16,6
+T7,IO_L51P_3,3,I/O,TRUE,T,16,7
+T8,VCCO_3,3,VCCO,,T,16,8
+T9,IO_L48N_3,3,I/O,TRUE,T,16,9
+T10,IO_L48P_3,3,I/O,TRUE,T,16,10
+T11,VCCINT,VCCINT,VCCINT,,T,16,11
+T12,GND,GND,GND,,T,16,12
+T13,VCCINT,VCCINT,VCCINT,,T,16,13
+T14,GND,GND,GND,,T,16,14
+T15,VCCINT,VCCINT,VCCINT,,T,16,15
+T16,GND,GND,GND,,T,16,16
+T17,IO_L17N_1,1,I/O,TRUE,T,16,17
+T18,IO_L17P_1,1,I/O,TRUE,T,16,18
+T19,VCCO_1,1,VCCO,,T,16,19
+T20,IO_L14N_1,1,I/O,TRUE,T,16,20
+T21,GND,GND,GND,,T,16,21
+T22,VCCAUX,VCCAUX,VCCAUX,,T,16,22
+T23,IO_L26P_1/A4,1,DUAL,TRUE,T,16,23
+T24,IO_L26N_1/A5,1,DUAL,TRUE,T,16,24
+T25,VCCO_1,1,VCCO,,T,16,25
+T26,GND,GND,GND,,T,16,26
+U1,IO_L44P_3,3,I/O,TRUE,U,17,1
+U2,IO_L44N_3,3,I/O,TRUE,U,17,2
+U3,IP_L46P_3,3,INPUT,TRUE,U,17,3
+U4,IO_L42N_3,3,I/O,TRUE,U,17,4
+U5,IO_L49P_3,3,I/O,TRUE,U,17,5
+U6,IO_L51N_3,3,I/O,TRUE,U,17,6
+U7,IO_L56P_3,3,I/O,TRUE,U,17,7
+U8,IO_L56N_3,3,I/O,TRUE,U,17,8
+U9,IO_L61P_3,3,I/O,TRUE,U,17,9
+U10,GND,GND,GND,,U,17,10
+U11,IO_L13N_2,2,I/O,TRUE,U,17,11
+U12,VCCINT,VCCINT,VCCINT,,U,17,12
+U13,GND,GND,GND,,U,17,13
+U14,VCCAUX,VCCAUX,VCCAUX,,U,17,14
+U15,IO_L35N_2,2,I/O,TRUE,U,17,15
+U16,IO_L42N_2,2,I/O,TRUE,U,17,16
+U17,GND,GND,GND,,U,17,17
+U18,IO_L12N_1,1,I/O,TRUE,U,17,18
+U19,IO_L12P_1,1,I/O,TRUE,U,17,19
+U20,IO_L10N_1,1,I/O,TRUE,U,17,20
+U21,IO_L14P_1,1,I/O,TRUE,U,17,21
+U22,IO_L21N_1,1,I/O,TRUE,U,17,22
+U23,IO_L23P_1,1,I/O,TRUE,U,17,23
+U24,IO_L23N_1/VREF_1,1,VREF,TRUE,U,17,24
+U25,GND,GND,GND,,U,17,25
+U26,IP_1/VREF_1,1,VREF,,U,17,26
+V1,IO_L47P_3,3,I/O,TRUE,V,18,1
+V2,IO_L47N_3,3,I/O,TRUE,V,18,2
+V3,GND,GND,GND,,V,18,3
+V4,IP_L46N_3,3,INPUT,TRUE,V,18,4
+V5,IO_L49N_3,3,I/O,TRUE,V,18,5
+V6,IO_L59N_3,3,I/O,TRUE,V,18,6
+V7,IO_L59P_3,3,I/O,TRUE,V,18,7
+V8,IO_L61N_3,3,I/O,TRUE,V,18,8
+V9,VCCAUX,VCCAUX,VCCAUX,,V,18,9
+V10,IO_L09P_2,2,I/O,TRUE,V,18,10
+V11,IO_L13P_2,2,I/O,TRUE,V,18,11
+V12,IO_L16P_2,2,I/O,TRUE,V,18,12
+V13,IO_L20P_2,2,I/O,TRUE,V,18,13
+V14,IO_L31P_2,2,I/O,TRUE,V,18,14
+V15,IO_L35P_2,2,I/O,TRUE,V,18,15
+V16,IO_L42P_2,2,I/O,TRUE,V,18,16
+V17,IO_L46N_2,2,I/O,TRUE,V,18,17
+V18,IO_L08P_1,1,I/O,TRUE,V,18,18
+V19,IO_L08N_1,1,I/O,TRUE,V,18,19
+V20,SUSPEND,1,PWRMGMT,,V,18,20
+V21,IO_L10P_1,1,I/O,TRUE,V,18,21
+V22,IO_L18N_1,1,I/O,TRUE,V,18,22
+V23,IO_L21P_1,1,I/O,TRUE,V,18,23
+V24,IO_L19P_1,1,I/O,TRUE,V,18,24
+V25,IO_L19N_1,1,I/O,TRUE,V,18,25
+V26,IP_1/VREF_1,1,VREF,,V,18,26
+W1,IP_L50P_3,3,INPUT,TRUE,W,19,1
+W2,IP_L50N_3/VREF_3,3,VREF,TRUE,W,19,2
+W3,IO_L52P_3,3,I/O,TRUE,W,19,3
+W4,IO_L52N_3,3,I/O,TRUE,W,19,4
+W5,VCCO_3,3,VCCO,,W,19,5
+W6,IO_L63N_3,3,I/O,TRUE,W,19,6
+W7,IO_L63P_3,3,I/O,TRUE,W,19,7
+W8,GND,GND,GND,,W,19,8
+W9,IO_L05P_2,2,I/O,TRUE,W,19,9
+W10,IO_L09N_2,2,I/O,TRUE,W,19,10
+W11,VCCO_2,2,VCCO,,W,19,11
+W12,IO_L16N_2,2,I/O,TRUE,W,19,12
+W13,IO_L20N_2,2,I/O,TRUE,W,19,13
+W14,GND,GND,GND,,W,19,14
+W15,IO_L31N_2,2,I/O,TRUE,W,19,15
+W16,VCCO_2,2,VCCO,,W,19,16
+W17,IO_L46P_2,2,I/O,TRUE,W,19,17
+W18,VCCINT,VCCINT,VCCINT,,W,19,18
+W19,GND,GND,GND,,W,19,19
+W20,IO_L04P_1,1,I/O,TRUE,W,19,20
+W21,IO_L04N_1,1,I/O,TRUE,W,19,21
+W22,VCCO_1,1,VCCO,,W,19,22
+W23,IO_L18P_1,1,I/O,TRUE,W,19,23
+W24,GND,GND,GND,,W,19,24
+W25,GND,GND,GND,,W,19,25
+W26,VCCAUX,VCCAUX,VCCAUX,,W,19,26
+Y1,IO_L53P_3,3,I/O,TRUE,Y,20,1
+Y2,IO_L53N_3,3,I/O,TRUE,Y,20,2
+Y3,IP_3,3,INPUT,,Y,20,3
+Y4,VCCINT,VCCINT,VCCINT,,Y,20,4
+Y5,IO_L57P_3,3,I/O,TRUE,Y,20,5
+Y6,IO_L57N_3,3,I/O,TRUE,Y,20,6
+Y7,IO_L02P_2/M2,2,DUAL,TRUE,Y,20,7
+Y8,VCCINT,VCCINT,VCCINT,,Y,20,8
+Y9,IO_L05N_2,2,I/O,TRUE,Y,20,9
+Y10,IO_L12P_2,2,I/O,TRUE,Y,20,10
+Y11,VCCINT,VCCINT,VCCINT,,Y,20,11
+Y12,IO_L17P_2/RDWR_B,2,DUAL,TRUE,Y,20,12
+Y13,IO_L25N_2/GCLK13,2,GCLK,TRUE,Y,20,13
+Y14,IO_L27P_2/GCLK0,2,GCLK,TRUE,Y,20,14
+Y15,IO_L34N_2/D3,2,DUAL,TRUE,Y,20,15
+Y16,IP_2/VREF_2,2,VREF,,Y,20,16
+Y17,IO_L43N_2,2,I/O,TRUE,Y,20,17
+Y18,VCCINT,VCCINT,VCCINT,,Y,20,18
+Y19,VCCINT,VCCINT,VCCINT,,Y,20,19
+Y20,IO_L01P_1/HDC,1,DUAL,TRUE,Y,20,20
+Y21,IO_L01N_1/LDC2,1,DUAL,TRUE,Y,20,21
+Y22,IO_L13P_1,1,I/O,TRUE,Y,20,22
+Y23,IO_L13N_1,1,I/O,TRUE,Y,20,23
+Y24,IO_L15P_1,1,I/O,TRUE,Y,20,24
+Y25,IO_L15N_1,1,I/O,TRUE,Y,20,25
+Y26,IP_1,1,INPUT,,Y,20,26
Added: usrp-hw/trunk/sym/generated/cy7c1354cv25-ac-CTRL.src
===================================================================
--- usrp-hw/trunk/sym/generated/cy7c1354cv25-ac-CTRL.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/cy7c1354cv25-ac-CTRL.src 2008-12-23
08:13:43 UTC (rev 10159)
@@ -0,0 +1,58 @@
+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# rotate_labels rotates the pintext of top and bottom pins
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)"
+wordswap=yes
+rotate_labels=yes
+sort_labels=no
+generate_pinseq=yes
+sym_width=1400
+pinwidthvertikal=400
+pinwidthhorizontal=400
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20060906
+name=CY7C1354C-AC-CTRL
+device=CY7C1354C-AC
+refdes=U?
+footprint=TQFP100
+description=256Kx36 ZBT/NoBL SRAM, 100-pin TQFP Package
+documentation=http://www.cypress.com
+author=mettus
+numslots=0
+#slot=1
+#slotdef=1:
+#slotdef=2:
+#slotdef=3:
+#slotdef=4:
+#comment=
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets
+# net specifies the name of the Vcc or GND name
+# label represents the pinlabel.
+# negation lines can be added with _Q_
+# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences
+#-----------------------------------------------------
+#pinnr seq type style posit. net label
+#-----------------------------------------------------
+31 in line r MODE
+64 in line r ZZ
+
+# in line l TDI
+# in line l TMS
+# out line l TDO
+# clk clk l TCK
Added: usrp-hw/trunk/sym/generated/cy7c1354cv25-ac-PWR.src
===================================================================
--- usrp-hw/trunk/sym/generated/cy7c1354cv25-ac-PWR.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/cy7c1354cv25-ac-PWR.src 2008-12-23 08:13:43 UTC
(rev 10159)
@@ -0,0 +1,77 @@
+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# rotate_labels rotates the pintext of top and bottom pins
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)"
+wordswap=yes
+rotate_labels=yes
+sort_labels=no
+generate_pinseq=yes
+sym_width=1400
+pinwidthvertikal=400
+pinwidthhorizontal=400
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20060906
+name=CY7C1354C-AC-PWR
+device=CY7C1354C-AC
+refdes=U?
+footprint=TQFP100
+description=256Kx36 ZBT/NoBL SRAM, 100-pin TQFP Package
+documentation=http://www.cypress.com
+author=mettus
+numslots=0
+#slot=1
+#slotdef=1:
+#slotdef=2:
+#slotdef=3:
+#slotdef=4:
+#comment=
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets
+# net specifies the name of the Vcc or GND name
+# label represents the pinlabel.
+# negation lines can be added with _Q_
+# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences
+#-----------------------------------------------------
+#pinnr seq type style posit. net label
+#-----------------------------------------------------
+5 pwr line r GND
+10 pwr line r GND
+17 pwr line r GND
+21 pwr line r GND
+26 pwr line r GND
+40 pwr line r GND
+55 pwr line r GND
+60 pwr line r GND
+67 pwr line r GND
+71 pwr line r GND
+76 pwr line r GND
+90 pwr line r GND
+
+4 pwr line l VDDQ
+11 pwr line l VDDQ
+20 pwr line l VDDQ
+27 pwr line l VDDQ
+54 pwr line l VDDQ
+61 pwr line l VDDQ
+70 pwr line l VDDQ
+77 pwr line l VDDQ
+
+15 pwr line l VDD
+41 pwr line l VDD
+65 pwr line l VDD
+91 pwr line l VDD
Added: usrp-hw/trunk/sym/generated/cy7c1354cv25-ac-RAM.src
===================================================================
--- usrp-hw/trunk/sym/generated/cy7c1354cv25-ac-RAM.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/cy7c1354cv25-ac-RAM.src 2008-12-23 08:13:43 UTC
(rev 10159)
@@ -0,0 +1,122 @@
+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# rotate_labels rotates the pintext of top and bottom pins
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)"
+wordswap=yes
+rotate_labels=yes
+sort_labels=no
+generate_pinseq=yes
+sym_width=5800
+pinwidthvertikal=400
+pinwidthhorizontal=400
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20060906
+name=CY7C1354C-AC-RAM
+device=CY7C1354C-AC
+refdes=U?
+footprint=TQFP100
+description=256Kx36 ZBT/NoBL SRAM, 100-pin TQFP Package
+documentation=http://www.cypress.com
+author=mettus
+numslots=0
+#slot=1
+#slotdef=1:
+#slotdef=2:
+#slotdef=3:
+#slotdef=4:
+#comment=
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets
+# net specifies the name of the Vcc or GND name
+# label represents the pinlabel.
+# negation lines can be added with _Q_
+# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences
+#-----------------------------------------------------
+#pinnr seq type style posit. net label
+#-----------------------------------------------------
+63 io line l DQa
+62 io line l DQa
+59 io line l DQa
+58 io line l DQa
+57 io line l DQa
+56 io line l DQa
+53 io line l DQa
+52 io line l DQa
+51 io line l DQPa
+
+68 io line l DQb
+69 io line l DQb
+72 io line l DQb
+73 io line l DQb
+74 io line l DQb
+75 io line l DQb
+78 io line l DQb
+79 io line l DQb
+80 io line l DQPb
+
+2 io line l DQc
+3 io line l DQc
+6 io line l DQc
+7 io line l DQc
+8 io line l DQc
+9 io line l DQc
+12 io line l DQc
+13 io line l DQc
+1 io line l DQPc
+
+18 io line l DQd
+19 io line l DQd
+22 io line l DQd
+23 io line l DQd
+24 io line l DQd
+25 io line l DQd
+28 io line l DQd
+29 io line l DQd
+30 io line l DQPd
+
+32 in line r A
+33 in line r A
+34 in line r A
+35 in line r A
+44 in line r A
+45 in line r A
+46 in line r A
+47 in line r A
+48 in line r A
+49 in line r A
+50 in line r A
+81 in line r A
+82 in line r A
+83 in line r A
+99 in line r A
+100 in line r A
+36 in line r A1
+37 in line r A0
+
+98 in dot b \_CE1\_
+97 in line b CE2
+92 in dot b \_CE3\_
+87 in dot b \_CEN\_
+89 clk clk b CLK
+88 in dot b \_WE\_
+86 in dot b \_OE\_
+85 in line b ADV/\_LD\_
+93 in dot b \_BWa\_
+94 in dot b \_BWb\_
+95 in dot b \_BWc\_
+96 in dot b \_BWd\_
Added: usrp-hw/trunk/sym/generated/xc3sd3400afg676-BOTCLK.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd3400afg676-BOTCLK.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd3400afg676-BOTCLK.src 2008-12-23
08:13:43 UTC (rev 10159)
@@ -0,0 +1,28 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=6000
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD3400AFG676-BOTCLK
+device=XC3SD3400AFG676
+refdes=U?
+footprint=FG676
+description=Xilinx Spartan 3A-DSP 1800/3400 FG676
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+AA13 clk clk l IO_L25P_2/GCLK12
+AA14 clk clk l IO_L27N_2/GCLK1
+AE13 clk clk l IO_L26N_2/GCLK15
+AE14 clk clk l IO_L28N_2/GCLK3
+AF13 clk clk l IO_L26P_2/GCLK14
+AF14 clk clk l IO_L28P_2/GCLK2
+Y13 clk clk l IO_L25N_2/GCLK13
+Y14 clk clk l IO_L27P_2/GCLK0
Added: usrp-hw/trunk/sym/generated/xc3sd3400afg676-CFG.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd3400afg676-CFG.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd3400afg676-CFG.src 2008-12-23 08:13:43 UTC
(rev 10159)
@@ -0,0 +1,45 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=6000
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD3400AFG676-CFG
+device=XC3SD3400AFG676
+refdes=U?
+footprint=FG676
+description=Xilinx Spartan 3A-DSP 1800/3400 FG676
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A2 io line l PROG_B
+AA7 io line r IO_L02N_2/CSO_B
+AA12 io line r IO_L17N_2/VS2
+AA15 io line r IO_L34P_2/INIT_B
+AB15 io line r IO_L30N_2/MOSI/CSI_B
+AB21 io line l DONE
+AC4 io line r IO_L01P_2/M1
+AD4 io line r IO_L01N_2/M0
+AD15 io line l IO_L32P_2/AWAKE
+AE9 io line r IO_L19P_2/VS1
+AE10 io line r IO_L22P_2/D7
+AE12 io line r IO_L24N_2/D4
+AE15 io line r IO_L32N_2/DOUT
+AE18 io line r IO_L36N_2/D1
+AE24 io line r IO_L52N_2/CCLK
+AF9 io line r IO_L19N_2/VS0
+AF10 io line r IO_L22N_2/D6
+AF12 io line r IO_L24P_2/D5
+AF18 io line r IO_L36P_2/D2
+AF24 io line r IO_L52P_2/D0/DIN/MISO
+G8 io line l IO_L52N_0/PUDC_B
+V20 io line l SUSPEND
+Y7 io line r IO_L02P_2/M2
+Y12 io line r IO_L17P_2/RDWR_B
+Y15 io line r IO_L34N_2/D3
Added: usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO0.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO0.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO0.src 2008-12-23 08:13:43 UTC
(rev 10159)
@@ -0,0 +1,132 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=6000
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD3400AFG676-IO0
+device=XC3SD3400AFG676
+refdes=U?
+footprint=FG676
+description=Xilinx Spartan 3A-DSP 1800/3400 FG676
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A3 io line l IO_L51P_0
+A4 io line l IO_L45P_0
+A7 pwr line b VCCO_0
+A8 io line l IO_L38P_0
+A9 io line l IO_L36P_0
+A10 io line l IO_L33P_0
+A12 io line l IO_L29P_0
+A13 in line r IP_0
+A15 io line l IO_L23N_0
+A17 in line r IP_0
+A18 io line l IO_L18N_0
+A19 io line l IO_L15N_0
+A20 io line l IO_L14N_0
+A22 io line l IO_L07N_0
+B3 io line l IO_L51N_0
+B4 io line l IO_L45N_0
+B5 pwr line b VCCO_0
+B6 io line l IO_L41P_0
+B7 io line l IO_L42P_0
+B8 io line l IO_L38N_0
+B9 io line l IO_L36N_0
+B10 io line l IO_L33N_0
+B11 pwr line b VCCO_0
+B12 io line l IO_L29N_0
+B15 io line l IO_L23P_0
+B16 pwr line b VCCO_0
+B17 io line l IO_L19N_0
+B18 io line l IO_L18P_0
+B19 io line l IO_L15P_0
+B20 io line r IO_L14P_0/VREF_0
+B21 io line l IO_L09N_0
+B22 pwr line b VCCO_0
+B23 io line l IO_L07P_0
+C5 io line l IO_L44P_0
+C6 io line l IO_L41N_0
+C7 io line l IO_L42N_0
+C8 io line l IO_L40P_0
+C10 io line l IO_L34P_0
+C11 io line l IO_L32P_0
+C12 io line l IO_L30N_0
+C15 io line l IO_L22N_0
+C16 io line l IO_L21N_0
+C17 io line l IO_L19P_0
+C18 io line l IO_L17N_0
+C20 io line l IO_L11N_0
+C21 io line l IO_L09P_0
+C22 io line l IO_L05N_0
+C23 io line l IO_L06N_0
+D6 io line l IO_L44N_0
+D7 io line r IP_0/VREF_0
+D8 io line l IO_L40N_0
+D9 io line l IO_L37N_0
+D10 io line l IO_L34N_0
+D11 io line r IO_L32N_0/VREF_0
+D12 in line r IP_0
+D13 io line l IO_L30P_0
+D14 io line r IP_0/VREF_0
+D16 io line l IO_L22P_0
+D17 io line l IO_L21P_0
+D18 io line l IO_L17P_0
+D20 io line l IO_L11P_0
+D21 io line l IO_L10N_0
+D22 io line l IO_L05P_0
+D23 io line l IO_L06P_0
+E7 io line l IO_L48N_0
+E8 pwr line b VCCO_0
+E10 io line l IO_L37P_0
+E11 in line r IP_0
+E12 io line l IO_L31P_0
+E13 pwr line b VCCO_0
+E14 io line l IO_L24P_0
+E15 io line r IO_L20N_0/VREF_0
+E17 io line l IO_L13N_0
+E18 in line r IP_0
+E19 pwr line b VCCO_0
+E21 io line l IO_L10P_0
+F7 io line l IO_L48P_0
+F8 io line r IO_L52P_0/VREF_0
+F12 io line l IO_L31N_0
+F14 io line l IO_L24N_0
+F15 io line l IO_L20P_0
+F17 io line l IO_L13P_0
+F19 io line l IO_L02N_0
+F20 io line l IO_L01N_0
+G9 io line l IO_L47P_0
+G10 io line l IO_L46P_0
+G11 io line r IP_0/VREF_0
+G12 io line l IO_L35P_0
+G14 in line r IP_0
+G15 io line l IO_L16P_0
+G17 io line l IO_L08N_0
+G19 io line r IO_L02P_0/VREF_0
+G20 io line l IO_L01P_0
+H9 io line l IO_L47N_0
+H10 io line l IO_L46N_0
+H11 pwr line b VCCO_0
+H12 io line l IO_L35N_0
+H13 in line r IP_0
+H15 io line l IO_L16N_0
+H16 pwr line b VCCO_0
+H17 io line l IO_L08P_0
+H18 in line r IP_0
+J10 in line r IP_0
+J11 io line l IO_L43P_0
+J12 io line l IO_L39P_0
+J13 in line r IP_0
+J15 in line r IP_0
+J16 io line l IO_L12P_0
+J17 io line r IP_0/VREF_0
+K11 io line l IO_L43N_0
+K12 io line l IO_L39N_0
+K16 io line l IO_L12N_0
Added: usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO1.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO1.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO1.src 2008-12-23 08:13:43 UTC
(rev 10159)
@@ -0,0 +1,145 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=6000
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD3400AFG676-IO1
+device=XC3SD3400AFG676
+refdes=U?
+footprint=FG676
+description=Xilinx Spartan 3A-DSP 1800/3400 FG676
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+AA22 io line l IO_L09P_1
+AA23 io line l IO_L09N_1
+AA24 io line l IO_L11P_1
+AA25 io line l IO_L11N_1
+AB23 io line l IO_L07P_1
+AB24 io line r IO_L07N_1/VREF_1
+AB25 pwr line b VCCO_1
+AB26 io line l IO_L06N_1
+AC23 io line l IO_L03P_1/A0
+AC24 io line l IO_L03N_1/A1
+AC25 io line l IO_L05N_1
+AC26 io line l IO_L06P_1
+AD25 io line l IO_L02N_1/LDC0
+AD26 io line l IO_L05P_1
+AE26 io line l IO_L02P_1/LDC1
+B26 io line r IP_1/VREF_1
+C25 io line l IO_L63N_1/A23
+C26 io line l IO_L63P_1/A22
+D24 io line l IO_L61N_1
+D25 io line l IO_L61P_1
+D26 io line l IO_L60N_1
+E24 io line l IO_L56P_1
+E25 pwr line b VCCO_1
+E26 io line l IO_L60P_1
+F22 io line r IO_L58P_1/VREF_1
+F23 io line l IO_L56N_1
+F24 io line l IO_L54N_1
+F25 io line l IO_L54P_1
+G21 io line l IO_L64N_1/A25
+G22 io line l IO_L58N_1
+G23 io line l IO_L51P_1
+G24 io line l IO_L51N_1
+G25 io line r IP_1/VREF_1
+H20 io line l IO_L64P_1/A24
+H21 io line l IO_L62N_1/A21
+H22 pwr line b VCCO_1
+H24 in line r IP_1
+H25 pwr line b VCCO_1
+H26 io line r IP_1/VREF_1
+J19 io line l IO_L59P_1
+J20 io line l IO_L59N_1
+J21 io line l IO_L62P_1/A20
+J22 io line l IO_L49N_1
+J23 io line l IO_L49P_1
+J25 io line l IO_L43N_1/A19
+J26 io line l IO_L43P_1/A18
+K18 io line l IO_L57N_1
+K19 io line l IO_L57P_1
+K20 io line l IO_L53N_1
+K21 io line l IO_L50N_1
+K22 io line l IO_L46N_1
+K23 io line l IO_L46P_1
+K24 in line r IP_L40P_1
+K25 io line l IO_L41P_1
+K26 io line l IO_L41N_1
+L17 io line l IO_L55N_1
+L18 io line l IO_L55P_1
+L19 pwr line b VCCO_1
+L20 io line l IO_L53P_1
+L22 io line l IO_L50P_1
+L23 in line r IP_L40N_1
+L24 io line l IO_L38P_1/A12
+L25 pwr line b VCCO_1
+M18 io line l IO_L47N_1
+M19 io line l IO_L47P_1
+M20 io line l IO_L42N_1/A17
+M21 io line l IO_L45P_1
+M22 io line l IO_L45N_1
+M23 io line l IO_L38N_1/A13
+M24 io line r IP_L36P_1/VREF_1
+M25 io line l IO_L35N_1/A11
+M26 io line l IO_L35P_1/A10
+N17 io line l IO_L39N_1/A15
+N18 io line l IO_L39P_1/A14
+N20 io line l IO_L42P_1/A16
+N21 io line l IO_L37N_1
+N22 pwr line b VCCO_1
+N23 in line r IP_L36N_1
+N25 in line r IP_L32N_1
+N26 in line r IP_L32P_1
+P22 io line l IO_L37P_1
+R17 io line l IO_L27N_1/A7
+R18 io line l IO_L27P_1/A6
+R19 io line l IO_L22P_1
+R20 io line l IO_L22N_1
+R21 io line l IO_L25P_1/A2
+R22 io line l IO_L25N_1/A3
+R23 io line r IP_L28P_1/VREF_1
+R24 in line r IP_L28N_1
+R25 io line l IO_L29P_1/A8
+R26 io line l IO_L29N_1/A9
+T17 io line l IO_L17N_1
+T18 io line l IO_L17P_1
+T19 pwr line b VCCO_1
+T20 io line l IO_L14N_1
+T23 io line l IO_L26P_1/A4
+T24 io line l IO_L26N_1/A5
+T25 pwr line b VCCO_1
+U18 io line l IO_L12N_1
+U19 io line l IO_L12P_1
+U20 io line l IO_L10N_1
+U21 io line l IO_L14P_1
+U22 io line l IO_L21N_1
+U23 io line l IO_L23P_1
+U24 io line r IO_L23N_1/VREF_1
+U26 io line r IP_1/VREF_1
+V18 io line l IO_L08P_1
+V19 io line l IO_L08N_1
+V21 io line l IO_L10P_1
+V22 io line l IO_L18N_1
+V23 io line l IO_L21P_1
+V24 io line l IO_L19P_1
+V25 io line l IO_L19N_1
+V26 io line r IP_1/VREF_1
+W20 io line l IO_L04P_1
+W21 io line l IO_L04N_1
+W22 pwr line b VCCO_1
+W23 io line l IO_L18P_1
+Y20 io line l IO_L01P_1/HDC
+Y21 io line l IO_L01N_1/LDC2
+Y22 io line l IO_L13P_1
+Y23 io line l IO_L13N_1
+Y24 io line l IO_L15P_1
+Y25 io line l IO_L15N_1
+Y26 in line r IP_1
Added: usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO2.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO2.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO2.src 2008-12-23 08:13:43 UTC
(rev 10159)
@@ -0,0 +1,113 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=6000
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD3400AFG676-IO2
+device=XC3SD3400AFG676
+refdes=U?
+footprint=FG676
+description=Xilinx Spartan 3A-DSP 1800/3400 FG676
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+AA9 io line r IP_2/VREF_2
+AA10 io line l IO_L12N_2
+AA17 io line l IO_L43P_2
+AA18 io line l IO_L47N_2
+AA20 io line r IP_2/VREF_2
+AB6 io line r IP_2/VREF_2
+AB7 io line l IO_L14N_2
+AB8 pwr line b VCCO_2
+AB9 io line l IO_L15P_2
+AB12 io line l IO_L21P_2
+AB13 in line r IP_2
+AB14 pwr line b VCCO_2
+AB16 io line l IO_L38N_2
+AB18 io line l IO_L47P_2
+AB19 pwr line b VCCO_2
+AC6 io line l IO_L08P_2
+AC8 io line l IO_L14P_2
+AC9 io line l IO_L15N_2
+AC10 io line r IP_2/VREF_2
+AC11 io line l IO_L23N_2
+AC12 io line l IO_L21N_2
+AC13 in line r IP_2
+AC14 io line l IO_L29N_2
+AC15 io line l IO_L30P_2
+AC16 io line l IO_L38P_2
+AC17 in line r IP_2
+AC19 io line l IO_L40N_2
+AC20 io line l IO_L41N_2
+AC21 io line l IO_L45N_2
+AC22 io line l IO_2
+AD6 io line l IO_L08N_2
+AD7 io line l IO_L11P_2
+AD9 in line r IP_2
+AD10 in line r IP_2
+AD11 io line l IO_L23P_2
+AD12 io line r IP_2/VREF_2
+AD14 io line l IO_L29P_2
+AD16 in line r IP_2
+AD17 io line l IO_L33N_2
+AD19 io line l IO_L40P_2
+AD20 io line l IO_L41P_2
+AD21 io line l IO_L44N_2
+AD22 io line l IO_L45P_2
+AE3 io line l IO_L06P_2
+AE4 io line l IO_L07P_2
+AE5 pwr line b VCCO_2
+AE6 io line l IO_L10N_2
+AE7 io line l IO_L11N_2
+AE8 io line l IO_L18P_2
+AE11 pwr line b VCCO_2
+AE16 pwr line b VCCO_2
+AE17 io line l IO_L33P_2
+AE19 io line l IO_L37N_2
+AE20 io line l IO_L39N_2
+AE21 io line l IO_L44P_2
+AE22 pwr line b VCCO_2
+AE23 io line l IO_L48N_2
+AE25 io line l IO_L51N_2
+AF3 io line l IO_L06N_2
+AF4 io line l IO_L07N_2
+AF5 io line l IO_L10P_2
+AF7 pwr line b VCCO_2
+AF8 io line l IO_L18N_2
+AF15 io line r IP_2/VREF_2
+AF17 io line r IP_2/VREF_2
+AF19 io line l IO_L37P_2
+AF20 io line l IO_L39P_2
+AF22 io line r IP_2/VREF_2
+AF23 io line l IO_L48P_2
+AF25 io line l IO_L51P_2
+U11 io line l IO_L13N_2
+U15 io line l IO_L35N_2
+U16 io line l IO_L42N_2
+V10 io line l IO_L09P_2
+V11 io line l IO_L13P_2
+V12 io line l IO_L16P_2
+V13 io line l IO_L20P_2
+V14 io line l IO_L31P_2
+V15 io line l IO_L35P_2
+V16 io line l IO_L42P_2
+V17 io line l IO_L46N_2
+W9 io line l IO_L05P_2
+W10 io line l IO_L09N_2
+W11 pwr line b VCCO_2
+W12 io line l IO_L16N_2
+W13 io line l IO_L20N_2
+W15 io line l IO_L31N_2
+W16 pwr line b VCCO_2
+W17 io line l IO_L46P_2
+Y9 io line l IO_L05N_2
+Y10 io line l IO_L12P_2
+Y16 io line r IP_2/VREF_2
+Y17 io line l IO_L43N_2
Added: usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO3.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO3.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd3400afg676-IO3.src 2008-12-23 08:13:43 UTC
(rev 10159)
@@ -0,0 +1,145 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=6000
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD3400AFG676-IO3
+device=XC3SD3400AFG676
+refdes=U?
+footprint=FG676
+description=Xilinx Spartan 3A-DSP 1800/3400 FG676
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+AA2 io line l IO_L55P_3
+AA3 io line l IO_L55N_3
+AA5 io line r IP_3/VREF_3
+AB1 io line l IO_L60P_3
+AB2 pwr line b VCCO_3
+AC1 io line l IO_L60N_3
+AC2 io line l IO_L64P_3
+AC3 io line l IO_L64N_3
+AD1 io line l IO_L65P_3
+AD2 io line l IO_L65N_3
+AE1 in line r IP_L66P_3
+AE2 io line r IP_L66N_3/VREF_3
+B1 io line l IO_L02N_3
+B2 io line l IO_L02P_3
+C1 io line r IP_3/VREF_3
+C2 pwr line b VCCO_3
+D3 io line l IO_L06P_3
+E1 io line l IO_L11P_3
+E2 pwr line b VCCO_3
+E3 io line l IO_L07P_3
+E4 io line l IO_L06N_3
+F2 io line l IO_L11N_3
+F3 io line l IO_L14N_3
+F4 io line l IO_L07N_3
+F5 io line l IO_L09P_3
+G1 in line r IP_3
+G3 io line l IO_L14P_3
+G4 io line l IO_L09N_3
+G6 io line l IO_L03P_3
+H1 io line l IO_L17N_3
+H2 io line l IO_L17P_3
+H4 io line r IP_3/VREF_3
+H5 pwr line b VCCO_3
+H6 io line l IO_L10N_3
+H7 io line l IO_L03N_3
+J1 in line r IP_L24P_3
+J2 io line r IP_L20N_3/VREF_3
+J3 in line r IP_L20P_3
+J4 io line l IO_L19N_3
+J5 io line l IO_L19P_3
+J6 io line l IO_L13N_3
+J7 io line l IO_L10P_3
+J8 io line l IO_L01P_3
+J9 io line l IO_L01N_3
+K1 in line r IP_L24N_3
+K2 io line l IO_L23N_3
+K3 io line l IO_L23P_3
+K4 io line l IO_L22N_3
+K5 io line l IO_L22P_3
+K6 io line l IO_L18P_3
+K7 io line l IO_L13P_3
+K8 io line l IO_L05N_3
+K9 io line l IO_L05P_3
+L2 pwr line b VCCO_3
+L3 io line l IO_L25N_3
+L4 io line l IO_L25P_3
+L7 io line l IO_L18N_3
+L8 pwr line b VCCO_3
+L9 io line l IO_L15N_3
+L10 io line l IO_L15P_3
+M1 io line r IO_L29N_3/VREF_3
+M2 io line l IO_L29P_3
+M3 io line l IO_L27N_3
+M4 io line l IO_L27P_3
+M5 io line l IO_L28P_3
+M6 io line l IO_L28N_3
+M7 io line l IO_L26N_3
+M8 io line l IO_L26P_3
+M9 io line l IO_L21N_3
+M10 io line l IO_L21P_3
+N1 io line l IO_L31P_3
+N2 io line l IO_L31N_3
+N4 io line l IO_L30N_3
+N5 io line l IO_L30P_3
+P5 pwr line b VCCO_3
+P6 io line l IO_L39N_3
+P7 io line l IO_L39P_3
+P8 io line l IO_L41P_3
+P9 io line l IO_L41N_3
+R1 io line r IO_L36P_3/VREF_3
+R2 io line l IO_L36N_3
+R3 io line l IO_L37P_3
+R4 io line l IO_L37N_3
+R5 io line l IO_L40P_3
+R6 io line l IO_L40N_3
+R7 io line l IO_L45N_3
+R8 io line l IO_L45P_3
+R9 io line l IO_L43N_3
+R10 io line r IO_L43P_3/VREF_3
+T2 pwr line b VCCO_3
+T3 io line l IO_L38P_3
+T4 io line l IO_L38N_3
+T5 io line l IO_L42P_3
+T7 io line l IO_L51P_3
+T8 pwr line b VCCO_3
+T9 io line l IO_L48N_3
+T10 io line l IO_L48P_3
+U1 io line l IO_L44P_3
+U2 io line l IO_L44N_3
+U3 in line r IP_L46P_3
+U4 io line l IO_L42N_3
+U5 io line l IO_L49P_3
+U6 io line l IO_L51N_3
+U7 io line l IO_L56P_3
+U8 io line l IO_L56N_3
+U9 io line l IO_L61P_3
+V1 io line l IO_L47P_3
+V2 io line l IO_L47N_3
+V4 in line r IP_L46N_3
+V5 io line l IO_L49N_3
+V6 io line l IO_L59N_3
+V7 io line l IO_L59P_3
+V8 io line l IO_L61N_3
+W1 in line r IP_L50P_3
+W2 io line r IP_L50N_3/VREF_3
+W3 io line l IO_L52P_3
+W4 io line l IO_L52N_3
+W5 pwr line b VCCO_3
+W6 io line l IO_L63N_3
+W7 io line l IO_L63P_3
+Y1 io line l IO_L53P_3
+Y2 io line l IO_L53N_3
+Y3 in line r IP_3
+Y5 io line l IO_L57P_3
+Y6 io line l IO_L57N_3
Added: usrp-hw/trunk/sym/generated/xc3sd3400afg676-JTAG.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd3400afg676-JTAG.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd3400afg676-JTAG.src 2008-12-23
08:13:43 UTC (rev 10159)
@@ -0,0 +1,24 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=6000
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD3400AFG676-JTAG
+device=XC3SD3400AFG676
+refdes=U?
+footprint=FG676
+description=Xilinx Spartan 3A-DSP 1800/3400 FG676
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A25 io line l TCK
+D4 io line l TMS
+E23 io line l TDO
+G7 io line l TDI
Added: usrp-hw/trunk/sym/generated/xc3sd3400afg676-LHCLK.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd3400afg676-LHCLK.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd3400afg676-LHCLK.src 2008-12-23
08:13:43 UTC (rev 10159)
@@ -0,0 +1,28 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=6000
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD3400AFG676-LHCLK
+device=XC3SD3400AFG676
+refdes=U?
+footprint=FG676
+description=Xilinx Spartan 3A-DSP 1800/3400 FG676
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+N6 clk clk l IO_L32P_3/LHCLK0
+N7 clk clk l IO_L32N_3/LHCLK1
+N9 clk clk l IO_L35P_3/TRDY2/LHCLK6
+P1 clk clk l IO_L33P_3/LHCLK2
+P2 clk clk l IO_L33N_3/IRDY2/LHCLK3
+P3 clk clk l IO_L34N_3/LHCLK5
+P4 clk clk l IO_L34P_3/LHCLK4
+P10 clk clk l IO_L35N_3/LHCLK7
Added: usrp-hw/trunk/sym/generated/xc3sd3400afg676-PWR.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd3400afg676-PWR.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd3400afg676-PWR.src 2008-12-23 08:13:43 UTC
(rev 10159)
@@ -0,0 +1,180 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=6000
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD3400AFG676-PWR
+device=XC3SD3400AFG676
+refdes=U?
+footprint=FG676
+description=Xilinx Spartan 3A-DSP 1800/3400 FG676
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A1 pwr line r GND
+A5 pwr line r GND
+A6 pwr line r GND
+A11 pwr line r GND
+A16 pwr line r GND
+A21 pwr line r GND
+A23 pwr line r GND
+A24 pwr line l VCCAUX
+A26 pwr line r GND
+AA1 pwr line r GND
+AA4 pwr line r GND
+AA6 pwr line r GND
+AA8 pwr line l VCCINT
+AA11 pwr line r GND
+AA16 pwr line r GND
+AA19 pwr line r GND
+AA21 pwr line r GND
+AA26 pwr line r GND
+AB3 pwr line r GND
+AB4 pwr line l VCCAUX
+AB5 pwr line l VCCAUX
+AB10 pwr line r GND
+AB11 pwr line l VCCAUX
+AB17 pwr line l VCCAUX
+AB20 pwr line r GND
+AB22 pwr line l VCCAUX
+AC5 pwr line r GND
+AC7 pwr line r GND
+AC18 pwr line r GND
+AD3 pwr line r GND
+AD5 pwr line r GND
+AD8 pwr line r GND
+AD13 pwr line r GND
+AD18 pwr line r GND
+AD23 pwr line r GND
+AD24 pwr line r GND
+AF1 pwr line r GND
+AF2 pwr line l VCCAUX
+AF6 pwr line r GND
+AF11 pwr line r GND
+AF16 pwr line r GND
+AF21 pwr line r GND
+AF26 pwr line r GND
+B24 pwr line r GND
+B25 pwr line r GND
+C3 pwr line r GND
+C4 pwr line l VCCINT
+C9 pwr line r GND
+C14 pwr line r GND
+C19 pwr line r GND
+C24 pwr line r GND
+D1 pwr line l VCCAUX
+D2 pwr line r GND
+D5 pwr line l VCCINT
+D15 pwr line r GND
+D19 pwr line r GND
+E5 pwr line l VCCAUX
+E6 pwr line l VCCINT
+E9 pwr line r GND
+E16 pwr line l VCCAUX
+E20 pwr line l VCCAUX
+E22 pwr line l VCCAUX
+F1 pwr line r GND
+F6 pwr line r GND
+F9 pwr line l VCCAUX
+F10 pwr line l VCCINT
+F11 pwr line r GND
+F16 pwr line r GND
+F18 pwr line l VCCINT
+F21 pwr line r GND
+F26 pwr line r GND
+G2 pwr line r GND
+G5 pwr line r GND
+G16 pwr line r GND
+G18 pwr line l VCCINT
+G26 pwr line l VCCAUX
+H3 pwr line r GND
+H8 pwr line r GND
+H14 pwr line r GND
+H19 pwr line r GND
+H23 pwr line l VCCAUX
+J18 pwr line l VCCAUX
+J24 pwr line r GND
+K10 pwr line r GND
+K13 pwr line l VCCAUX
+K15 pwr line l VCCINT
+K17 pwr line r GND
+L1 pwr line r GND
+L5 pwr line l VCCAUX
+L6 pwr line r GND
+L11 pwr line r GND
+L12 pwr line l VCCINT
+L13 pwr line r GND
+L14 pwr line l VCCINT
+L15 pwr line r GND
+L16 pwr line l VCCINT
+L21 pwr line r GND
+L26 pwr line r GND
+M11 pwr line l VCCINT
+M12 pwr line r GND
+M13 pwr line l VCCINT
+M14 pwr line r GND
+M15 pwr line l VCCINT
+M16 pwr line r GND
+M17 pwr line l VCCINT
+N3 pwr line r GND
+N8 pwr line r GND
+N10 pwr line l VCCAUX
+N11 pwr line r GND
+N12 pwr line l VCCINT
+N13 pwr line l VCCINT
+N14 pwr line l VCCINT
+N15 pwr line r GND
+N16 pwr line l VCCINT
+P11 pwr line l VCCINT
+P12 pwr line r GND
+P13 pwr line l VCCINT
+P14 pwr line l VCCINT
+P15 pwr line l VCCINT
+P16 pwr line r GND
+P17 pwr line l VCCAUX
+P19 pwr line r GND
+P24 pwr line r GND
+R11 pwr line r GND
+R12 pwr line l VCCINT
+R13 pwr line r GND
+R14 pwr line l VCCINT
+R15 pwr line r GND
+R16 pwr line l VCCINT
+T1 pwr line r GND
+T6 pwr line r GND
+T11 pwr line l VCCINT
+T12 pwr line r GND
+T13 pwr line l VCCINT
+T14 pwr line r GND
+T15 pwr line l VCCINT
+T16 pwr line r GND
+T21 pwr line r GND
+T22 pwr line l VCCAUX
+T26 pwr line r GND
+U10 pwr line r GND
+U12 pwr line l VCCINT
+U13 pwr line r GND
+U14 pwr line l VCCAUX
+U17 pwr line r GND
+U25 pwr line r GND
+V3 pwr line r GND
+V9 pwr line l VCCAUX
+W8 pwr line r GND
+W14 pwr line r GND
+W18 pwr line l VCCINT
+W19 pwr line r GND
+W24 pwr line r GND
+W25 pwr line r GND
+W26 pwr line l VCCAUX
+Y4 pwr line l VCCINT
+Y8 pwr line l VCCINT
+Y11 pwr line l VCCINT
+Y18 pwr line l VCCINT
+Y19 pwr line l VCCINT
Added: usrp-hw/trunk/sym/generated/xc3sd3400afg676-RHCLK.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd3400afg676-RHCLK.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd3400afg676-RHCLK.src 2008-12-23
08:13:43 UTC (rev 10159)
@@ -0,0 +1,28 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=6000
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD3400AFG676-RHCLK
+device=XC3SD3400AFG676
+refdes=U?
+footprint=FG676
+description=Xilinx Spartan 3A-DSP 1800/3400 FG676
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+N19 clk clk l IO_L34N_1/RHCLK7
+N24 clk clk l IO_L33N_1/RHCLK5
+P18 clk clk l IO_L34P_1/IRDY1/RHCLK6
+P20 clk clk l IO_L30N_1/RHCLK1
+P21 clk clk l IO_L30P_1/RHCLK0
+P23 clk clk l IO_L33P_1/RHCLK4
+P25 clk clk l IO_L31N_1/TRDY1/RHCLK3
+P26 clk clk l IO_L31P_1/RHCLK2
Added: usrp-hw/trunk/sym/generated/xc3sd3400afg676-TOPCLK.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd3400afg676-TOPCLK.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd3400afg676-TOPCLK.src 2008-12-23
08:13:43 UTC (rev 10159)
@@ -0,0 +1,28 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=6000
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD3400AFG676-TOPCLK
+device=XC3SD3400AFG676
+refdes=U?
+footprint=FG676
+description=Xilinx Spartan 3A-DSP 1800/3400 FG676
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A14 clk clk l IO_L26N_0/GCLK7
+B13 clk clk l IO_L28P_0/GCLK10
+B14 clk clk l IO_L26P_0/GCLK6
+C13 clk clk l IO_L28N_0/GCLK11
+F13 clk clk l IO_L27P_0/GCLK8
+G13 clk clk l IO_L27N_0/GCLK9
+J14 clk clk l IO_L25N_0/GCLK5
+K14 clk clk l IO_L25P_0/GCLK4
Added: usrp-hw/trunk/sym/generated/xilinxgen676
===================================================================
--- usrp-hw/trunk/sym/generated/xilinxgen676 (rev 0)
+++ usrp-hw/trunk/sym/generated/xilinxgen676 2008-12-23 08:13:43 UTC (rev
10159)
@@ -0,0 +1,127 @@
+#!/usr/bin/python
+
+import re
+matchstr = re.compile("_")
+
+def writepin(file,number,name,linetype,pintype,pos):
+ #newname = matchstr.sub("\\_",name)
+ newname = name
+ file.write("%s\t\t%s\t%s\t%s\t\t%s\n" %
(number,pintype,linetype,pos,newname))
+
+pinfile = open ('XC3SD3400AFG676.csv','r')
+
+boilerplate = '''
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=6000
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD3400AFG676-%s
+device=XC3SD3400AFG676
+refdes=U?
+footprint=FG676
+description=Xilinx Spartan 3A-DSP 1800/3400 FG676
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+'''
+
+configfile = open ('xc3sd3400afg676-CFG.src', 'w')
+configfile.write(boilerplate % ("CFG",))
+
+jtagfile = open ('xc3sd3400afg676-JTAG.src', 'w')
+jtagfile.write(boilerplate % ("JTAG",))
+powerfile = open ('xc3sd3400afg676-PWR.src', 'w')
+powerfile.write(boilerplate % ("PWR",))
+topclockfile = open ('xc3sd3400afg676-TOPCLK.src', 'w')
+topclockfile.write(boilerplate % ("TOPCLK",))
+botclockfile = open ('xc3sd3400afg676-BOTCLK.src', 'w')
+botclockfile.write(boilerplate % ("BOTCLK",))
+lhclockfile = open ('xc3sd3400afg676-LHCLK.src', 'w')
+lhclockfile.write(boilerplate % ("LHCLK",))
+rhclockfile = open ('xc3sd3400afg676-RHCLK.src', 'w')
+rhclockfile.write(boilerplate % ("RHCLK",))
+
+iofiles = [0] * 4
+for i in range(4):
+ iofiles[i] = open ( ('xc3sd3400afg676-IO%d.src' % (i,)), 'w')
+ iofiles[i].write(boilerplate % ('IO%d' % (i,),))
+
+dummy = pinfile.readline()
+lines = pinfile.readlines()
+
+for line in lines:
+ elements = line.strip().split(',')
+
+ pintype = elements[3]
+ #nc = elements[5] == "N.C."
+
+ #if(elements[5] != elements[9]) and not nc:
+ # print "error"
+ # print elements
+
+ #if nc and pintype != 'I/O' and pintype != 'VREF':
+ # print "error"
+ # print elements
+
+ if(pintype == 'GND'):
+ writepin(powerfile,elements[0],elements[1],'line','pwr','r')
+ elif(pintype == 'VCCAUX'):
+ writepin(powerfile,elements[0],elements[1],'line','pwr','l')
+ elif(pintype == 'VCCO'):
+ #writepin(powerfile,elements[3],elements[6],'line','pwr','l')
+
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','pwr','b')
+ elif(pintype == 'VCCINT'):
+ writepin(powerfile,elements[0],elements[1],'line','pwr','l')
+
+ elif(pintype == 'JTAG'):
+ writepin(jtagfile,elements[0],elements[1],'line','io','l')
+
+ elif(pintype == 'CONFIG'):
+ #writepin(configfile,elements[0],elements[1],'line','io','b')
+ writepin(configfile,elements[0],elements[1],'line','io','l')
+
+ elif(pintype == 'PWRMGMT'):
+ #writepin(configfile,elements[0],elements[1],'line','io','b')
+ writepin(configfile,elements[0],elements[1],'line','io','l')
+
+ elif(pintype == 'DUAL'):
+ if(int(elements[2]) == 1): # All these are for BPI mode, so just put
in bank 1
+
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','io','l')
+ elif(int(elements[2]) == 2):
+ writepin(configfile,elements[0],elements[1],'line','io','r')
+ else:
+ writepin(configfile,elements[0],elements[1],'line','io','l')
+
+ elif(pintype == 'GCLK'):
+ if(int(elements[2]) == 0):
+ writepin(topclockfile,elements[0],elements[1],'clk','clk','l')
+ else:
+ writepin(botclockfile,elements[0],elements[1],'clk','clk','l')
+
+ elif(pintype == 'LHCLK'):
+ writepin(lhclockfile,elements[0],elements[1],'clk','clk','l')
+
+ elif(pintype == 'RHCLK'):
+ writepin(rhclockfile,elements[0],elements[1],'clk','clk','l')
+
+ elif(pintype == 'VREF'):
+
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','io','r')
+
+ elif(pintype == 'I/O'):
+
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','io','l')
+
+ elif(pintype == 'INPUT'):
+
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','in','r')
+
+ elif(pintype == 'DCI'):
+ writepin(iofiles[int(elements[12])],elements[3],"%s/DCI" %
(elements[6],),'line','io','l')
+
+ else:
+ print elements
Property changes on: usrp-hw/trunk/sym/generated/xilinxgen676
___________________________________________________________________
Name: svn:executable
+ *
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