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[Commit-gnuradio] r10140 - in gnuradio/branches/developers/n4hy/pfb_fbs/
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From: |
n4hy |
|
Subject: |
[Commit-gnuradio] r10140 - in gnuradio/branches/developers/n4hy/pfb_fbs/usrp2: firmware firmware/apps firmware/include firmware/lib fpga/control_lib fpga/extram fpga/sdr_lib fpga/serdes fpga/timing fpga/top/u2_core fpga/top/u2_rev2 fpga/top/u2_rev3 host/include/usrp2 host/lib |
|
Date: |
Fri, 19 Dec 2008 19:42:22 -0700 (MST) |
Author: n4hy
Date: 2008-12-19 19:42:20 -0700 (Fri, 19 Dec 2008)
New Revision: 10140
Added:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/_exit.c
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/extram/extram_interface.v
Removed:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/rx_only_v2.c
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/test_serdes.c
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/tx_only_v2.c
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/extram_interface.v
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/Makefile.common
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/Makefile.am
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/app_common_v2.c
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/app_common_v2.h
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/factory_test.c
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/serdes_txrx.c
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/txrx.c
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/include/usrp2_eth_packet.h
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/include/usrp2_types.h
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/Makefile.am
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/clocks.c
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/clocks.h
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/db_init.c
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/db_rfx.c
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/db_tvrx.c
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/dbsm.c
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/hal_uart.c
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/hal_uart.h
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/memory_map.h
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/u2_init.c
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/icache.v
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/longfifo.v
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/ram_harv_cache.v
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/shortfifo.v
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/sdr_lib/dsp_core_rx.v
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/sdr_lib/dsp_core_tx.v
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/serdes/serdes.v
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/serdes/serdes_rx.v
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/timing/time_sync.v
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_core/u2_core.v
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_rev2/Makefile
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_rev2/u2_rev2.v
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_rev3/Makefile
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/include/usrp2/usrp2.h
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/control.h
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/usrp2.cc
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/usrp2_impl.cc
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/usrp2_impl.h
Log:
last one!
Property changes on: gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware
___________________________________________________________________
Name: svn:ignore
- *-stamp
*.a
*.bin
*.dump
*.log
*.rom
.deps
Makefile
Makefile.in
aclocal.m4
autom4te.cache
blink_leds
blink_leds2
build
compile
config.h
config.h.in
config.log
config.status
configure
depcomp
eth_test
gen_eth_packets
ibs_rx_test
ibs_tx_test
install-sh
libtool
ltmain.sh
missing
py-compile
rcv_eth_packets
run_tests.sh
stamp-h1
test1
test_phy_comm
timer_test
buf_ram_test
buf_ram_zero
hello
+ *-stamp
*.a
*.bin
*.dump
*.log
*.rom
.deps
Makefile
Makefile.in
aclocal.m4
autom4te.cache
blink_leds
blink_leds2
build
compile
config.h
config.h.in
config.log
config.status
configure
depcomp
eth_test
gen_eth_packets
ibs_rx_test
ibs_tx_test
install-sh
libtool
ltmain.sh
missing
py-compile
rcv_eth_packets
run_tests.sh
stamp-h1
test1
test_phy_comm
timer_test
buf_ram_test
buf_ram_zero
hello
configure.lineno
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/Makefile.common
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/Makefile.common
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/Makefile.common
2008-12-20 02:42:20 UTC (rev 10140)
@@ -23,12 +23,10 @@
AM_CPPFLAGS = $(HAL_IO) $(STD_INCLUDES)
-STD_CFLAGS = -O2 -g -Wall -Werror-implicit-function-declaration -mxl-soft-div
-msoft-float
+STD_CFLAGS = -Wall -Werror-implicit-function-declaration -mxl-soft-div
-msoft-float
-#AM_CFLAGS = $(STD_CFLAGS) -mxl-soft-mul
-AM_CFLAGS = $(STD_CFLAGS) -mxl-soft-mul -mxl-barrel-shift
-#AM_CFLAGS = $(STD_CFLAGS) -mno-xl-soft-mul
-#AM_CFLAGS = $(STD_CFLAGS) -mno-xl-soft-mul -mxl-barrel-shift
+AM_CFLAGS = $(STD_CFLAGS) -mxl-soft-mul -mxl-barrel-shift
+#AM_CFLAGS = $(STD_CFLAGS) -mxl-soft-mul -mxl-barrel-shift -mxl-gp-opt -G 16384
LINKER_SCRIPT = $(top_srcdir)/lib/microblaze.ld
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/Makefile.am
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/Makefile.am
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/Makefile.am
2008-12-20 02:42:20 UTC (rev 10140)
@@ -31,7 +31,6 @@
ibs_rx_test \
ibs_tx_test \
rcv_eth_packets \
- rx_only_v2 \
read_dbids \
set_hw_rev \
test1 \
@@ -42,9 +41,7 @@
test_phy_comm \
test_lsadc \
test_lsdac \
- test_serdes \
timer_test \
- tx_only_v2 \
tx_standalone \
txrx \
factory_test \
@@ -56,8 +53,6 @@
# tx_drop_SOURCES = tx_drop.c app_common.c
# tx_drop_rate_limited_SOURCES = tx_drop_rate_limited.c app_common.c
# tx_drop2_SOURCES = tx_drop2.c app_common.c
-rx_only_v2_SOURCES = rx_only_v2.c app_common_v2.c
-tx_only_v2_SOURCES = tx_only_v2.c app_common_v2.c
txrx_SOURCES = txrx.c app_common_v2.c
factory_test_SOURCES = factory_test.c app_common_v2.c
eth_serdes_SOURCES = eth_serdes.c app_passthru_v2.c
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/app_common_v2.c
===================================================================
---
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/app_common_v2.c
2008-12-20 02:41:31 UTC (rev 10139)
+++
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/app_common_v2.c
2008-12-20 02:42:20 UTC (rev 10140)
@@ -27,6 +27,7 @@
#include "nonstdio.h"
#include "print_rmon_regs.h"
#include "db.h"
+#include "db_base.h"
#include "clocks.h"
#include "u2_init.h"
#include <string.h>
@@ -39,7 +40,6 @@
static unsigned char exp_seqno __attribute__((unused)) = 0;
-
static bool
burn_mac_addr(const op_burn_mac_addr_t *p)
{
@@ -47,6 +47,14 @@
}
static bool
+sync_to_pps(const op_generic_t *p)
+{
+ timesync_regs->sync_on_next_pps = 1;
+ putstr("SYNC to PPS\n");
+ return true;
+}
+
+static bool
config_mimo_cmd(const op_config_mimo_t *p)
{
clocks_mimo_config(p->flags);
@@ -89,7 +97,7 @@
}
if (0){
- printf("sending_reply to port %d, len = %d\n", cpu_tx_buf_dest_port,
reply_len);
+ printf("sending_reply to port %d, len = %d\n", cpu_tx_buf_dest_port,
(int)reply_len);
print_buffer(buffer_ram(CPU_TX_BUF), reply_len/4);
}
@@ -122,8 +130,6 @@
// r->fpga_md5sum = ; // FIXME
// r->sw_md5sum = ; // FIXME
- // FIXME Add d'board info, including dbid, min/max gain, min/max freq
-
return r->len;
}
@@ -146,10 +152,17 @@
}
if (p->valid & CFGV_FREQ){
+ bool was_streaming = is_streaming();
+ if (was_streaming)
+ stop_rx_cmd();
+
u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo);
bool tune_ok = db_tune(tx_dboard, f, &tune_result);
ok &= tune_ok;
print_tune_result("Tx", tune_ok, f, &tune_result);
+
+ if (was_streaming)
+ restart_streaming();
}
if (p->valid & CFGV_INTERP_DECIM){
@@ -167,7 +180,7 @@
interp = interp >> 1;
}
- if (p->interp < MIN_INTERP || p->interp > MAX_INTERP)
+ if (interp < MIN_INTERP || interp > MAX_INTERP)
ok = false;
else {
dsp_tx_regs->interp_rate = (hb1<<9) | (hb2<<8) | interp;
@@ -213,10 +226,17 @@
}
if (p->valid & CFGV_FREQ){
+ bool was_streaming = is_streaming();
+ if (was_streaming)
+ stop_rx_cmd();
+
u2_fxpt_freq_t f = u2_fxpt_freq_from_hilo(p->freq_hi, p->freq_lo);
bool tune_ok = db_tune(rx_dboard, f, &tune_result);
ok &= tune_ok;
print_tune_result("Rx", tune_ok, f, &tune_result);
+
+ if (was_streaming)
+ restart_streaming();
}
if (p->valid & CFGV_INTERP_DECIM){
@@ -279,7 +299,39 @@
return r->len;
}
+static void
+fill_db_info(u2_db_info_t *p, const struct db_base *db)
+{
+ p->dbid = db->dbid;
+ p->freq_min_hi = u2_fxpt_freq_hi(db->freq_min);
+ p->freq_min_lo = u2_fxpt_freq_lo(db->freq_min);
+ p->freq_max_hi = u2_fxpt_freq_hi(db->freq_max);
+ p->freq_max_lo = u2_fxpt_freq_lo(db->freq_max);
+ p->gain_min = db->gain_min;
+ p->gain_max = db->gain_max;
+ p->gain_step_size = db->gain_step_size;
+}
+
static size_t
+dboard_info_cmd(const op_generic_t *p,
+ void *reply_payload, size_t reply_payload_space)
+{
+ op_dboard_info_reply_t *r = (op_dboard_info_reply_t *) reply_payload;
+ if (reply_payload_space < sizeof(*r))
+ return 0; // no room
+
+ r->opcode = OP_DBOARD_INFO_REPLY;
+ r->len = sizeof(*r);
+ r->rid = p->rid;
+ r->ok = true;
+
+ fill_db_info(&r->tx_db_info, tx_dboard);
+ fill_db_info(&r->rx_db_info, rx_dboard);
+
+ return r->len;
+}
+
+static size_t
generic_reply(const op_generic_t *p,
void *reply_payload, size_t reply_payload_space,
bool ok)
@@ -374,6 +426,15 @@
subpktlen = read_time_cmd(gp, reply_payload, reply_payload_space);
break;
+ case OP_DBOARD_INFO:
+ subpktlen = dboard_info_cmd(gp, reply_payload, reply_payload_space);
+ break;
+
+ case OP_SYNC_TO_PPS:
+ subpktlen = generic_reply(gp, reply_payload, reply_payload_space,
+ sync_to_pps((op_generic_t *) payload));
+ break;
+
default:
printf("app_common_v2: unhandled opcode = %d\n", gp->opcode);
break;
@@ -469,10 +530,12 @@
print_tune_result(char *msg, bool tune_ok,
u2_fxpt_freq_t target_freq, struct tune_result *r)
{
+#if 0
printf("db_tune %s %s\n", msg, tune_ok ? "true" : "false");
putstr(" target_freq "); print_fxpt_freq(target_freq); newline();
putstr(" baseband_freq "); print_fxpt_freq(r->baseband_freq); newline();
putstr(" dxc_freq "); print_fxpt_freq(r->dxc_freq); newline();
putstr(" residual_freq "); print_fxpt_freq(r->residual_freq); newline();
printf(" inverted %s\n", r->inverted ? "true" : "false");
+#endif
}
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/app_common_v2.h
===================================================================
---
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/app_common_v2.h
2008-12-20 02:41:31 UTC (rev 10139)
+++
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/app_common_v2.h
2008-12-20 02:42:20 UTC (rev 10140)
@@ -56,6 +56,8 @@
void start_rx_streaming_cmd(const u2_mac_addr_t *host, op_start_rx_streaming_t
*p);
void stop_rx_cmd(void);
+void restart_streaming(void);
+bool is_streaming(void);
void handle_control_chan_frame(u2_eth_packet_t *pkt, size_t len);
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/factory_test.c
===================================================================
---
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/factory_test.c
2008-12-20 02:41:31 UTC (rev 10139)
+++
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/factory_test.c
2008-12-20 02:42:20 UTC (rev 10140)
@@ -37,6 +37,8 @@
#include <string.h>
#include <i2c.h>
#include <usrp2_i2c_addr.h>
+#include <clocks.h>
+#include "sd.h"
#define HW_REV_MAJOR 3
#define HW_REV_MINOR 0
@@ -127,11 +129,12 @@
static int streaming_frame_count = 0;
#define FRAMES_PER_CMD 1000
+bool is_streaming(void){ return streaming_p; }
// ----------------------------------------------------------------
-static void
+void
restart_streaming(void)
{
// setup RX DSP regs
@@ -254,12 +257,79 @@
dbsm_process_status(&dsp_rx_sm, status);
}
+int test_ram()
+{
+ int i,j,k;
+ output_regs->ram_page = 1<<10;
+
+ extram[0] = 0xDEADBEEF;
+ extram[1] = 0xF00D1234;
+ extram[7] = 0x76543210;
+
+ output_regs->ram_page = 2<<10;
+ extram[7] = 0x55555555;
+ extram[1] = 0xaaaaaaaa;
+ extram[0] = 0xeeeeeeee;
+
+ output_regs->ram_page = 1<<10;
+
+ i = extram[0];
+ k = extram[1];
+ j = extram[7];
+
+ if((i != 0xDEADBEEF)||(j!=0x76543210)||(k!=0xF00D1234)) {
+ puts("RAM FAIL1!\n");
+ puthex32_nl(i);
+ puthex32_nl(j);
+ puthex32_nl(k);
+ return 0;
+ }
+
+ output_regs->ram_page = 2<<10;
+
+ j = extram[7];
+ k = extram[1];
+ i = extram[0];
+
+ if((i != 0xeeeeeeee)||(j!=0x55555555)||(k!=0xaaaaaaaa)) {
+ puts("RAM FAIL2!\n");
+ puthex32_nl(i);
+ puthex32_nl(j);
+ puthex32_nl(k);
+ return 0;
+ }
+ return 1;
+}
+
+int test_sd()
+{
+ int i = sd_init();
+ if(i==0) {
+ puts("FAILED INIT of Card\n");
+ return 0;
+ }
+
+ unsigned char buf[512];
+ i = sd_read_block(2048,buf);
+ if(i == 0) {
+ puts("READ Command Rejected\n");
+ return 0;
+ }
+ if((buf[0]==0xb8)&&(buf[1]==0x08)&&(buf[2]==0x00)&&(buf[3]==0x50))
+ ;
+ else {
+ puts("Read bad data from SD Card\n");
+ return 0;
+ }
+ return 1;
+}
+
int
main(void)
{
u2_init();
- putstr("\nset_hw_rev\n");
+ putstr("\nFactory Test TXRX\n");
bool ok = true;
unsigned char maj = HW_REV_MAJOR;
@@ -267,19 +337,40 @@
ok = eeprom_write(I2C_ADDR_MBOARD, MBOARD_REV_MSB, &maj, 1);
ok &= eeprom_write(I2C_ADDR_MBOARD, MBOARD_REV_LSB, &min, 1);
+ putstr("\nset_hw_rev\n");
if (ok)
printf("OK: set h/w rev to %d.%d\n", HW_REV_MAJOR, HW_REV_MINOR);
- else
+ else {
printf("FAILED to set h/w rev to %d.%d\n", HW_REV_MAJOR, HW_REV_MINOR);
+ hal_finish();
+ return 0;
+ }
- putstr("\nFactory Test TXRX\n");
+ if(test_sd())
+ puts("SD OK\n");
+ else {
+ puts("SD FAIL\n");
+ hal_finish();
+ return 0;
+ }
+ if(test_ram())
+ puts("RAM OK\n");
+ else {
+ puts("RAM FAIL\n");
+ hal_finish();
+ return 0;
+ }
+
print_mac_addr(ethernet_mac_addr()->addr);
newline();
+ output_regs->led_src = 0x7; // make bottom 3 controlled by HW
+
ethernet_register_link_changed_callback(link_changed_callback);
ethernet_init();
-
+ clocks_enable_tx_dboard(true,1);
+ clocks_mimo_config(MC_WE_LOCK_TO_SMA);
#if 0
// make bit 15 of Tx gpio's be a s/w output
hal_gpio_set_sel(GPIO_TX_BANK, 15, 's');
Deleted:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/rx_only_v2.c
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/serdes_txrx.c
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/serdes_txrx.c
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/serdes_txrx.c
2008-12-20 02:42:20 UTC (rev 10140)
@@ -124,11 +124,12 @@
static int streaming_frame_count = 0;
#define FRAMES_PER_CMD 1000
+bool is_streaming(void){ return streaming_p; }
// ----------------------------------------------------------------
-static void
+void
restart_streaming(void)
{
// setup RX DSP regs
Deleted:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/test_serdes.c
Deleted:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/tx_only_v2.c
Modified: gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/txrx.c
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/txrx.c
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/apps/txrx.c
2008-12-20 02:42:20 UTC (rev 10140)
@@ -35,8 +35,8 @@
#include <stddef.h>
#include <stdlib.h>
#include <string.h>
+#include "clocks.h"
-
#define FW_SETS_SEQNO 1 // define to 0 or 1 (FIXME must be 1 for now)
#if (FW_SETS_SEQNO)
@@ -123,11 +123,13 @@
static int streaming_frame_count = 0;
#define FRAMES_PER_CMD 1000
+bool is_streaming(void){ return streaming_p; }
+
// ----------------------------------------------------------------
-static void
+void
restart_streaming(void)
{
// setup RX DSP regs
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/include/usrp2_eth_packet.h
===================================================================
---
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/include/usrp2_eth_packet.h
2008-12-20 02:41:31 UTC (rev 10139)
+++
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/include/usrp2_eth_packet.h
2008-12-20 02:42:20 UTC (rev 10140)
@@ -181,6 +181,10 @@
#define OP_STOP_RX_REPLY (OP_STOP_RX | OP_REPLY_BIT)
#define OP_CONFIG_MIMO 8
#define OP_CONFIG_MIMO_REPLY (OP_CONFIG_MIMO | OP_REPLY_BIT)
+#define OP_DBOARD_INFO 9
+#define OP_DBOARD_INFO_REPLY (OP_DBOARD_INFO | OP_REPLY_BIT)
+#define OP_SYNC_TO_PPS 10
+#define OP_SYNC_TO_PPS_REPLY (OP_SYNC_TO_PPS | OP_REPLY_BIT)
//#define OP_WRITE_REG xx // not implemented
@@ -199,7 +203,7 @@
*
* Used by:
* OP_EOP, OP_BURN_MAC_ADDR_REPLY, OP_START_RX_STREAMING_REPLY,
- * OP_STOP_RX_REPLY
+ * OP_STOP_RX_REPLY, OP_DBOARD_INFO
*/
typedef struct {
uint8_t opcode;
@@ -348,6 +352,36 @@
} op_config_mimo_t;
+/*!
+ * \brief High-level information about daughterboards
+ */
+typedef struct {
+ int32_t dbid; //< d'board ID (-1 none, -2 invalid eeprom)
+ uint32_t freq_min_hi; //< high 32-bits of 64-bit fxpt_freq (Q44.20)
+ uint32_t freq_min_lo; //< low 32-bits of 64-bit fxpt_freq (Q44.20)
+ uint32_t freq_max_hi; //< high 32-bits of 64-bit fxpt_freq (Q44.20)
+ uint32_t freq_max_lo; //< low 32-bits of 64-bit fxpt_freq (Q44.20)
+ uint16_t gain_min; //< min gain that can be set. fxpt_db (Q9.7)
+ uint16_t gain_max; //< max gain that can be set. fxpt_db (Q9.7)
+ uint16_t gain_step_size; //< fxpt_db (Q9.7)
+} u2_db_info_t;
+
+
+/*!
+ * \brief Reply to d'board info request
+ */
+typedef struct {
+ uint8_t opcode;
+ uint8_t len;
+ uint8_t rid;
+ uint8_t ok; // request was successful (bool)
+
+ u2_db_info_t tx_db_info;
+ u2_db_info_t rx_db_info;
+} _AL4 op_dboard_info_reply_t;
+
+
+
/*
* ================================================================
* union of all of subpacket types
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/include/usrp2_types.h
===================================================================
---
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/include/usrp2_types.h
2008-12-20 02:41:31 UTC (rev 10139)
+++
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/include/usrp2_types.h
2008-12-20 02:42:20 UTC (rev 10140)
@@ -99,7 +99,13 @@
return ((double) fx) * 1.0/(1 << U2_FPG_RP);
}
+static inline int
+u2_fxpt_gain_round_to_int(u2_fxpt_gain_t fx)
+{
+ return (int)((fx+(1<<(U2_FPG_RP-1)))>>U2_FPG_RP);
+}
+
__U2_END_DECLS
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/Makefile.am
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/Makefile.am
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/Makefile.am
2008-12-20 02:42:20 UTC (rev 10140)
@@ -34,6 +34,8 @@
eeprom.c \
ethernet.c \
eth_mac.c \
+ _exit.c \
+ exit.c \
hal_io.c \
hal_uart.c \
i2c.c \
Copied: gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/_exit.c
(from rev 10133, gnuradio/trunk/usrp2/firmware/lib/_exit.c)
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/_exit.c
(rev 0)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/_exit.c
2008-12-20 02:42:20 UTC (rev 10140)
@@ -0,0 +1,27 @@
+/* -*- c++ -*- */
+/*
+ * Copyright 2008 Free Software Foundation, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * Stub so we can compile using 3.4 based mb-gcc
+ */
+void
+_exit(int status)
+{
+ while (1)
+ ;
+}
Modified: gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/clocks.c
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/clocks.c
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/clocks.c
2008-12-20 02:42:20 UTC (rev 10140)
@@ -52,14 +52,13 @@
// Set up other clocks
- clocks_enable_test_clk(false);
+ clocks_enable_test_clk(false, 0);
clocks_enable_tx_dboard(false, 0);
clocks_enable_rx_dboard(false, 0);
// ETH phy clock
ad9510_write_reg(0x41, 0x01); // Turn off output 5 (phy_clk)
ad9510_write_reg(0x53, 0x80); // Bypass divider
- ad9510_write_reg(0x5A, 0x01); // Update Regs
// Enable clock to ADCs and DACs
ad9510_write_reg(0x3F, 0x00); // Turn on output 3 (DAC CLK), normal levels
@@ -129,54 +128,55 @@
ad9510_write_reg(0x5A, 0x01); // Update Regs
}
-void
-clocks_enable_test_clk(bool enable)
+int inline
+clocks_gen_div(int divisor)
{
- if (enable){
- ad9510_write_reg(0x3C, 0x08); // Turn on output 0 -- Test output
- ad9510_write_reg(0x49, 0x80); // Bypass divider 0
- }
- else {
- ad9510_write_reg(0x3C, 0x02); // Turn off output 0
- }
- ad9510_write_reg(0x5A, 0x01); // Update Regs
+ int L,H;
+ L = (divisor>>1)-1;
+ H = divisor-L-2;
+ return (L<<4)|H;
}
+#define CLOCK_OUT_EN 0x08
+#define CLOCK_OUT_DIS_CMOS 0x01
+#define CLOCK_OUT_DIS_PECL 0x02
+#define CLOCK_DIV_DIS 0x80
+#define CLOCK_DIV_EN 0x00
-void
-clocks_enable_rx_dboard(bool enable, int divisor)
+void
+clocks_enable_XXX_clk(bool enable, int divisor, int reg_en, int reg_div, int
val_off)
{
- if (enable){
- ad9510_write_reg(0x43, 0x08); // enable output 7 (db_rx_clk), CMOS
-
- if (divisor == 0){
- ad9510_write_reg(0x57, 0x80); // Bypass Div #7, 100 MHz clock
+ if(enable) {
+ ad9510_write_reg(reg_en,CLOCK_OUT_EN); // Turn on output, normal levels
+ if(divisor>1) {
+ ad9510_write_reg(reg_div,clocks_gen_div(divisor)); // Set divisor
+ ad9510_write_reg(reg_div+1,CLOCK_DIV_EN); // Enable divider
}
else {
- // FIXME Matt, do something with divisor...
+ ad9510_write_reg(reg_div+1,CLOCK_DIV_DIS); // Disable Divider
}
}
else {
- ad9510_write_reg(0x43, 0x01); // Turn off output 7 (db_rx_clk)
+ ad9510_write_reg(reg_en,val_off); // Power off output (val different for
PECL/CMOS)
+ ad9510_write_reg(reg_div+1,CLOCK_DIV_DIS); // Bypass Divider to power it
down
}
- ad9510_write_reg(0x5A, 0x01); // Update Regs
+ ad9510_write_reg(0x5A, 0x01); // Update Regs
}
+void
+clocks_enable_test_clk(bool enable, int divisor)
+{
+ clocks_enable_XXX_clk(enable,divisor,0x3C,0x48,CLOCK_OUT_DIS_PECL);
+}
void
+clocks_enable_rx_dboard(bool enable, int divisor)
+{
+ clocks_enable_XXX_clk(enable,divisor,0x43,0x56,CLOCK_OUT_DIS_CMOS);
+}
+
+void
clocks_enable_tx_dboard(bool enable, int divisor)
{
- if (enable){
- ad9510_write_reg(0x42, 0x08); // enable output 6 (db_tx_clk), CMOS
- if (divisor == 0) {
- ad9510_write_reg(0x55, 0x80); // Bypass Div #6, 100 MHz clock
- }
- else {
- // FIXME Matt, do something with divisor
- }
- }
- else {
- ad9510_write_reg(0x42, 0x01); // Turn off output 6 (db_tx_clk)
- }
- ad9510_write_reg(0x5A, 0x01); // Update Regs
+ clocks_enable_XXX_clk(enable,divisor,0x42,0x54,CLOCK_OUT_DIS_CMOS);
}
Modified: gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/clocks.h
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/clocks.h
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/clocks.h
2008-12-20 02:42:20 UTC (rev 10140)
@@ -46,7 +46,7 @@
/*!
* \brief Enable or disable test clock (extra clock signal)
*/
-void clocks_enable_test_clk(bool enable);
+void clocks_enable_test_clk(bool enable, int divisor);
/*!
* \brief Enable or disable clock to Rx daughterboard
Modified: gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/db_init.c
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/db_init.c
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/db_init.c
2008-12-20 02:42:20 UTC (rev 10140)
@@ -37,6 +37,14 @@
extern struct db_base db_lf_rx;
extern struct db_base db_rfx_400_tx;
extern struct db_base db_rfx_400_rx;
+extern struct db_base db_rfx_900_tx;
+extern struct db_base db_rfx_900_rx;
+extern struct db_base db_rfx_1200_tx;
+extern struct db_base db_rfx_1200_rx;
+extern struct db_base db_rfx_1800_tx;
+extern struct db_base db_rfx_1800_rx;
+extern struct db_base db_rfx_2400_tx;
+extern struct db_base db_rfx_2400_rx;
extern struct db_base db_tvrx1;
extern struct db_base db_tvrx2;
extern struct db_base db_tvrx3;
@@ -48,6 +56,14 @@
&db_lf_rx,
&db_rfx_400_tx,
&db_rfx_400_rx,
+ &db_rfx_900_tx,
+ &db_rfx_900_rx,
+ &db_rfx_1200_tx,
+ &db_rfx_1200_rx,
+ &db_rfx_1800_tx,
+ &db_rfx_1800_rx,
+ &db_rfx_2400_tx,
+ &db_rfx_2400_rx,
&db_tvrx1,
&db_tvrx2,
&db_tvrx3,
@@ -123,14 +139,18 @@
{
struct db_base *db;
int dbid = read_dboard_eeprom(i2c_addr);
+
+ // FIXME removing this printf has the system hang if there are two d'boards
+ // installed. (I think the problem is in i2c_read/write or the way
+ // I kludge the zero-byte write to set the read address in eeprom_read.)
printf("%s dbid: 0x%x\n", msg, dbid);
if (dbid < 0){ // there was some kind of problem. Treat as Basic Tx
return default_db;
}
else if ((db = lookup_dbid(dbid)) == 0){
+ printf("No daugherboard code for dbid = 0x%x\n", dbid);
return default_db;
- printf("No daugherboard code for dbid = 0x%x\n", dbid);
}
return db;
}
@@ -180,19 +200,77 @@
}
}
+static int __attribute__((unused))
+determine_tx_mux_value(struct db_base *db)
+{
+ if (db->i_and_q_swapped)
+ return 0x01;
+ else
+ return 0x10;
+}
+
+static int
+determine_rx_mux_value(struct db_base *db)
+{
+#define ADC0 0x0
+#define ADC1 0x1
+#define ZERO 0x2
+
+ static int truth_table[8] = {
+ /* swap_iq, uses */
+ /* 0, 0x0 */ (ZERO << 2) | ZERO, // N/A
+ /* 0, 0x1 */ (ZERO << 2) | ADC0,
+ /* 0, 0x2 */ (ZERO << 2) | ADC1,
+ /* 0, 0x3 */ (ADC1 << 2) | ADC0,
+ /* 1, 0x0 */ (ZERO << 2) | ZERO, // N/A
+ /* 1, 0x1 */ (ZERO << 2) | ADC0,
+ /* 1, 0x2 */ (ZERO << 2) | ADC1,
+ /* 1, 0x3 */ (ADC0 << 2) | ADC1,
+ };
+
+ int subdev0_uses;
+ int subdev1_uses;
+ int uses;
+
+ if (db->is_quadrature)
+ subdev0_uses = 0x3; // uses A/D 0 and 1
+ else
+ subdev0_uses = 0x1; // uses A/D 0 only
+
+ // FIXME second subdev on Basic Rx, LF RX
+ // if subdev2 exists
+ // subdev1_uses = 0x2;
+ subdev1_uses = 0;
+
+ uses = subdev0_uses;
+
+ int swap_iq = db->i_and_q_swapped & 0x1;
+ int index = (swap_iq << 2) | uses;
+
+ return truth_table[index];
+}
+
+
void
db_init(void)
{
+ int m;
tx_dboard = lookup_dboard(I2C_ADDR_TX_A, &db_basic_tx, "Tx");
//printf("db_init: tx dbid = 0x%x\n", tx_dboard->dbid);
set_gpio_mode(GPIO_TX_BANK, tx_dboard);
tx_dboard->init(tx_dboard);
+ //m = determine_tx_mux_value(tx_dboard);
+ //dsp_tx_regs->tx_mux = m;
+ //printf("tx_mux = 0x%x\n", m);
rx_dboard = lookup_dboard(I2C_ADDR_RX_A, &db_basic_rx, "Rx");
//printf("db_init: rx dbid = 0x%x\n", rx_dboard->dbid);
set_gpio_mode(GPIO_RX_BANK, rx_dboard);
rx_dboard->init(rx_dboard);
+ m = determine_rx_mux_value(rx_dboard);
+ dsp_rx_regs->rx_mux = m;
+ //printf("rx_mux = 0x%x\n", m);
}
/*!
@@ -238,17 +316,16 @@
}
}
else {
- while (delta < -fs){
+ while (delta < -fs)
delta += fs;
- if (delta >= -fs/2){ // non-inverted region
- *dxc_freq = -delta;
- *inverted = false;
- }
- else { // inverted region
- *dxc_freq = delta + fs;
- *inverted = true;
- }
+ if (delta >= -fs/2){ // non-inverted region
+ *dxc_freq = -delta;
+ *inverted = false;
}
+ else { // inverted region
+ *dxc_freq = delta + fs;
+ *inverted = true;
+ }
}
}
Modified: gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/db_rfx.c
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/db_rfx.c
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/db_rfx.c
2008-12-20 02:42:20 UTC (rev 10140)
@@ -72,7 +72,8 @@
unsigned char CP1;
unsigned char CP2;
int freq_mult;
- int spi_mask;
+ int spi_mask;
+ u2_fxpt_freq_t freq_offset;
};
struct db_rfx_dummy {
@@ -140,13 +141,13 @@
.base.is_tx = false,
.base.output_enables = 0x00E0,
.base.used_pins = 0x00FF,
- //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
- //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
- //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(400e6),
+ .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(500e6),
+ .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(45),
+ .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.022),
.base.is_quadrature = true,
- .base.i_and_q_swapped = false,
+ .base.i_and_q_swapped = true,
.base.spectrum_inverted = false,
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_rx,
@@ -162,7 +163,8 @@
.common.CP1 = 7,
.common.CP2 = 7,
.common.spi_mask = SPI_SS_RX_DB,
- .common.freq_mult = 2
+ .common.freq_mult = 2,
+ .common.freq_offset = U2_DOUBLE_TO_FXPT_FREQ(0)
};
@@ -171,13 +173,13 @@
.base.is_tx = true,
.base.output_enables = 0x00E0,
.base.used_pins = 0x00FF,
- //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
- //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(400e6),
+ .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(500e6),
//.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
//.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
//.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
.base.is_quadrature = true,
- .base.i_and_q_swapped = false,
+ .base.i_and_q_swapped = true,
.base.spectrum_inverted = false,
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_tx,
@@ -193,7 +195,8 @@
.common.CP1 = 7,
.common.CP2 = 7,
.common.spi_mask = SPI_SS_TX_DB,
- .common.freq_mult = 2
+ .common.freq_mult = 2,
+ .common.freq_offset = U2_DOUBLE_TO_FXPT_FREQ(12.5e6)
};
struct db_rfx_900_rx db_rfx_900_rx = {
@@ -201,13 +204,13 @@
.base.is_tx = false,
.base.output_enables = 0x00E0,
.base.used_pins = 0x00FF,
- //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
- //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
- //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(800e6),
+ .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1000e6),
+ .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(70),
+ .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.034),
.base.is_quadrature = true,
- .base.i_and_q_swapped = false,
+ .base.i_and_q_swapped = true,
.base.spectrum_inverted = false,
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_rx,
@@ -223,7 +226,8 @@
.common.CP1 = 7,
.common.CP2 = 7,
.common.spi_mask = SPI_SS_RX_DB,
- .common.freq_mult = 2
+ .common.freq_mult = 2,
+ .common.freq_offset = U2_DOUBLE_TO_FXPT_FREQ(0)
};
@@ -232,13 +236,13 @@
.base.is_tx = true,
.base.output_enables = 0x00E0,
.base.used_pins = 0x00FF,
- //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
- //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(800e6),
+ .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1000e6),
//.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
//.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
//.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
.base.is_quadrature = true,
- .base.i_and_q_swapped = false,
+ .base.i_and_q_swapped = true,
.base.spectrum_inverted = false,
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_tx,
@@ -254,7 +258,8 @@
.common.CP1 = 7,
.common.CP2 = 7,
.common.spi_mask = SPI_SS_TX_DB,
- .common.freq_mult = 2
+ .common.freq_mult = 2,
+ .common.freq_offset = U2_DOUBLE_TO_FXPT_FREQ(12.5e6)
};
struct db_rfx_1200_rx db_rfx_1200_rx = {
@@ -262,13 +267,13 @@
.base.is_tx = false,
.base.output_enables = 0x00E0,
.base.used_pins = 0x00FF,
- //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
- //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
- //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(1150e6),
+ .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1350e6),
+ .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(70),
+ .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.034),
.base.is_quadrature = true,
- .base.i_and_q_swapped = false,
+ .base.i_and_q_swapped = true,
.base.spectrum_inverted = false,
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_rx,
@@ -284,7 +289,8 @@
.common.CP1 = 7,
.common.CP2 = 7,
.common.spi_mask = SPI_SS_RX_DB,
- .common.freq_mult = 2
+ .common.freq_mult = 2,
+ .common.freq_offset = U2_DOUBLE_TO_FXPT_FREQ(0)
};
@@ -293,13 +299,13 @@
.base.is_tx = true,
.base.output_enables = 0x00E0,
.base.used_pins = 0x00FF,
- //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
- //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(1150e6),
+ .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(1350e6),
//.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
//.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
//.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
.base.is_quadrature = true,
- .base.i_and_q_swapped = false,
+ .base.i_and_q_swapped = true,
.base.spectrum_inverted = false,
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_tx,
@@ -315,7 +321,8 @@
.common.CP1 = 7,
.common.CP2 = 7,
.common.spi_mask = SPI_SS_TX_DB,
- .common.freq_mult = 2
+ .common.freq_mult = 2,
+ .common.freq_offset = U2_DOUBLE_TO_FXPT_FREQ(12.5e6)
};
struct db_rfx_1800_rx db_rfx_1800_rx = {
@@ -323,13 +330,13 @@
.base.is_tx = false,
.base.output_enables = 0x00E0,
.base.used_pins = 0x00FF,
- //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
- //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
- //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(1600e6),
+ .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2000e6),
+ .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(70),
+ .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.034),
.base.is_quadrature = true,
- .base.i_and_q_swapped = false,
+ .base.i_and_q_swapped = true,
.base.spectrum_inverted = false,
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_rx,
@@ -345,7 +352,8 @@
.common.CP1 = 7,
.common.CP2 = 7,
.common.spi_mask = SPI_SS_RX_DB,
- .common.freq_mult = 1
+ .common.freq_mult = 1,
+ .common.freq_offset = U2_DOUBLE_TO_FXPT_FREQ(0)
};
@@ -354,13 +362,13 @@
.base.is_tx = true,
.base.output_enables = 0x00E0,
.base.used_pins = 0x00FF,
- //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
- //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(1600e6),
+ .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2000e6),
//.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
//.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
//.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
.base.is_quadrature = true,
- .base.i_and_q_swapped = false,
+ .base.i_and_q_swapped = true,
.base.spectrum_inverted = false,
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_tx,
@@ -376,7 +384,8 @@
.common.CP1 = 7,
.common.CP2 = 7,
.common.spi_mask = SPI_SS_TX_DB,
- .common.freq_mult = 1
+ .common.freq_mult = 1,
+ .common.freq_offset = U2_DOUBLE_TO_FXPT_FREQ(12.5e6)
};
@@ -385,13 +394,13 @@
.base.is_tx = false,
.base.output_enables = 0x00E0,
.base.used_pins = 0x00FF,
- //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
- //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
- //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(2300e6),
+ .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2700e6),
+ .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(70),
+ .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0.034),
.base.is_quadrature = true,
- .base.i_and_q_swapped = false,
+ .base.i_and_q_swapped = true,
.base.spectrum_inverted = false,
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_rx,
@@ -407,7 +416,8 @@
.common.CP1 = 7,
.common.CP2 = 7,
.common.spi_mask = SPI_SS_RX_DB,
- .common.freq_mult = 1
+ .common.freq_mult = 1,
+ .common.freq_offset = U2_DOUBLE_TO_FXPT_FREQ(0)
};
@@ -416,13 +426,13 @@
.base.is_tx = true,
.base.output_enables = 0x00E0,
.base.used_pins = 0x00FF,
- //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
- //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(2300e6),
+ .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(2700e6),
//.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
//.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
//.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
.base.is_quadrature = true,
- .base.i_and_q_swapped = false,
+ .base.i_and_q_swapped = true,
.base.spectrum_inverted = false,
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_tx,
@@ -438,7 +448,8 @@
.common.CP1 = 7,
.common.CP2 = 7,
.common.spi_mask = SPI_SS_TX_DB,
- .common.freq_mult = 1
+ .common.freq_mult = 1,
+ .common.freq_offset = U2_DOUBLE_TO_FXPT_FREQ(12.5e6)
};
@@ -447,6 +458,10 @@
{
//struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
clocks_enable_tx_dboard(true, 0);
+
+ // Set the freq now to get the one time 10ms delay out of the way.
+ u2_fxpt_freq_t dc;
+ dbb->set_freq(dbb, dbb->freq_min, &dc);
return true;
}
@@ -458,18 +473,22 @@
// test gain
dbb->set_gain(dbb,U2_DOUBLE_TO_FXPT_GAIN(45.0));
- printf("set the gain\n");
+
+ // Set the freq now to get the one time 10ms delay out of the way.
+ u2_fxpt_freq_t dc;
+ dbb->set_freq(dbb, dbb->freq_min, &dc);
+
return true;
}
bool
rfx_set_freq(struct db_base *dbb, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc)
{
+ static unsigned char first = true;
+
*dc = 0;
struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
- //u2_fxpt_freq_t desired_n = db->common.freq_mult*freq/phdet_freq;
- //int N_DIV = u2_fxpt_freq_round_to_int(desired_n);
- u2_fxpt_freq_t desired_n = ((1LL<<20) *
db->common.freq_mult*freq)/phdet_freq;
+ u2_fxpt_freq_t desired_n =
((1LL<<20)*db->common.freq_mult*(freq+db->common.freq_offset))/phdet_freq;
int N_DIV = u2_fxpt_freq_round_to_int(desired_n);
int B = N_DIV/PRESCALER;
int A = N_DIV - PRESCALER*B;
@@ -484,10 +503,13 @@
spi_transact(SPI_TXONLY,db->common.spi_mask,R,24,SPIF_PUSH_FALL);
spi_transact(SPI_TXONLY,db->common.spi_mask,C,24,SPIF_PUSH_FALL);
- mdelay(10);
+ if (first){
+ first = false;
+ mdelay(10);
+ }
spi_transact(SPI_TXONLY,db->common.spi_mask,N,24,SPIF_PUSH_FALL);
- printf("A = %d, B = %d, N_DIV = %d\n",A, B, N_DIV);
+ //printf("A = %d, B = %d, N_DIV = %d\n",A, B, N_DIV);
*dc = (N_DIV * phdet_freq) / db->common.freq_mult;
return true;
}
@@ -504,43 +526,14 @@
{
struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
- u2_fxpt_gain_t MAXGAIN = U2_DOUBLE_TO_FXPT_GAIN(70.0);
-
int offset_q8 = (int)(1.2/3.3*4096*(1<<15));
- int slope_q8 = (int)(-1.0/45.0*4096/3.3*256);
+ int range_q15 = (int)(-1.0*4096/3.3*256*128);
+ int slope_q8 = range_q15/db->base.gain_max;
+
int dacword = ((slope_q8 * gain) + offset_q8)>>15;
- printf("DACWORD %d\n",dacword);
+ //printf("DACWORD %d\n",dacword);
lsdac_write_rx(1,dacword);
return true;
- /*
- def set_gain(self, gain):
- """
- Set the gain.
-
- @param gain: gain in decibels
- @returns True/False
- """
- maxgain = self.gain_range()[1] - self._u.pga_max()
- mingain = self.gain_range()[0]
- if gain > maxgain:
- pga_gain = gain-maxgain
- assert pga_gain <= self._u.pga_max()
- agc_gain = maxgain
- else:
- pga_gain = 0
- agc_gain = gain
- V_maxgain = .2
- V_mingain = 1.2
- V_fullscale = 3.3
- dac_value = (agc_gain*(V_maxgain-V_mingain)/(maxgain-mingain) +
V_mingain)*4096/V_fullscale
- assert dac_value>=0 and dac_value<4096
- return self._u.write_aux_dac(self._which, 0, int(dac_value)) and \
- self._set_pga(int(pga_gain))
-
- def gain_range(self):
- return (self._u.pga_min(), self._u.pga_max() + 70, 0.05) -- For
900-2400
- return (self._u.pga_min(), self._u.pga_max() + 45, 0.035) -- For 400
- */
}
Modified: gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/db_tvrx.c
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/db_tvrx.c
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/db_tvrx.c
2008-12-20 02:42:20 UTC (rev 10140)
@@ -23,7 +23,6 @@
#include <hal_io.h>
#include <ad9510.h>
#include <stdio.h>
-#include <mdelay.h>
bool tvrx_init(struct db_base *db);
bool tvrx_set_freq(struct db_base *db, u2_fxpt_freq_t freq, u2_fxpt_freq_t
*dc);
@@ -83,9 +82,9 @@
.base.used_pins = 0x0000,
.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(50e6),
.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(860e6),
- //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+ .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(95),
+ .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(1),
.base.is_quadrature = false,
.base.i_and_q_swapped = false,
.base.spectrum_inverted = false,
@@ -110,12 +109,12 @@
.base.used_pins = 0x0000,
.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(50e6),
.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(860e6),
- //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+ .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(95),
+ .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(1),
.base.is_quadrature = false,
.base.i_and_q_swapped = false,
- .base.spectrum_inverted = false,
+ .base.spectrum_inverted = true,
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = tvrx_init,
.base.set_freq = tvrx_set_freq,
@@ -137,12 +136,12 @@
.base.used_pins = 0x0000,
.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(50e6),
.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(860e6),
- //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
- //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+ .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(95),
+ .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(1),
.base.is_quadrature = false,
.base.i_and_q_swapped = false,
- .base.spectrum_inverted = false,
+ .base.spectrum_inverted = true,
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = tvrx_init,
.base.set_freq = tvrx_set_freq,
@@ -182,10 +181,12 @@
if(N_DIV > 32767)
return false;
- printf("N_DIV = %d, actual_freq = %d, actual_lo_freq = %d\n",
- N_DIV,
u2_fxpt_freq_round_to_int(actual_freq),u2_fxpt_freq_round_to_int(actual_freq));
+ if (0)
+ printf("N_DIV = %d, actual_freq = %d, actual_lo_freq = %d\n",
+ N_DIV, u2_fxpt_freq_round_to_int(actual_freq),
+ u2_fxpt_freq_round_to_int(actual_lo_freq));
- char buf[4];
+ unsigned char buf[4];
buf[0] = (N_DIV>>8) & 0xff;
buf[1] = N_DIV & 0xff;
buf[2] = control_byte_1;
@@ -200,7 +201,7 @@
bool
tvrx_set_gain(struct db_base *dbb, u2_fxpt_gain_t gain)
{
- struct db_tvrx_dummy *db = (struct db_tvrx_dummy *) dbb;
+ //struct db_tvrx_dummy *db = (struct db_tvrx_dummy *) dbb;
int rfgain;
int ifgain;
if(gain>U2_DOUBLE_TO_FXPT_GAIN(95.0))
@@ -227,7 +228,9 @@
lsdac_write_rx(0,rfdac);
lsdac_write_rx(1,ifdac);
- printf("Setting gain %d, rf %d, if %d\n",gain,rfdac,ifdac);
+ if (0)
+ printf("Setting gain %d, rf %d, if %d\n",gain,rfdac,ifdac);
+
return true;
}
@@ -235,6 +238,6 @@
bool
tvrx_lock_detect(struct db_base *dbb)
{
- struct db_tvrx_dummy *db = (struct db_tvrx_dummy *) dbb;
+ // struct db_tvrx_dummy *db = (struct db_tvrx_dummy *) dbb;
return true;
}
Modified: gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/dbsm.c
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/dbsm.c
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/dbsm.c
2008-12-20 02:42:20 UTC (rev 10140)
@@ -177,50 +177,48 @@
{
int buf_other = buf_this ^ 1;
- if (1){
- bp_clear_buf(buf_this);
+ bp_clear_buf(buf_this);
- if (buffer_state[buf_this] == BS_FILLING){
- buffer_state[buf_this] = BS_FULL;
- //
- // does s/w handle this packet?
- //
- if (sm->inspect(sm, buf_this)){
- // s/w handled the packet; refill the buffer
- dbsm_receive_to_buf(sm, buf_this);
- buffer_state[buf_this] = BS_FILLING;
- }
+ if (buffer_state[buf_this] == BS_FILLING){
+ buffer_state[buf_this] = BS_FULL;
+ //
+ // does s/w handle this packet?
+ //
+ if (sm->inspect(sm, buf_this)){
+ // s/w handled the packet; refill the buffer
+ dbsm_receive_to_buf(sm, buf_this);
+ buffer_state[buf_this] = BS_FILLING;
+ }
- else { // s/w didn't handle this; pass it on
+ else { // s/w didn't handle this; pass it on
- if(buffer_state[buf_other] == BS_EMPTY){
- dbsm_receive_to_buf(sm, buf_other);
- buffer_state[buf_other] = BS_FILLING;
- }
- else
- sm->rx_idle = true;
+ if(buffer_state[buf_other] == BS_EMPTY){
+ dbsm_receive_to_buf(sm, buf_other);
+ buffer_state[buf_other] = BS_FILLING;
+ }
+ else
+ sm->rx_idle = true;
- if (sm->tx_idle){
- sm->tx_idle = false;
- dbsm_send_from_buf(sm, buf_this);
- buffer_state[buf_this] = BS_EMPTYING;
- }
+ if (sm->tx_idle){
+ sm->tx_idle = false;
+ dbsm_send_from_buf(sm, buf_this);
+ buffer_state[buf_this] = BS_EMPTYING;
}
}
- else { // buffer was emptying
- buffer_state[buf_this] = BS_EMPTY;
- if (sm->rx_idle){
- sm->rx_idle = false;
- dbsm_receive_to_buf(sm, buf_this);
- buffer_state[buf_this] = BS_FILLING;
- }
- if (buffer_state[buf_other] == BS_FULL){
- dbsm_send_from_buf(sm, buf_other);
- buffer_state[buf_other] = BS_EMPTYING;
- }
- else
- sm->tx_idle = true;
+ }
+ else { // buffer was emptying
+ buffer_state[buf_this] = BS_EMPTY;
+ if (sm->rx_idle){
+ sm->rx_idle = false;
+ dbsm_receive_to_buf(sm, buf_this);
+ buffer_state[buf_this] = BS_FILLING;
}
+ if (buffer_state[buf_other] == BS_FULL){
+ dbsm_send_from_buf(sm, buf_other);
+ buffer_state[buf_other] = BS_EMPTYING;
+ }
+ else
+ sm->tx_idle = true;
}
}
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/hal_uart.c
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/hal_uart.c
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/hal_uart.c
2008-12-20 02:42:20 UTC (rev 10140)
@@ -57,6 +57,16 @@
u->txchar = ch;
}
+void
+hal_uart_putc_nowait(int ch)
+{
+ if (ch == '\n') // FIXME for now map \n -> \r\n
+ hal_uart_putc('\r');
+
+ if(u->txlevel) // If fifo has space
+ u->txchar = ch;
+}
+
int
hal_uart_getc(void)
{
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/hal_uart.h
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/hal_uart.h
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/hal_uart.h
2008-12-20 02:42:20 UTC (rev 10140)
@@ -54,6 +54,11 @@
*/
void hal_uart_putc(int ch);
+/*!
+ * \brief Enqueue \p ch for output over serial port, silent fail if queue is
full
+ */
+void hal_uart_putc_nowait(int ch);
+
/*
* \brief Blocking read of next char from serial port
*/
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/memory_map.h
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/memory_map.h
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/memory_map.h
2008-12-20 02:42:20 UTC (rev 10140)
@@ -354,6 +354,8 @@
volatile uint32_t phy_ctrl; // LSB is reset line to eth phy
volatile uint32_t debug_mux_ctrl;
volatile uint32_t ram_page; // FIXME should go somewhere else...
+ volatile uint32_t flush_icache; // Flush the icache
+ volatile uint32_t led_src; // HW or SW control for LEDs
} output_regs_t;
#define SERDES_ENABLE 8
@@ -377,6 +379,42 @@
volatile uint32_t interp_rate;
volatile uint32_t clear_state; // clears out state machine, fifos,
// NOT freq, scale, interp
+ /*!
+ * \brief output mux configuration.
+ *
+ * <pre>
+ * 3 2 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-------------------------------+-------+-------+-------+-------+
+ * | | DAC1 | DAC0 |
+ * +-------------------------------+-------+-------+-------+-------+
+ *
+ * There are N DUCs (1 now) with complex inputs and outputs.
+ * There are two DACs.
+ *
+ * Each 4-bit DACx field specifies the source for the DAC
+ * Each subfield is coded like this:
+ *
+ * 3 2 1 0
+ * +-------+
+ * | N |
+ * +-------+
+ *
+ * N specifies which DUC output is connected to this DAC.
+ *
+ * N which interp output
+ * --- -------------------
+ * 0 DUC 0 I
+ * 1 DUC 0 Q
+ * 2 DUC 1 I
+ * 3 DUC 1 Q
+ * F All Zeros
+ *
+ * The default value is 0x10
+ * </pre>
+ */
+ volatile uint32_t tx_mux;
+
} dsp_tx_regs_t;
#define dsp_tx_regs ((dsp_tx_regs_t *) DSP_TX_BASE)
@@ -399,8 +437,30 @@
volatile uint32_t dcoffset_i; // Bit 31 high sets fixed offset mode,
using lower 14 bits,
// otherwise it is automatic
volatile uint32_t dcoffset_q; // Bit 31 high sets fixed offset mode,
using lower 14 bits
- volatile uint32_t adc_mux; // 4 bits -- lowest 2 for adc_i, next
for adc_q
+ /*!
+ * \brief input mux configuration.
+ *
+ * This determines which ADC (or constant zero) is connected to
+ * each DDC input. There are N DDCs (1 now). Each has two inputs.
+ *
+ * <pre>
+ * Mux value:
+ *
+ * 3 2 1
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-------+-------+-------+-------+-------+-------+-------+-------+
+ * | |Q0 |I0 |
+ * +-------+-------+-------+-------+-------+-------+-------+-------+
+ *
+ * Each 2-bit I field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
+ * Each 2-bit Q field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
+ *
+ * The default value is 0x4
+ * </pre>
+ */
+ volatile uint32_t rx_mux; // called adc_mux in dsp_core_rx.v
+
} dsp_rx_regs_t;
#define dsp_rx_regs ((dsp_rx_regs_t *) DSP_RX_BASE)
@@ -482,6 +542,8 @@
#define IRQ_PPS 7 // pulse per second
#define IRQ_UART_RX 8
#define IRQ_UART_TX 9
+#define IRQ_SERDES 10
+#define IRQ_CLKSTATUS 11
#define IRQ_TO_MASK(x) (1 << (x))
@@ -495,8 +557,9 @@
#define PIC_PPS_INT IRQ_TO_MASK(IRQ_PPS)
#define PIC_UART_RX_INT IRQ_TO_MASK(IRQ_UART_RX)
#define PIC_UART_TX_INT IRQ_TO_MASK(IRQ_UART_TX)
+#define PIC_SERDES IRQ_TO_MASK(IRQ_SERDES)
+#define PIC_CLKSTATUS IRQ_TO_MASK(IRQ_CLKSTATUS)
-
typedef struct {
volatile uint32_t edge_enable; // mask: 1 -> edge triggered, 0 -> level
volatile uint32_t polarity; // mask: 1 -> rising edge
@@ -559,6 +622,7 @@
volatile uint32_t tick_control;
volatile uint32_t tick_interval;
volatile uint32_t delta_time;
+ volatile uint32_t sync_on_next_pps;
} timesync_regs_t;
#define timesync_regs ((timesync_regs_t *) TIMESYNC_BASE)
Modified: gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/u2_init.c
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/u2_init.c
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/firmware/lib/u2_init.c
2008-12-20 02:42:20 UTC (rev 10140)
@@ -67,7 +67,7 @@
// set up the default clocks
clocks_init();
- // clocks_enable_test_clk(true);
+ // clocks_enable_test_clk(true,1);
// Enable ADCs
output_regs->adc_ctrl = ADC_CTRL_ON;
@@ -87,6 +87,10 @@
ad9777_write_reg(11, 0); // Q dac offset
ad9777_write_reg(12, 0);
+ // Initial values for tx and rx mux registers
+ dsp_tx_regs->tx_mux = 0x10;
+ dsp_rx_regs->rx_mux = 0x44444444;
+
// Set up serdes
output_regs->serdes_ctrl = (SERDES_ENABLE | SERDES_RXEN);
Deleted:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/extram_interface.v
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/icache.v
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/icache.v
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/icache.v
2008-12-20 02:42:20 UTC (rev 10140)
@@ -11,7 +11,8 @@
output iwb_ack_o,
input [31:0] iram_dat_i,
output [AWIDTH-1:0] iram_adr_o,
- output iram_en_o );
+ output iram_en_o,
+ input flush);
localparam TAGWIDTH = AWIDTH-CWIDTH-2;
reg stb_d1, ack_d1, miss_d1;
@@ -28,7 +29,7 @@
// Write into cache
integer i;
always @(posedge wb_clk_i)
- if(wb_rst_i)
+ if(wb_rst_i | flush)
for(i=0;i<(1<<CWIDTH);i=i+1)
ivalid[i] <= 0;
else
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/longfifo.v
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/longfifo.v
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/longfifo.v
2008-12-20 02:42:20 UTC (rev 10140)
@@ -15,8 +15,8 @@
input clear,
output full,
output empty,
- output [15:0] space,
- output [15:0] occupied);
+ output reg [15:0] space,
+ output reg [15:0] occupied);
// Read side states
localparam EMPTY = 0;
@@ -26,12 +26,6 @@
reg [SIZE-1:0] wr_addr, rd_addr;
reg [1:0] read_state;
- wire [SIZE-1:0] fullness = wr_addr - rd_addr; // Approximate, for
simulation only
- assign occupied = {{16-SIZE{1'b0}},fullness};
-
- wire [SIZE-1:0] free_space = rd_addr - wr_addr - 2; // Approximate, for
SERDES flow control
- assign space = {{16-SIZE{1'b0}},free_space};
-
reg empty_reg, full_reg;
always @(posedge clk)
if(rst)
@@ -43,7 +37,7 @@
ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
ram (.clka(clk),
- .ena(1),
+ .ena(1'b1),
.wea(write),
.addra(wr_addr),
.dia(datain),
@@ -118,5 +112,39 @@
// assign full = ((rd_addr - 1) == wr_addr);
assign full = full_reg;
+
+ //////////////////////////////////////////////
+ // space and occupied are for diagnostics only
+ // not guaranteed exact
+
+ localparam NUMLINES = (1<<SIZE)-2;
+ always @(posedge clk)
+ if(rst)
+ space <= NUMLINES;
+ else if(clear)
+ space <= NUMLINES;
+ else if(read & ~write)
+ space <= space + 1;
+ else if(write & ~read)
+ space <= space - 1;
+ always @(posedge clk)
+ if(rst)
+ occupied <= 0;
+ else if(clear)
+ occupied <= 0;
+ else if(read & ~write)
+ occupied <= occupied - 1;
+ else if(write & ~read)
+ occupied <= occupied + 1;
+
+ /*
+ wire [SIZE-1:0] fullness = wr_addr - rd_addr; // Approximate, for
simulation only
+ assign occupied = {{16-SIZE{1'b0}},fullness};
+
+ wire [SIZE-1:0] free_space = rd_addr - wr_addr - 2; // Approximate, for
SERDES flow control
+ assign space = {{16-SIZE{1'b0}},free_space};
+ */
+
+
endmodule // longfifo
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/ram_harv_cache.v
===================================================================
---
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/ram_harv_cache.v
2008-12-20 02:41:31 UTC (rev 10139)
+++
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/ram_harv_cache.v
2008-12-20 02:42:20 UTC (rev 10140)
@@ -25,8 +25,10 @@
input dwb_we_i,
output dwb_ack_o,
input dwb_stb_i,
- input [3:0] dwb_sel_i );
+ input [3:0] dwb_sel_i,
+ input flush_icache );
+
wire [31:0] iram_dat, dram_dat_i, dram_dat_o;
wire [AWIDTH-1:0] iram_adr, dram_adr;
wire iram_en, dram_en, dram_we;
@@ -60,7 +62,8 @@
icache(.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i),
.iwb_adr_i(iwb_adr_i),.iwb_stb_i(iwb_stb_i),
.iwb_dat_o(iwb_dat_o),.iwb_ack_o(iwb_ack_o),
- .iram_dat_i(iram_dat),.iram_adr_o(iram_adr),.iram_en_o(iram_en) );
+ .iram_dat_i(iram_dat),.iram_adr_o(iram_adr),.iram_en_o(iram_en),
+ .flush(flush_icache));
// RAM loader
assign ram_loader_ack_o = ram_loader_stb_i;
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/shortfifo.v
===================================================================
---
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/shortfifo.v
2008-12-20 02:41:31 UTC (rev 10139)
+++
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/control_lib/shortfifo.v
2008-12-20 02:42:20 UTC (rev 10140)
@@ -9,8 +9,8 @@
input clear,
output reg full,
output reg empty,
- output [4:0] space,
- output [4:0] occupied);
+ output reg [4:0] space,
+ output reg [4:0] occupied);
reg [3:0] a;
genvar i;
@@ -57,7 +57,31 @@
// NOTE will fail if you write into a full fifo or read from an empty one
- assign space = full ? 0 : empty ? 16 : 15-a;
- assign occupied = empty ? 0 : full ? 16 : a+1;
+ //////////////////////////////////////////////////////////////
+ // space and occupied are used for diagnostics, not
+ // guaranteed correct
+ //assign space = full ? 0 : empty ? 16 : 15-a;
+ //assign occupied = empty ? 0 : full ? 16 : a+1;
+
+ always @(posedge clk)
+ if(rst)
+ space <= 16;
+ else if(clear)
+ space <= 16;
+ else if(read & ~write)
+ space <= space + 1;
+ else if(write & ~read)
+ space <= space - 1;
+
+ always @(posedge clk)
+ if(rst)
+ occupied <= 0;
+ else if(clear)
+ occupied <= 0;
+ else if(read & ~write)
+ occupied <= occupied - 1;
+ else if(write & ~read)
+ occupied <= occupied + 1;
+
endmodule // shortfifo
Copied:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/extram/extram_interface.v
(from rev 10133, gnuradio/trunk/usrp2/fpga/extram/extram_interface.v)
===================================================================
---
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/extram/extram_interface.v
(rev 0)
+++
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/extram/extram_interface.v
2008-12-20 02:42:20 UTC (rev 10140)
@@ -0,0 +1,53 @@
+
+// Temporary buffer pool storage, mostly useful for pre-generated data streams
or
+// for making more space to juggle packets in case of eth frames coming out
of order
+
+module extram_interface
+ (input clk, input rst,
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+ // Buffer pool interfaces
+ input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output
rd_error_o,
+ input rd_sop_i, input rd_eop_i,
+ output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output
wr_error_o,
+ input wr_ready_i, input wr_full_i,
+
+ // RAM Interface
+ inout [17:0] RAM_D,
+ output [18:0] RAM_A,
+ output RAM_CE1n,
+ output RAM_CENn,
+ input RAM_CLK,
+ output RAM_WEn,
+ output RAM_OEn,
+ output RAM_LDn );
+
+ // Command format --
+ // Read/_Write , start address[17:0]
+ wire [18:0] cmd_in;
+ wire cmd_stb, store_wr_cmd, store_rd_cmd, read_wr_cmd, read_rd_cmd;
+ wire empty_wr_cmd, empty_rd_cmd, full_wr_cmd, full_rd_cmd;
+
+ // Dummy logic
+ assign RAM_OEn = 1;
+
+ setting_reg #(.my_addr(0))
+ sr_ram_cmd (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(cmd_in),.changed(cmd_stb));
+
+ reg cmd_stb_d1;
+ always @(posedge clk) cmd_stb_d1 <= cmd_stb;
+ assign store_wr_cmd = ~cmd_in[18] & cmd_stb & ~cmd_stb_d1;
+ assign store_rd_cmd = cmd_in[18] & cmd_stb & ~cmd_stb_d1;
+
+ shortfifo #(.WIDTH(19)) wr_cmd_fifo
+ (.clk(clk),.rst(rst),.clear(1'b0),
+ .datain(cmd_in), .write(store_wr_cmd), .full(full_wr_cmd),
+ .dataout(), .read(read_wr_cmd), .empty(empty_wr_cmd) );
+
+ shortfifo #(.WIDTH(19)) rd_cmd_fifo
+ (.clk(clk),.rst(rst),.clear(1'b0),
+ .datain(cmd_in), .write(store_rd_cmd), .full(full_rd_cmd),
+ .dataout(), .read(read_rd_cmd), .empty(empty_rd_cmd) );
+
+endmodule // extram_interface
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/sdr_lib/dsp_core_rx.v
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/sdr_lib/dsp_core_rx.v
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/sdr_lib/dsp_core_rx.v
2008-12-20 02:42:20 UTC (rev 10140)
@@ -56,17 +56,26 @@
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(muxctrl),.changed());
+ // The TVRX connects to what is called adc_b, thus A and B are
+ // swapped throughout the design.
+ //
+ // In the interest of expediency and keeping the s/w sane, we just remap
them here.
+ // The I & Q fields are mapped the same:
+ // 0 -> "the real A" (as determined by the TVRX)
+ // 1 -> "the real B"
+ // 2 -> const zero
+
always @(posedge clk)
- case(muxctrl[1:0])
- 0: adc_i <= adc_a_ofs;
- 1: adc_i <= adc_b_ofs;
+ case(muxctrl[1:0]) // The I mapping
+ 0: adc_i <= adc_b_ofs; // "the real A"
+ 1: adc_i <= adc_a_ofs;
2: adc_i <= 0;
default: adc_i <= 0;
endcase // case(muxctrl[1:0])
always @(posedge clk)
- case(muxctrl[3:2])
- 0: adc_q <= adc_b_ofs;
+ case(muxctrl[3:2]) // The Q mapping
+ 0: adc_q <= adc_b_ofs; // "the real A"
1: adc_q <= adc_a_ofs;
2: adc_q <= 0;
default: adc_q <= 0;
@@ -75,7 +84,9 @@
always @(posedge clk)
if(rst)
phase <= 0;
- else if(run)
+ else if(~run)
+ phase <= 0;
+ else
phase <= phase + phase_inc;
MULT18X18S mult_i
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/sdr_lib/dsp_core_tx.v
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/sdr_lib/dsp_core_tx.v
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/sdr_lib/dsp_core_tx.v
2008-12-20 02:42:20 UTC (rev 10140)
@@ -19,7 +19,7 @@
wire [31:0] phase_inc;
reg [31:0] phase;
wire [7:0] interp_rate;
-
+ wire [3:0] dacmux_a, dacmux_b;
wire enable_hb1, enable_hb2;
setting_reg #(.my_addr(`DSP_CORE_TX_BASE+0)) sr_0
@@ -34,6 +34,10 @@
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed());
+ setting_reg #(.my_addr(`DSP_CORE_TX_BASE+4)) sr_4
+ (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out({dacmux_b,dacmux_a}),.changed());
+
// Strobes are all now delayed by 1 cycle for timing reasons
wire strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre;
reg strobe_cic = 1;
@@ -54,11 +58,13 @@
always @(posedge clk) strobe_hb2 <= strobe_hb2_pre;
always @(posedge clk) strobe_cic <= strobe_cic_pre;
- // DDC
+ // NCO
always @(posedge clk)
if(rst)
phase <= 0;
- else if(run)
+ else if(~run)
+ phase <= 0;
+ else
phase <= phase + phase_inc;
wire signed [17:0] da, db;
@@ -122,11 +128,19 @@
);
always @(posedge clk)
- dac_a <= prod_i[28:13];
+ case(dacmux_a)
+ 0 : dac_a <= prod_i[28:13];
+ 1 : dac_a <= prod_q[28:13];
+ default : dac_a <= 0;
+ endcase // case(dacmux_a)
always @(posedge clk)
- dac_b <= prod_q[28:13];
-
+ case(dacmux_b)
+ 0 : dac_b <= prod_i[28:13];
+ 1 : dac_b <= prod_q[28:13];
+ default : dac_b <= 0;
+ endcase // case(dacmux_b)
+
assign debug = {strobe_cic, strobe_hb1, strobe_hb2,run};
endmodule // dsp_core
Modified: gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/serdes/serdes.v
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/serdes/serdes.v
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/serdes/serdes.v
2008-12-20 02:42:20 UTC (rev 10140)
@@ -16,6 +16,8 @@
output [15:0] tx_occupied, output tx_full, output tx_empty,
output [15:0] rx_occupied, output rx_full, output rx_empty,
+
+ output serdes_link_up,
output [31:0] debug0,
output [31:0] debug1);
@@ -40,7 +42,7 @@
.wr_ready_i(wr_ready_i),.wr_full_i(wr_full_i),
.fifo_space(fifo_space), .xon_rcvd(xon_rcvd), .xoff_rcvd(xoff_rcvd),
.fifo_occupied(rx_occupied),.fifo_full(rx_full),.fifo_empty(rx_empty),
- .debug(debug_rx) );
+ .serdes_link_up(serdes_link_up), .debug(debug_rx) );
serdes_fc_tx serdes_fc_tx
(.clk(clk),.rst(rst),
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/serdes/serdes_rx.v
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/serdes/serdes_rx.v
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/serdes/serdes_rx.v
2008-12-20 02:42:20 UTC (rev 10140)
@@ -42,6 +42,7 @@
output xon_rcvd, output xoff_rcvd,
output [15:0] fifo_occupied, output fifo_full, output fifo_empty,
+ output reg serdes_link_up,
output [31:0] debug
);
@@ -336,18 +337,16 @@
assign wr_dat_o = line_o;
- /*
- assign debug = { { fifo_space[15:8] },
- { fifo_space[7:0] },
- { 2'd0, error_i, sop_i, eop_i, error_o, sop_o, eop_o },
- { full, empty, write, read, xfer_active, state[2:0] } };
+ wire slu = ~({2'b11,K_ERROR}=={ser_rkmsb,ser_rklsb,ser_r});
+ reg [3:0] slu_reg;
+
+ always @(posedge clk)
+ if(rst) slu_reg <= 0;
+ else slu_reg <= {slu_reg[2:0],slu};
- assign debug = { { xoff_rcvd,xon_rcvd,sop_i,eop_i,error_i,state[2:0] },
- { odd, wait_here, write_pre, write_d, write, full,
chosen_data[17:16]},
- { chosen_data[15:8] },
- { chosen_data[7:0] } };
- */
-
+ always @(posedge clk)
+ serdes_link_up <= &slu_reg[3:1];
+
assign debug = { full, empty, odd, xfer_active, sop_i, eop_i, error_i,
state[2:0] };
endmodule // serdes_rx
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/timing/time_sync.v
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/timing/time_sync.v
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/timing/time_sync.v
2008-12-20 02:42:20 UTC (rev 10140)
@@ -5,8 +5,11 @@
input cyc_i, input stb_i, input [2:0] adr_i,
input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o,
input sys_clk_i, output [31:0] master_time_o,
- input pps_in, input exp_pps_in, output exp_pps_out,
- output reg int_o );
+ input pps_posedge, input pps_negedge,
+ input exp_pps_in, output exp_pps_out,
+ output reg int_o,
+ output reg epoch_o,
+ output reg pps_o );
wire [31:0] master_time_rcvd;
reg [31:0] master_time;
@@ -18,6 +21,8 @@
wire tick_free_run;
reg tick_int_enable, tick_source, external_sync;
reg [31:0] tick_interval;
+ reg sync_on_next_pps;
+ reg pps_edge;
// Generate master time
always @(posedge sys_clk_i)
@@ -25,6 +30,8 @@
master_time <= 0;
else if(external_sync & sync_rcvd)
master_time <= master_time_rcvd + delta_time;
+ else if(pps_ext & sync_on_next_pps)
+ master_time <= 0;
else
master_time <= master_time + 1;
assign master_time_o = master_time;
@@ -42,7 +49,10 @@
.exp_pps_in(exp_pps_in) );
assign ack_o = stb_i;
-
+ wire wb_write = cyc_i & stb_i & we_i;
+ wire wb_read = cyc_i & stb_i & ~we_i;
+ wire wb_acc = cyc_i & stb_i;
+
always @(posedge wb_clk_i)
if(rst_i)
begin
@@ -51,18 +61,33 @@
external_sync <= 0;
tick_interval <= 100000-1; // default to 1K times per second
delta_time <= 0;
+ pps_edge <= 0;
end
- else if(stb_i & we_i)
- if(adr_i[2:0] == 2)
- delta_time <= dat_i;
- else if(adr_i[2:0] == 1)
- tick_interval <= dat_i;
- else
- begin
- tick_source <= dat_i[0];
- tick_int_enable <= dat_i[1];
- external_sync <= dat_i[2];
- end
+ else if(wb_write)
+ case(adr_i[2:0])
+ 3'd0 :
+ begin
+ tick_source <= dat_i[0];
+ tick_int_enable <= dat_i[1];
+ external_sync <= dat_i[2];
+ pps_edge <= dat_i[3];
+ end
+ 3'd1 :
+ tick_interval <= dat_i;
+ 3'd2 :
+ delta_time <= dat_i;
+ 3'd3 :
+ ;
+ // Do nothing here, this is to arm the sync_on_next
+ endcase // case(adr_i[2:0])
+
+ always @(posedge sys_clk_i)
+ if(rst_i)
+ sync_on_next_pps <= 0;
+ else if(pps_ext)
+ sync_on_next_pps <= 0;
+ else if(wb_write & (adr_i[2:0] == 3))
+ sync_on_next_pps <= 1;
always @(posedge sys_clk_i)
if(internal_tick)
@@ -90,11 +115,14 @@
reg pps_in_d1, pps_in_d2;
always @(posedge sys_clk_i)
begin
- pps_in_d1 <= pps_in;
+ pps_in_d1 <= pps_edge ? pps_posedge : pps_negedge;
pps_in_d2 <= pps_in_d1;
end
assign pps_ext = pps_in_d1 & ~pps_in_d2;
+ always @(posedge sys_clk_i)
+ pps_o <= pps_ext;
+
// Need to register this?
reg internal_tick_d1;
always @(posedge sys_clk_i) internal_tick_d1 <= internal_tick;
@@ -102,9 +130,15 @@
always @(posedge wb_clk_i)
if(rst_i)
int_o <= 0;
- else if(tick_int_enable & (internal_tick | internal_tick_d1))
+/*
+ else if(tick_int_enable & (internal_tick | internal_tick_d1))
int_o <= 1;
else
int_o <= 0;
-
+*/
+ always @(posedge sys_clk_i)
+ if(rst_i)
+ epoch_o <= 0;
+ else
+ epoch_o <= (master_time_o[27:0] == 0);
endmodule // time_sync
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_core/u2_core.v
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_core/u2_core.v
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_core/u2_core.v
2008-12-20 02:42:20 UTC (rev 10140)
@@ -3,7 +3,7 @@
//
////////////////////////////////////////////////////////////////////////////////
module u2_core
- #(parameter RAM_SIZE=16384)
+ #(parameter RAM_SIZE=32768)
(// Clocks
input dsp_clk,
input wb_clk,
@@ -123,7 +123,7 @@
output [18:0] RAM_A,
output RAM_CE1n,
output RAM_CENn,
- input RAM_CLK,
+ output RAM_CLK,
output RAM_WEn,
output RAM_OEn,
output RAM_LDn,
@@ -156,25 +156,28 @@
wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full,
eth_rx_full, eth_tx_full, eth_rx_full2;
wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty,
eth_rx_empty, eth_tx_empty, eth_rx_empty2;
+ wire serdes_link_up;
+ wire epoch;
+
//
///////////////////////////////////////////////////////////////////////////////////////////////
// Wishbone Single Master INTERCON
- parameter dw = 32; // Data bus width
- parameter aw = 16; // Address bus width, for byte addressibility, 16 =
64K byte memory space
- parameter sw = 4; // Select width -- 32-bit data bus with 8-bit
granularity.
+ localparam dw = 32; // Data bus width
+ localparam aw = 16; // Address bus width, for byte addressibility, 16 =
64K byte memory space
+ localparam sw = 4; // Select width -- 32-bit data bus with 8-bit
granularity.
wire [dw-1:0] m0_dat_o, m0_dat_i;
wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o,
s2_dat_i, s3_dat_i,
s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o,
s6_dat_i, s7_dat_i,
s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i,
s11_dat_i, s11_dat_o,
- s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o;
- wire [aw-1:0]
m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr,
s13_adr;
- wire [sw-1:0]
m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel,
s13_sel;
- wire
m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack,
s13_ack;
- wire
m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb,
s13_stb;
- wire
m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc,
s13_cyc;
- wire
m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err,
s13_err;
- wire
m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty,
s13_rty;
- wire
m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we;
+ s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i,
s14_dat_o;
+ wire [aw-1:0]
m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr,
s13_adr, s14_adr;
+ wire [sw-1:0]
m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel,
s13_sel, s14_sel;
+ wire
m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack,
s13_ack, s14_ack;
+ wire
m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb,
s13_stb, s14_stb;
+ wire
m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc,
s13_cyc, s14_cyc;
+ wire
m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err,
s13_err, s14_err;
+ wire
m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty,
s13_rty, s14_rty;
+ wire
m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we,
s14_we;
wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10),
.s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10),
@@ -213,7 +216,8 @@
.s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty),
.s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb),
.s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty),
- .s14_dat_i(0),.s14_ack_i(0),.s14_err_i(0),.s14_rty_i(0),
+
.s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb),
+
.s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty),
.s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0) );
//////////////////////////////////////////////////////////////////////////////////////////
@@ -280,6 +284,7 @@
// Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
// I-port connects directly to processor and ram loader
+ wire flush_icache;
ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
@@ -292,11 +297,15 @@
.iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
.dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o),
.dwb_dat_o(s0_dat_i),
- .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb),
.dwb_sel_i(s0_sel));
+ .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb),
.dwb_sel_i(s0_sel),
+ .flush_icache(flush_icache));
assign s0_err = 1'b0;
assign s0_rty = 1'b0;
+ setting_reg #(.my_addr(7)) sr_icache
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+
.in(set_data),.out(),.changed(flush_icache));
+
// Buffer Pool, slave #1
wire rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop;
wire rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop;
@@ -385,7 +394,7 @@
.word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
.word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
-
.word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10({30'b0,clk_func,clk_status}),
+
.word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0),
.word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0)
);
@@ -419,12 +428,26 @@
.in(set_data),.out(serdes_outs),.changed());
setting_reg #(.my_addr(2)) sr_adc
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(adc_outs),.changed());
- setting_reg #(.my_addr(3)) sr_led
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out(leds),.changed());
setting_reg #(.my_addr(4)) sr_phy
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phy_reset),.changed());
// /////////////////////////////////////////////////////////////////////////
+ // LEDS
+ // register 8 determines whether leds are controlled by SW or not
+ // 1 = controlled by HW, 0 = by SW
+ // In Rev3 there are only 6 leds, and the highest one is on the ETH
connector
+
+ wire [7:0] led_src, led_sw;
+ wire [7:0] led_hw = {clk_status,serdes_link_up};
+
+ setting_reg #(.my_addr(3)) sr_led
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(led_sw),.changed());
+ setting_reg #(.my_addr(8)) sr_led_src
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+
.in(set_data),.out(led_src),.changed());
+
+ assign leds = (led_src & led_hw) | (~led_src & led_sw);
+
+ // /////////////////////////////////////////////////////////////////////////
// Ethernet MAC Slave #6
wire Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop;
@@ -476,10 +499,10 @@
// /////////////////////////////////////////////////////////////////////////
// Interrupt Controller, Slave #8
- wire [8:0] irq={{6'b0,uart_tx_int, uart_rx_int},
+ wire [15:0] irq={{4'b0, clk_status, serdes_link_up, uart_tx_int,
uart_rx_int},
{pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}};
- simple_pic #(.is(9),.dwidth(32)) simple_pic
+ simple_pic #(.is(16),.dwidth(32)) simple_pic
(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
.we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
.irq(irq) );
@@ -530,13 +553,21 @@
//
//////////////////////////////////////////////////////////////////////////
// Time Sync, Slave #12
+ reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1;
+ always @(negedge dsp_clk) pps_negedge <= pps_in;
+ always @(posedge dsp_clk) pps_posedge <= pps_in;
+ always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge;
+ always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge;
+
+ wire pps_o;
time_sync time_sync
(.wb_clk_i(wb_clk),.rst_i(wb_rst),
.cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]),
.we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack),
.sys_clk_i(dsp_clk),.master_time_o(master_time),
- .pps_in(pps_in),.exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
- .int_o(pps_int) );
+ .pps_posedge(pps_posedge),.pps_negedge(pps_negedge),
+ .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
+ .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) );
assign s12_err = 0;
assign s12_rty = 0;
@@ -605,66 +636,122 @@
.wr_ready_i(wr0_ready),.wr_full_i(wr0_full),
.tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
.rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
- .debug0(debug_serdes0), .debug1(debug_serdes1) );
+ .serdes_link_up(serdes_link_up),.debug0(debug_serdes0),
.debug1(debug_serdes1) );
//
///////////////////////////////////////////////////////////////////////////////////
// External RAM Interface
- extram_interface extram_interface
- (.clk(dsp_clk),.rst(dsp_rst),
- .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-
.rd_dat_i(rd3_dat),.rd_read_o(rd3_read),.rd_done_o(rd3_done),.rd_error_o(rd3_error),
- .rd_sop_i(rd3_sop),.rd_eop_i(rd3_eop),
-
.wr_dat_o(wr3_dat),.wr_write_o(wr3_write),.wr_done_o(wr3_done),.wr_error_o(wr3_error),
- .wr_ready_i(wr3_ready),.wr_full_i(wr3_full),
- .RAM_D(RAM_D),.RAM_A(RAM_A),.RAM_CE1n(RAM_CE1n),.RAM_CENn(RAM_CENn),
- .RAM_CLK(RAM_CLK),.RAM_WEn(RAM_WEn),.RAM_OEn(RAM_OEn),.RAM_LDn(RAM_LDn)
);
+ localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes
-
+ wire [15:0] bus2ram, ram2bus;
+ wire [15:0] bridge_adr;
+ wire [1:0] bridge_sel;
+ wire bridge_stb, bridge_cyc, bridge_we, bridge_ack;
+
+ wire [19:0] page;
+ wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]};
+ setting_reg #(.my_addr(6)) sr_page
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(page),.changed());
+
+ wb_bridge_16_32 bridge
+ (.wb_clk(wb_clk),.wb_rst(wb_rst),
+ .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel),
+
.A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack),
+
.B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel),
+
.B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack));
+
+ wb_zbt16_b wb_zbt16_b
+ (.clk(wb_clk),.rst(wb_rst),
+
.wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel),
+
.wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we),
+ .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn),
+ .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn),
+ .sram_mode(),.sram_zz() );
+
+ assign s14_err = 0; assign s14_rty = 0;
+ assign RAM_CE1n = 0;
+ assign RAM_D[17:16] = 2'bzz;
+
//
/////////////////////////////////////////////////////////////////////////////////////////
// Debug Pins
-
+
// FIFO Level Debugging
- reg [31:0] host_to_dsp_fifo, dsp_to_host_fifo, eth_mac_debug,
serdes_to_dsp_fifo, dsp_to_serdes_fifo;
-
+ reg [31:0]
host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo;
+
always @(posedge dsp_clk)
serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]},
- {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
+ {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
always @(posedge dsp_clk)
dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]},
- {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
-
+ {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
+
always @(posedge dsp_clk)
host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]},
{dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
-
+
always @(posedge dsp_clk)
dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]},
- {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
-
+ {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
+
always @(posedge dsp_clk)
- eth_mac_debug <= {// {eth_tx_full2, eth_tx_empty2, eth_tx_occ2[13:0]},
- // {underrun, overrun, debug_mac0[13:0] },
- {debug_txc[15:0]},
- {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
+ eth_mac_debug <= { { GMII_TX_EN, GMII_RX_DV, debug_txc[13:0]},
+ {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
- wire debug_mux;
+ wire debug_mux;
setting_reg #(.my_addr(5)) sr_debug
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(debug_mux),.changed());
//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo;
- // Assign various commonly used debug buses.
- /*
- wire [31:0] debug_rx_1 =
{uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
- irq[7:0],
- GMII_RXD,
- GMII_TXD};
+ assign debug_clk[0] = wb_clk;
+ assign debug_clk[1] = dsp_clk;
- wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
+ assign debug = 0; //master_time;
+ assign debug_gpio_0={{8'b0},
+ {8'b0},
+ {4'b0,strobe_rx,run_rx,strobe_tx,run_tx},
+
{s12_ack,pps_o,pps_int,epoch,pps_pos_d1,pps_posedge,pps_neg_d1,pps_negedge}};
+ assign debug_gpio_1 = 0;
+endmodule // u2_core
+
+//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
+// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
+
+//assign debug = debug_tx_dsp;
+//assign debug = debug_serdes0;
+
+//assign debug_gpio_0 = 0; //debug_serdes0;
+//assign debug_gpio_1 = 0; //debug_serdes1;
+
+// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success},
+// {8'b0},
+// {3'b0,ram_loader_ack, ram_loader_stb,
ram_loader_we,ram_loader_rst,ram_loader_done },
+//
{cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b}
};
+
+//assign debug = {dac_a,dac_b};
+
+/*
+ assign debug = {{ram_loader_done, takeover, 6'd0},
+ {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso,
sd_mosi},
+ {8'd0},
+ {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached,
cpld_clk, cpld_init_b}}; */
+
+/*assign debug = host_to_dsp_fifo;
+ assign debug_gpio_0 = eth_mac_debug;
+ assign debug_gpio_1 = 0;
+ */
+// Assign various commonly used debug buses.
+/*
+ wire [31:0] debug_rx_1 =
{uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
+ irq[7:0],
+ GMII_RXD,
+ GMII_TXD};
+
+ wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
+
wire [31:0] debug_time = {uart_tx_o, 7'b0,
irq[7:0],
6'b0, GMII_RX_DV, GMII_TX_EN,
@@ -699,28 +786,3 @@
*/
- // Choose actual debug buses
- assign debug_clk[0] = wb_clk;
- assign debug_clk[1] = dsp_clk;
-
- //assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
- // {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
-
- //assign debug = debug_tx_dsp;
- //assign debug = debug_serdes0;
-
- assign debug_gpio_0 = 0; //debug_serdes0;
- assign debug_gpio_1 = 0; //debug_serdes1;
-
-// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success},
- // {8'b0},
- // {3'b0,ram_loader_ack, ram_loader_stb,
ram_loader_we,ram_loader_rst,ram_loader_done },
- //
{cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b}
};
-
- //assign debug = {dac_a,dac_b};
-
- assign debug = {{ram_loader_done, takeover, 6'd0},
- {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int,
sd_clk, sd_csn, sd_miso, sd_mosi},
- {8'd0},
- {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc,
cpld_detached, cpld_clk, cpld_init_b}};
-endmodule // u2_core
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_rev2/Makefile
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_rev2/Makefile
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_rev2/Makefile
2008-12-20 02:42:20 UTC (rev 10140)
@@ -62,7 +62,6 @@
control_lib/dcache.v \
control_lib/decoder_3_8.v \
control_lib/dpram32.v \
-control_lib/extram_interface.v \
control_lib/fifo_2clock.v \
control_lib/fifo_2clock_casc.v \
control_lib/gray2bin.v \
@@ -89,6 +88,7 @@
control_lib/oneshot_2clk.v \
control_lib/sd_spi.v \
control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
coregen/fifo_xlnx_2Kx36_2clk.v \
coregen/fifo_xlnx_2Kx36_2clk.xco \
coregen/fifo_xlnx_512x36_2clk.v \
@@ -120,6 +120,7 @@
eth/rtl/verilog/miim/eth_clockgen.v \
eth/rtl/verilog/miim/eth_outputcontrol.v \
eth/rtl/verilog/miim/eth_shiftreg.v \
+extram/wb_zbt16_b.v \
opencores/8b10b/decode_8b10b.v \
opencores/8b10b/encode_8b10b.v \
opencores/aemb/rtl/verilog/aeMB_bpcu.v \
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_rev2/u2_rev2.v
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_rev2/u2_rev2.v
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_rev2/u2_rev2.v
2008-12-20 02:42:20 UTC (rev 10140)
@@ -75,7 +75,7 @@
input cpld_clk, // AB14 serial clock
input cpld_detached,// V11 unused
output cpld_init_b, // W12 unused dual purpose
- input cpld_misc, // Y12 unused
+ output cpld_misc, // Y12
// ADC
input [13:0] adc_a,
@@ -362,6 +362,8 @@
.cpld_din (cpld_din),
.cpld_clk (cpld_clk),
.cpld_detached (cpld_detached),
+ .cpld_misc (cpld_misc),
+ .cpld_init_b (cpld_init_b),
.por (~POR),
.config_success (config_success),
.adc_a (adc_a_reg2),
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_rev3/Makefile
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_rev3/Makefile
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/fpga/top/u2_rev3/Makefile
2008-12-20 02:42:20 UTC (rev 10140)
@@ -62,7 +62,6 @@
control_lib/dcache.v \
control_lib/decoder_3_8.v \
control_lib/dpram32.v \
-control_lib/extram_interface.v \
control_lib/fifo_2clock.v \
control_lib/fifo_2clock_casc.v \
control_lib/gray2bin.v \
@@ -89,6 +88,7 @@
control_lib/oneshot_2clk.v \
control_lib/sd_spi.v \
control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
coregen/fifo_xlnx_2Kx36_2clk.v \
coregen/fifo_xlnx_2Kx36_2clk.xco \
coregen/fifo_xlnx_512x36_2clk.v \
@@ -120,6 +120,7 @@
eth/rtl/verilog/miim/eth_clockgen.v \
eth/rtl/verilog/miim/eth_outputcontrol.v \
eth/rtl/verilog/miim/eth_shiftreg.v \
+extram/wb_zbt16_b.v \
opencores/8b10b/decode_8b10b.v \
opencores/8b10b/encode_8b10b.v \
opencores/aemb/rtl/verilog/aeMB_bpcu.v \
Modified:
gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/include/usrp2/usrp2.h
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/include/usrp2/usrp2.h
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/include/usrp2/usrp2.h
2008-12-20 02:42:20 UTC (rev 10140)
@@ -23,12 +23,17 @@
#include <boost/utility.hpp>
#include <vector>
#include <complex>
-//#include <iosfwd>
#include <usrp2/rx_sample_handler.h>
#include <usrp2/tune_result.h>
-#include <usrp2/rx_sample_handler.h>
+/*
+ * N.B., The interfaces described here are still in flux.
+ *
+ * We will keep all the code in the tree up-to-date with regard to changes
+ * here, but reserve the right to change this on a whim.
+ */
+
namespace usrp2 {
/*!
@@ -89,14 +94,6 @@
*/
std::string mac_addr();
- /*!
- * Burn new mac address into EEPROM on USRP2
- *
- * \param new_addr Network mac address, e.g., "01:23:45:67:89:ab" or
"89:ab".
- * If \p addr is HH:HH, it's treated as if it were
00:50:c2:85:HH:HH
- */
- bool burn_mac_addr(const std::string &new_addr);
-
/*
* ----------------------------------------------------------------
* Rx configuration and control
@@ -105,19 +102,38 @@
/*!
* Set receiver gain
+ * \param gain in dB (more or less)
*/
bool set_rx_gain(double gain);
+ //! return minimum Rx gain
+ double rx_gain_min();
+
+ //! return maximum Rx gain
+ double rx_gain_max();
+
+ //! return Rx gain db_per_step
+ double rx_gain_db_per_step();
+
/*!
* Set receiver center frequency
*/
bool set_rx_center_freq(double frequency, tune_result *result);
+ //! return minimum Rx center frequency
+ double rx_freq_min();
+
+ //! return maximum Rx center frequency
+ double rx_freq_max();
+
/*!
* Set receiver sample rate decimation
*/
bool set_rx_decim(int decimation_factor);
+ //! Return current decimation factor
+ int rx_decim();
+
/*!
* Set receiver IQ magnitude scaling
*/
@@ -175,16 +191,34 @@
*/
bool set_tx_gain(double gain);
+ //! return minimum Tx gain
+ double tx_gain_min();
+
+ //! return maximum Tx gain
+ double tx_gain_max();
+
+ //! return Tx gain db_per_step
+ double tx_gain_db_per_step();
+
/*!
* Set transmitter center frequency
*/
bool set_tx_center_freq(double frequency, tune_result *result);
+ //! return minimum Tx center frequency
+ double tx_freq_min();
+
+ //! return maximum Tx center frequency
+ double tx_freq_max();
+
/*!
* Set transmitter sample rate interpolation
*/
bool set_tx_interp(int interpolation_factor);
+ //! Return current interpolation factor
+ int tx_interp();
+
/*!
* Set transmit IQ magnitude scaling
*/
@@ -253,7 +287,11 @@
size_t nitems,
const tx_metadata *metadata);
- // ----------------------------------------------------------------
+ /*
+ * ----------------------------------------------------------------
+ * miscellaneous methods
+ * ----------------------------------------------------------------
+ */
/*!
* \brief MIMO configuration
@@ -274,6 +312,126 @@
*/
bool config_mimo(int flags);
+
+ //! Get frequency of master oscillator in Hz
+ bool fpga_master_clock_freq(long *freq);
+
+ // Get Sampling rate of A/D converter in Hz
+ bool adc_rate(long *rate);
+
+ // Get Sampling rate of D/A converter in Hz
+ bool dac_rate(long *rate);
+
+ /*!
+ * \brief Get Tx daughterboard ID
+ *
+ * \param[out] dbid returns the daughterboard id.
+ *
+ * daughterboard id >= 0 if successful, -1 if no daugherboard installed,
+ * -2 if invalid EEPROM on daughterboard.
+ */
+ bool tx_daughterboard_id(int *dbid);
+
+ /*!
+ * \brief Get Rx daughterboard ID
+ *
+ * \param[out] dbid returns the daughterboard id.
+ *
+ * daughterboard id >= 0 if successful, -1 if no daugherboard installed,
+ * -2 if invalid EEPROM on daughterboard.
+ */
+ bool rx_daughterboard_id(int *dbid);
+
+ /*
+ * ----------------------------------------------------------------
+ * Low level methods
+ * ----------------------------------------------------------------
+ */
+
+ /*!
+ * Burn new mac address into EEPROM on USRP2
+ *
+ * \param new_addr Network mac address, e.g., "01:23:45:67:89:ab" or
"89:ab".
+ * If \p addr is HH:HH, it's treated as if it were
00:50:c2:85:HH:HH
+ */
+ bool burn_mac_addr(const std::string &new_addr);
+
+ /*!
+ * Reset master time to 0 at next PPS rising edge
+ */
+ bool sync_to_pps();
+
+#if 0 // not yet implemented
+ /*!
+ * \brief Write EEPROM on motherboard or any daughterboard.
+ * \param i2c_addr I2C bus address of EEPROM
+ * \param eeprom_offset byte offset in EEPROM to begin writing
+ * \param buf the data to write
+ * \returns true iff sucessful
+ */
+ bool write_eeprom (int i2c_addr, int eeprom_offset, const std::string
&buf);
+
+ /*!
+ * \brief Read EEPROM on motherboard or any daughterboard.
+ * \param i2c_addr I2C bus address of EEPROM
+ * \param eeprom_offset byte offset in EEPROM to begin reading
+ * \param len number of bytes to read
+ * \returns the data read if successful, else a zero length string.
+ */
+ std::string read_eeprom (int i2c_addr, int eeprom_offset, int len);
+
+ /*!
+ * \brief Write to I2C peripheral
+ * \param i2c_addr I2C bus address (7-bits)
+ * \param buf the data to write
+ * \returns true iff successful
+ * Writes are limited to a maximum of of 64 bytes.
+ */
+ bool write_i2c (int i2c_addr, const std::string &buf);
+
+ /*!
+ * \brief Read from I2C peripheral
+ * \param i2c_addr I2C bus address (7-bits)
+ * \param len number of bytes to read
+ * \returns the data read if successful, else a zero length string.
+ * Reads are limited to a maximum of 64 bytes.
+ */
+ std::string read_i2c (int i2c_addr, int len);
+
+ /*!
+ * \brief Write data to SPI bus peripheral.
+ *
+ * \param optional_header 0,1 or 2 bytes to write before buf.
+ * \param enables bitmask of peripherals to write. See
usrp_spi_defs.h
+ * \param format transaction format. See usrp_spi_defs.h
SPI_FMT_*
+ * \param buf the data to write
+ * \returns true iff successful
+ * Writes are limited to a maximum of 64 bytes.
+ *
+ * If \p format specifies that optional_header bytes are present, they are
+ * written to the peripheral immediately prior to writing \p buf.
+ */
+ bool write_spi (int optional_header, int enables, int format, const
std::string &buf);
+
+ /*
+ * \brief Read data from SPI bus peripheral.
+ *
+ * \param optional_header 0,1 or 2 bytes to write before buf.
+ * \param enables bitmask of peripheral to read. See
usrp_spi_defs.h
+ * \param format transaction format. See usrp_spi_defs.h
SPI_FMT_*
+ * \param len number of bytes to read. Must be in [0,64].
+ * \returns the data read if sucessful, else a zero length string.
+ *
+ * Reads are limited to a maximum of 64 bytes.
+ *
+ * If \p format specifies that optional_header bytes are present, they
+ * are written to the peripheral first. Then \p len bytes are read from
+ * the peripheral and returned.
+ */
+ std::string read_spi (int optional_header, int enables, int format, int
len);
+#endif
+
+
class impl; // implementation details
private:
Modified: gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/control.h
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/control.h
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/control.h
2008-12-20 02:42:20 UTC (rev 10140)
@@ -53,6 +53,13 @@
op_generic_t eop;
};
+ struct op_config_mimo_cmd
+ {
+ u2_eth_packet_t h;
+ op_config_mimo_t op;
+ op_generic_t eop;
+ };
+
struct op_burn_mac_addr_cmd
{
u2_eth_packet_t h;
@@ -60,6 +67,13 @@
op_generic_t eop;
};
+ struct op_dboard_info_cmd {
+ u2_eth_packet_t h;
+ op_generic_t op;
+ op_generic_t eop;
+ };
+
+
/*!
* Control mechanism to allow API calls to block waiting for reply packets
*/
Modified: gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/usrp2.cc
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/usrp2.cc
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/usrp2.cc
2008-12-20 02:42:20 UTC (rev 10140)
@@ -160,13 +160,6 @@
return d_impl->mac_addr();
}
- bool
- usrp2::burn_mac_addr(const std::string &new_addr)
- {
- return d_impl->burn_mac_addr(new_addr);
- }
-
-
// Receive
bool
@@ -175,18 +168,54 @@
return d_impl->set_rx_gain(gain);
}
+ double
+ usrp2::rx_gain_min()
+ {
+ return d_impl->rx_gain_min();
+ }
+
+ double
+ usrp2::rx_gain_max()
+ {
+ return d_impl->rx_gain_max();
+ }
+
+ double
+ usrp2::rx_gain_db_per_step()
+ {
+ return d_impl->rx_gain_db_per_step();
+ }
+
bool
usrp2::set_rx_center_freq(double frequency, tune_result *result)
{
return d_impl->set_rx_center_freq(frequency, result);
}
+ double
+ usrp2::rx_freq_min()
+ {
+ return d_impl->rx_freq_min();
+ }
+
+ double
+ usrp2::rx_freq_max()
+ {
+ return d_impl->rx_freq_max();
+ }
+
bool
usrp2::set_rx_decim(int decimation_factor)
{
return d_impl->set_rx_decim(decimation_factor);
}
+ int
+ usrp2::rx_decim()
+ {
+ return d_impl->rx_decim();
+ }
+
bool
usrp2::set_rx_scale_iq(int scale_i, int scale_q)
{
@@ -231,18 +260,55 @@
return d_impl->set_tx_gain(gain);
}
+ double
+ usrp2::tx_gain_min()
+ {
+ return d_impl->tx_gain_min();
+ }
+
+ double
+ usrp2::tx_gain_max()
+ {
+ return d_impl->tx_gain_max();
+ }
+
+ double
+ usrp2::tx_gain_db_per_step()
+ {
+ return d_impl->tx_gain_db_per_step();
+ }
+
bool
usrp2::set_tx_center_freq(double frequency, tune_result *result)
{
return d_impl->set_tx_center_freq(frequency, result);
}
+ double
+ usrp2::tx_freq_min()
+ {
+ return d_impl->tx_freq_min();
+ }
+
+ double
+ usrp2::tx_freq_max()
+ {
+ return d_impl->tx_freq_max();
+ }
+
+
bool
usrp2::set_tx_interp(int interpolation_factor)
{
return d_impl->set_tx_interp(interpolation_factor);
}
+ int
+ usrp2::tx_interp()
+ {
+ return d_impl->tx_interp();
+ }
+
bool
usrp2::set_tx_scale_iq(int scale_i, int scale_q)
{
@@ -276,6 +342,59 @@
return d_impl->tx_raw(channel, items, nitems, metadata);
}
+ // miscellaneous methods
+
+ bool
+ usrp2::config_mimo(int flags)
+ {
+ return d_impl->config_mimo(flags);
+ }
+
+ bool
+ usrp2::fpga_master_clock_freq(long *freq)
+ {
+ return d_impl->fpga_master_clock_freq(freq);
+ }
+
+ bool
+ usrp2::adc_rate(long *rate)
+ {
+ return d_impl->adc_rate(rate);
+ }
+
+ bool
+ usrp2::dac_rate(long *rate)
+ {
+ return d_impl->dac_rate(rate);
+ }
+
+ bool
+ usrp2::tx_daughterboard_id(int *dbid)
+ {
+ return d_impl->tx_daughterboard_id(dbid);
+ }
+
+ bool
+ usrp2::rx_daughterboard_id(int *dbid)
+ {
+ return d_impl->rx_daughterboard_id(dbid);
+ }
+
+
+ // low level methods
+
+ bool
+ usrp2::burn_mac_addr(const std::string &new_addr)
+ {
+ return d_impl->burn_mac_addr(new_addr);
+ }
+
+ bool
+ usrp2::sync_to_pps()
+ {
+ return d_impl->sync_to_pps();
+ }
+
} // namespace usrp2
Modified: gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/usrp2_impl.cc
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/usrp2_impl.cc
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/usrp2_impl.cc
2008-12-20 02:42:20 UTC (rev 10140)
@@ -68,6 +68,10 @@
case OP_CONFIG_TX_REPLY_V2: return "OP_CONFIG_TX_REPLY_V2";
case OP_START_RX_STREAMING: return "OP_START_RX_STREAMING";
case OP_STOP_RX: return "OP_STOP_RX";
+ case OP_CONFIG_MIMO: return "OP_CONFIG_MIMO";
+ case OP_DBOARD_INFO: return "OP_DBOARD_INFO";
+ case OP_DBOARD_INFO_REPLY: return "OP_DBOARD_INFO_REPLY";
+ case OP_SYNC_TO_PPS: return "OP_SYNC_TO_PPS";
#if 0
case OP_WRITE_REG: return "OP_WRITE_REG";
case OP_WRITE_REG_MASKED: return "OP_WRITE_REG_MASKED";
@@ -105,9 +109,13 @@
md->word0 = u2p_word0(fh);
md->timestamp = u2p_timestamp(fh);
+ // FIXME when we've got more info
// md->start_of_burst = (md->word0 & XXX) != 0;
// md->end_of_burst = (md->word0 & XXX) != 0;
// md->rx_overrun = (md->word0 & XXX) != 0;
+ md->start_of_burst = 0;
+ md->end_of_burst = 0;
+ md->rx_overrun = 0;
*items = (uint32_t *)(&fh[1]);
size_t nbytes = payload_len_in_bytes - sizeof(u2_fixed_hdr_t);
@@ -120,10 +128,10 @@
usrp2::impl::impl(const std::string &ifc, props *p)
: d_eth_buf(new eth_buffer()), d_pf(0), d_bg_thread(0),
d_bg_running(false),
- d_rx_decim(0), d_rx_seqno(-1), d_tx_seqno(0), d_next_rid(0),
+ d_rx_seqno(-1), d_tx_seqno(0), d_next_rid(0),
d_num_rx_frames(0), d_num_rx_missing(0), d_num_rx_overruns(0),
d_num_rx_bytes(0),
d_num_enqueued(0), d_enqueued_mutex(),
d_bg_pending_cond(&d_enqueued_mutex),
- d_channel_rings(NCHANS)
+ d_channel_rings(NCHANS), d_tx_interp(0), d_rx_decim(0)
{
if (!d_eth_buf->open(ifc, htons(U2_ETHERTYPE)))
throw std::runtime_error("Unable to register USRP2 protocol");
@@ -142,6 +150,43 @@
d_bg_thread = new usrp2_thread(this);
d_bg_thread->start();
+ if (!dboard_info()) // we're hosed
+ throw std::runtime_error("Unable to retrieve daughterboard info");
+
+ if (0){
+ int dbid;
+
+ tx_daughterboard_id(&dbid);
+ fprintf(stderr, "Tx dboard 0x%x\n", dbid);
+ fprintf(stderr, " freq_min = %g\n", tx_freq_min());
+ fprintf(stderr, " freq_max = %g\n", tx_freq_max());
+ fprintf(stderr, " gain_min = %g\n", tx_gain_min());
+ fprintf(stderr, " gain_max = %g\n", tx_gain_max());
+ fprintf(stderr, " gain_db_per_step = %g\n", tx_gain_db_per_step());
+
+ rx_daughterboard_id(&dbid);
+ fprintf(stderr, "Rx dboard 0x%x\n", dbid);
+ fprintf(stderr, " freq_min = %g\n", rx_freq_min());
+ fprintf(stderr, " freq_max = %g\n", rx_freq_max());
+ fprintf(stderr, " gain_min = %g\n", rx_gain_min());
+ fprintf(stderr, " gain_max = %g\n", rx_gain_max());
+ fprintf(stderr, " gain_db_per_step = %g\n", rx_gain_db_per_step());
+ }
+
+ // default gains to mid point
+ if (!set_tx_gain((tx_gain_min() + tx_gain_max()) / 2))
+ std::cerr << "usrp2::ctor set_tx_gain failed\n";
+
+ if (!set_rx_gain((rx_gain_min() + rx_gain_max()) / 2))
+ std::cerr << "usrp2::ctor set_rx_gain failed\n";
+
+ // default interp and decim
+ if (!set_tx_interp(12))
+ std::cerr << "usrp2::ctor set_tx_interp failed\n";
+
+ if (!set_rx_decim(12))
+ std::cerr << "usrp2::ctor set_rx_decim failed\n";
+
// set workable defaults for scaling
if (!set_rx_scale_iq(DEFAULT_RX_SCALE, DEFAULT_RX_SCALE))
std::cerr << "usrp2::ctor set_rx_scale_iq failed\n";
@@ -412,33 +457,6 @@
// ----------------------------------------------------------------
- // misc commands
- // ----------------------------------------------------------------
-
- bool
- usrp2::impl::burn_mac_addr(const std::string &new_addr)
- {
- op_burn_mac_addr_cmd cmd;
- op_generic_t reply;
-
- memset(&cmd, 0, sizeof(cmd));
- init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
- cmd.op.opcode = OP_BURN_MAC_ADDR;
- cmd.op.len = sizeof(cmd.op);
- cmd.op.rid = d_next_rid++;
- if (!parse_mac_addr(new_addr, &cmd.op.addr))
- return false;
-
- pending_reply p(cmd.op.rid, &reply, sizeof(reply));
- if (!transmit_cmd(&cmd, sizeof(cmd), &p, 4*DEF_CMD_TIMEOUT))
- return false;
-
- bool success = (ntohx(reply.ok) == 1);
- return success;
- }
-
-
- // ----------------------------------------------------------------
// Receive
// ----------------------------------------------------------------
@@ -514,6 +532,8 @@
return false;
bool success = (ntohx(reply.ok) == 1);
+ if (success)
+ d_rx_decim = decimation_factor;
return success;
}
@@ -751,6 +771,8 @@
return false;
bool success = (ntohx(reply.ok) == 1);
+ if (success)
+ d_tx_interp = interpolation_factor;
return success;
}
@@ -870,5 +892,154 @@
return true;
}
+ // ----------------------------------------------------------------
+ // misc commands
+ // ----------------------------------------------------------------
+ bool
+ usrp2::impl::config_mimo(int flags)
+ {
+ op_config_mimo_cmd cmd;
+ op_generic_t reply;
+
+ memset(&cmd, 0, sizeof(cmd));
+ init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
+ cmd.op.opcode = OP_CONFIG_MIMO;
+ cmd.op.len = sizeof(cmd.op);
+ cmd.op.rid = d_next_rid++;
+ cmd.eop.opcode = OP_EOP;
+ cmd.eop.len = sizeof(cmd.eop);
+
+ pending_reply p(cmd.op.rid, &reply, sizeof(reply));
+ if (!transmit_cmd(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
+ return false;
+
+ return ntohx(reply.ok) == 1;
+ }
+
+ bool
+ usrp2::impl::fpga_master_clock_freq(long *freq)
+ {
+ *freq = 100000000L; // 100 MHz
+ return true;
+ }
+
+ bool
+ usrp2::impl::adc_rate(long *rate)
+ {
+ return fpga_master_clock_freq(rate);
+ }
+
+ bool
+ usrp2::impl::dac_rate(long *rate)
+ {
+ return fpga_master_clock_freq(rate);
+ }
+
+ bool
+ usrp2::impl::tx_daughterboard_id(int *dbid)
+ {
+ *dbid = d_tx_db_info.dbid;
+ return true;
+ }
+
+ bool
+ usrp2::impl::rx_daughterboard_id(int *dbid)
+ {
+ *dbid = d_rx_db_info.dbid;
+ return true;
+ }
+
+
+ // ----------------------------------------------------------------
+ // low-level commands
+ // ----------------------------------------------------------------
+
+ bool
+ usrp2::impl::burn_mac_addr(const std::string &new_addr)
+ {
+ op_burn_mac_addr_cmd cmd;
+ op_generic_t reply;
+
+ memset(&cmd, 0, sizeof(cmd));
+ init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
+ cmd.op.opcode = OP_BURN_MAC_ADDR;
+ cmd.op.len = sizeof(cmd.op);
+ cmd.op.rid = d_next_rid++;
+ if (!parse_mac_addr(new_addr, &cmd.op.addr))
+ return false;
+
+ pending_reply p(cmd.op.rid, &reply, sizeof(reply));
+ if (!transmit_cmd(&cmd, sizeof(cmd), &p, 4*DEF_CMD_TIMEOUT))
+ return false;
+
+ bool success = (ntohx(reply.ok) == 1);
+ return success;
+ }
+
+ static void
+ fill_dboard_info(db_info *dst, const u2_db_info_t *src)
+ {
+ dst->dbid = ntohl(src->dbid);
+
+ dst->freq_min =
+ u2_fxpt_freq_to_double(u2_fxpt_freq_from_hilo(ntohl(src->freq_min_hi),
+ ntohl(src->freq_min_lo)));
+ dst->freq_max =
+ u2_fxpt_freq_to_double(u2_fxpt_freq_from_hilo(ntohl(src->freq_max_hi),
+ ntohl(src->freq_max_lo)));
+
+ dst->gain_min = u2_fxpt_gain_to_double(ntohs(src->gain_min));
+ dst->gain_max = u2_fxpt_gain_to_double(ntohs(src->gain_max));
+ dst->gain_step_size = u2_fxpt_gain_to_double(ntohs(src->gain_step_size));
+ }
+
+ bool
+ usrp2::impl::dboard_info()
+ {
+ op_dboard_info_cmd cmd;
+ op_dboard_info_reply_t reply;
+
+ memset(&cmd, 0, sizeof(cmd));
+ init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
+ cmd.op.opcode = OP_DBOARD_INFO;
+ cmd.op.len = sizeof(cmd.op);
+ cmd.op.rid = d_next_rid++;
+ cmd.eop.opcode = OP_EOP;
+ cmd.eop.len = sizeof(cmd.eop);
+
+ pending_reply p(cmd.op.rid, &reply, sizeof(reply));
+ if (!transmit_cmd(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
+ return false;
+
+ bool success = (ntohx(reply.ok) == 1);
+ if (success){
+ fill_dboard_info(&d_tx_db_info, &reply.tx_db_info);
+ fill_dboard_info(&d_rx_db_info, &reply.rx_db_info);
+ }
+ return success;
+ }
+
+
+ bool
+ usrp2::impl::sync_to_pps()
+ {
+ op_config_mimo_cmd cmd;
+ op_generic_t reply;
+
+ memset(&cmd, 0, sizeof(cmd));
+ init_etf_hdrs(&cmd.h, d_addr, 0, CONTROL_CHAN, -1);
+ cmd.op.opcode = OP_SYNC_TO_PPS;
+ cmd.op.len = sizeof(cmd.op);
+ cmd.op.rid = d_next_rid++;
+ cmd.eop.opcode = OP_EOP;
+ cmd.eop.len = sizeof(cmd.eop);
+
+ pending_reply p(cmd.op.rid, &reply, sizeof(reply));
+ if (!transmit_cmd(&cmd, sizeof(cmd), &p, DEF_CMD_TIMEOUT))
+ return false;
+
+ return ntohx(reply.ok) == 1;
+ }
+
} // namespace usrp2
Modified: gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/usrp2_impl.h
===================================================================
--- gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/usrp2_impl.h
2008-12-20 02:41:31 UTC (rev 10139)
+++ gnuradio/branches/developers/n4hy/pfb_fbs/usrp2/host/lib/usrp2_impl.h
2008-12-20 02:42:20 UTC (rev 10140)
@@ -36,6 +36,19 @@
class pending_reply;
class ring;
+ //! High-level d'board info
+ struct db_info {
+ int dbid;
+ double freq_min; // Hz
+ double freq_max; // Hz
+ double gain_min; // dB
+ double gain_max; // dB
+ double gain_step_size; // dB
+
+ db_info() : dbid(-1), freq_min(0), freq_max(0),
+ gain_min(0), gain_max(0), gain_step_size(0) {}
+ };
+
class usrp2::impl : private data_handler
{
static const size_t NRIDS = 256;
@@ -47,7 +60,6 @@
usrp2_thread *d_bg_thread;
volatile bool d_bg_running; // TODO: multistate if needed
- int d_rx_decim;
int d_rx_seqno;
int d_tx_seqno;
int d_next_rid;
@@ -65,6 +77,12 @@
std::vector<ring_sptr> d_channel_rings; // indexed by 5-bit channel
number
+ db_info d_tx_db_info;
+ db_info d_rx_db_info;
+
+ int d_tx_interp; // shadow tx interp
+ int d_rx_decim; // shadow rx decim
+
void inc_enqueued() {
omni_mutex_lock l(d_enqueued_mutex);
d_num_enqueued++;
@@ -87,6 +105,7 @@
virtual data_handler::result operator()(const void *base, size_t len);
data_handler::result handle_control_packet(const void *base, size_t len);
data_handler::result handle_data_packet(const void *base, size_t len);
+ bool dboard_info();
public:
impl(const std::string &ifc, props *p);
@@ -95,11 +114,18 @@
void bg_loop();
std::string mac_addr() const { return d_addr; } // FIXME: convert from
u2_mac_addr_t
- bool burn_mac_addr(const std::string &new_addr);
+ // Rx
+
bool set_rx_gain(double gain);
+ double rx_gain_min() { return d_rx_db_info.gain_min; }
+ double rx_gain_max() { return d_rx_db_info.gain_max; }
+ double rx_gain_db_per_step() { return d_rx_db_info.gain_step_size; }
bool set_rx_center_freq(double frequency, tune_result *result);
+ double rx_freq_min() { return d_rx_db_info.freq_min; }
+ double rx_freq_max() { return d_rx_db_info.freq_max; }
bool set_rx_decim(int decimation_factor);
+ int rx_decim() { return d_rx_decim; }
bool set_rx_scale_iq(int scale_i, int scale_q);
bool start_rx_streaming(unsigned int channel, unsigned int
items_per_frame);
bool rx_samples(unsigned int channel, rx_sample_handler *handler);
@@ -107,9 +133,17 @@
unsigned int rx_overruns() const { return d_num_rx_overruns; }
unsigned int rx_missing() const { return d_num_rx_missing; }
+ // Tx
+
bool set_tx_gain(double gain);
+ double tx_gain_min() { return d_tx_db_info.gain_min; }
+ double tx_gain_max() { return d_tx_db_info.gain_max; }
+ double tx_gain_db_per_step() { return d_tx_db_info.gain_step_size; }
bool set_tx_center_freq(double frequency, tune_result *result);
+ double tx_freq_min() { return d_tx_db_info.freq_min; }
+ double tx_freq_max() { return d_tx_db_info.freq_max; }
bool set_tx_interp(int interpolation_factor);
+ int tx_interp() { return d_tx_interp; }
bool set_tx_scale_iq(int scale_i, int scale_q);
bool tx_32fc(unsigned int channel,
@@ -126,6 +160,20 @@
const uint32_t *items,
size_t nitems,
const tx_metadata *metadata);
+
+ // misc
+
+ bool config_mimo(int flags);
+ bool fpga_master_clock_freq(long *freq);
+ bool adc_rate(long *rate);
+ bool dac_rate(long *rate);
+ bool tx_daughterboard_id(int *dbid);
+ bool rx_daughterboard_id(int *dbid);
+
+ // low level
+
+ bool burn_mac_addr(const std::string &new_addr);
+ bool sync_to_pps();
};
} // namespace usrp2
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- [Commit-gnuradio] r10140 - in gnuradio/branches/developers/n4hy/pfb_fbs/usrp2: firmware firmware/apps firmware/include firmware/lib fpga/control_lib fpga/extram fpga/sdr_lib fpga/serdes fpga/timing fpga/top/u2_core fpga/top/u2_rev2 fpga/top/u2_rev3 host/include/usrp2 host/lib,
n4hy <=