[Commit-gnuradio] r10120 - in gnuradio/trunk/usrp2/fpga: timing top/u2_core

[matt]

Author: matt
Date: 2008-12-14 21:26:43 -0700 (Sun, 14 Dec 2008)
New Revision: 10120

Modified:
   gnuradio/trunk/usrp2/fpga/timing/time_sync.v
   gnuradio/trunk/usrp2/fpga/top/u2_core/u2_core.v
Log:
pps sync works, meets timing


Modified: gnuradio/trunk/usrp2/fpga/timing/time_sync.v
===================================================================
--- gnuradio/trunk/usrp2/fpga/timing/time_sync.v        2008-12-14 19:47:11 UTC 
(rev 10119)
+++ gnuradio/trunk/usrp2/fpga/timing/time_sync.v        2008-12-15 04:26:43 UTC 
(rev 10120)
@@ -5,8 +5,11 @@
    input cyc_i, input stb_i, input [2:0] adr_i,
    input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o,
    input sys_clk_i, output [31:0] master_time_o,
-   input pps_in, input exp_pps_in, output exp_pps_out,
-   output reg int_o );
+   input pps_posedge, input pps_negedge, 
+   input exp_pps_in, output exp_pps_out,
+   output reg int_o,
+   output reg epoch_o,
+   output reg pps_o );
    
    wire [31:0] master_time_rcvd;
    reg [31:0]  master_time;
@@ -19,6 +22,7 @@
    reg                tick_int_enable, tick_source, external_sync;
    reg [31:0]  tick_interval;
    reg                sync_on_next_pps;
+   reg                pps_edge;
    
    // Generate master time
    always @(posedge sys_clk_i)
@@ -57,6 +61,7 @@
          external_sync <= 0;
          tick_interval <= 100000-1;  // default to 1K times per second
          delta_time <= 0;
+         pps_edge <= 0;
        end
      else if(wb_write)
        case(adr_i[2:0])
@@ -65,6 +70,7 @@
              tick_source <= dat_i[0];
              tick_int_enable <= dat_i[1];
              external_sync <= dat_i[2];
+             pps_edge <= dat_i[3];
           end
         3'd1 :
           tick_interval <= dat_i;
@@ -81,7 +87,7 @@
      else if(pps_ext)
        sync_on_next_pps <= 0;
      else if(wb_write & (adr_i[2:0] == 3))
-       sync_on_next_pps <= 0;
+       sync_on_next_pps <= 1;
    
    always @(posedge sys_clk_i)
      if(internal_tick)
@@ -109,11 +115,14 @@
    reg               pps_in_d1, pps_in_d2;
    always @(posedge sys_clk_i)
      begin
-       pps_in_d1 <= pps_in;
+       pps_in_d1 <= pps_edge ? pps_posedge : pps_negedge;
        pps_in_d2 <= pps_in_d1;
      end
    assign pps_ext = pps_in_d1 & ~pps_in_d2;
 
+   always @(posedge sys_clk_i)
+     pps_o <= pps_ext;
+   
    // Need to register this?
    reg           internal_tick_d1;
    always @(posedge sys_clk_i) internal_tick_d1 <= internal_tick;
@@ -121,9 +130,15 @@
    always @(posedge wb_clk_i)
      if(rst_i)
        int_o <= 0;
-     else if(tick_int_enable & (internal_tick | internal_tick_d1))
+/*
+      else if(tick_int_enable & (internal_tick | internal_tick_d1))
        int_o <= 1;
      else
        int_o <= 0;
-   
+*/
+   always @(posedge sys_clk_i)
+     if(rst_i)
+       epoch_o <= 0;
+     else
+       epoch_o <= (master_time_o[27:0] == 0);
 endmodule // time_sync

Modified: gnuradio/trunk/usrp2/fpga/top/u2_core/u2_core.v
===================================================================
--- gnuradio/trunk/usrp2/fpga/top/u2_core/u2_core.v     2008-12-14 19:47:11 UTC 
(rev 10119)
+++ gnuradio/trunk/usrp2/fpga/top/u2_core/u2_core.v     2008-12-15 04:26:43 UTC 
(rev 10120)
@@ -565,11 +565,9 @@
       .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]),
       .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack),
       .sys_clk_i(dsp_clk),.master_time_o(master_time),
-      //.pps_posedge(pps_posedge),.pps_negedge(pps_negedge),
-      .pps_in(pps_negedge),
+      .pps_posedge(pps_posedge),.pps_negedge(pps_negedge),
       .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
-      //.int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) );
-      .int_o(pps_int));
+      .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) );
    assign       s12_err = 0;
    assign       s12_rty = 0;
 
@@ -710,11 +708,11 @@
    assign      debug_clk[0] = wb_clk;
    assign      debug_clk[1] = dsp_clk; 
    
-   assign      debug = 0; 
+   assign      debug = 0; //master_time; 
    assign      debug_gpio_0={{8'b0},
                             {8'b0},
-                            {8'b0},
-                            
{1'b0,pps_o,pps_int,epoch,pps_pos_d1,pps_posedge,pps_neg_d1,pps_negedge}};
+                            {4'b0,strobe_rx,run_rx,strobe_tx,run_tx},
+                            
{s12_ack,pps_o,pps_int,epoch,pps_pos_d1,pps_posedge,pps_neg_d1,pps_negedge}};
    assign      debug_gpio_1 = 0;
    
 endmodule // u2_core