Re: SIGSTKSZ is now a run-time variable

From:

Carol Bouchard

Subject:

Date:

Fri, 26 Mar 2021 08:46:14 -0400

M4 Experts:

Since this issue seems to be in a standstill, I've put together a patch that I can use locally.

I'm seeking input for this patch I've produced for m4 package. I'd appreciate your thoughts.

Carol

On Tue, Mar 16, 2021 at 3:46 PM Carol Bouchard <cbouchar@redhat.com> wrote:

Folks:

I misstated earlier that the latest Fedora is going in this direction. This appears to be a glibc only issue as my build is pulling in glibc and not playing nicely with m4.
According to https://pkgs.org/download/glibc-devel, fedora rawhide is pulling in the latest version glibc-devel 2.33.
I'm wondering if there is a short-term work-around I can use.

Carol

On Tue, Mar 9, 2021 at 4:30 PM Scott Lurndal <slurndal@sonic.net> wrote:
On Tue, Mar 09, 2021 at 08:58:38PM +0100, Bruno Haible via austin-group-l at The Open Group wrote:
> Eric Blake wrote:
> > I can open a defect against POSIX if we decide that is needed, but want
> > some consensus first on whether it is glibc's change that went too far,
> > or POSIX's requirements that are too restrictive for what glibc wants to do.
>
> Thanks for opening the discussion, Eric.
>
> Here are a couple of questions, to understand the motivation and the possible
> alternative solutions to the problem:
>
> 1) As far as I understand, the issue occurs with certain x86 or x86_64
> processors.
>
> 1.1) What has been the value of MINSIGSTKSZ on x86 and x86_64 so far?
> 1.2) What value of MINSIGSTKSZ is needed for AVX-512F support?
> 1.3) Will the trend to larger MINSIGSTKSZ values continue for Intel
> processors?

It's not just Intel processors.

64-bit ARM processors that support scalable vectors (SVE) support
vectors of up to 2084 bits, and they have 32 vector registers which would
require 8Kbytes for the SVE state alone if the implementation supports
the full 2kbits.

scott